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e2211743 | 1 | /* |
414eec35 | 2 | * (C) Copyright 2000-2005 |
e2211743 WD |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific | |
26 | */ | |
27 | ||
28 | #ifndef __CONFIG_H | |
29 | #define __CONFIG_H | |
30 | ||
31 | /* | |
32 | * High Level Configuration Options | |
33 | * (easy to change) | |
34 | */ | |
35 | ||
36 | #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ | |
37 | #define CONFIG_IP860 1 /* ...on a IP860 board */ | |
c837dcb1 | 38 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ |
e2211743 WD |
39 | |
40 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
41 | #define CONFIG_BAUDRATE 9600 | |
42 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
43 | ||
e2211743 WD |
44 | #define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" \ |
45 | "\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 $(filesize)\0" | |
46 | ||
e2211743 WD |
47 | #undef CONFIG_BOOTARGS |
48 | #define CONFIG_BOOTCOMMAND \ | |
49 | "bootp; " \ | |
50 | "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ | |
51 | "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ | |
52 | "bootm" | |
53 | ||
54 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
55 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
56 | ||
57 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
58 | ||
59 | ||
60 | /* enable I2C and select the hardware/software driver */ | |
61 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
62 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
63 | /* | |
64 | * Software (bit-bang) I2C driver configuration | |
65 | */ | |
66 | #define PB_SCL 0x00000020 /* PB 26 */ | |
67 | #define PB_SDA 0x00000010 /* PB 27 */ | |
68 | ||
69 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
70 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
71 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
72 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
73 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
74 | else immr->im_cpm.cp_pbdat &= ~PB_SDA | |
75 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ | |
76 | else immr->im_cpm.cp_pbdat &= ~PB_SCL | |
77 | #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ | |
78 | ||
79 | ||
80 | # define CFG_I2C_SPEED 50000 | |
81 | # define CFG_I2C_SLAVE 0xFE | |
82 | # define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C16 */ | |
83 | # define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */ | |
84 | /* mask of address bits that overflow into the "EEPROM chip address" */ | |
85 | #define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07 | |
86 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
87 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */ | |
88 | ||
414eec35 WD |
89 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
90 | ||
91 | #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ | |
92 | CFG_CMD_BEDBUG | \ | |
93 | CFG_CMD_I2C | \ | |
94 | CFG_CMD_EEPROM | \ | |
95 | CFG_CMD_NFS | \ | |
96 | CFG_CMD_SNTP ) | |
e2211743 WD |
97 | |
98 | #define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT | |
99 | ||
100 | /*----------------------------------------------------------------------*/ | |
101 | ||
102 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ | |
103 | #include <cmd_confdefs.h> | |
104 | ||
105 | /*----------------------------------------------------------------------*/ | |
106 | ||
107 | /* | |
108 | * Miscellaneous configurable options | |
109 | */ | |
110 | #define CFG_LONGHELP /* undef to save memory */ | |
111 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
112 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
113 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
114 | #else | |
115 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
116 | #endif | |
117 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
118 | #define CFG_MAXARGS 16 /* max number of command args */ | |
119 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
120 | ||
121 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
122 | #define CFG_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */ | |
123 | ||
124 | #define CFG_LOAD_ADDR 0x00100000 /* default load address */ | |
125 | ||
126 | #define CFG_PIO_MODE 0 /* IDE interface in PIO Mode 0 */ | |
127 | ||
128 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
129 | ||
130 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
131 | ||
132 | /* | |
133 | * Low Level Configuration Settings | |
134 | * (address mappings, register initial values, etc.) | |
135 | * You should know what you are doing if you make changes here. | |
136 | */ | |
137 | /*----------------------------------------------------------------------- | |
138 | * Internal Memory Mapped Register | |
139 | */ | |
140 | #define CFG_IMMR 0xF1000000 /* Non-standard value!! */ | |
141 | ||
142 | /*----------------------------------------------------------------------- | |
143 | * Definitions for initial stack pointer and data area (in DPRAM) | |
144 | */ | |
145 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
146 | #define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ | |
147 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
148 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
149 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
150 | ||
151 | /*----------------------------------------------------------------------- | |
152 | * Start addresses for the final memory configuration | |
153 | * (Set up by the startup code) | |
154 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
155 | */ | |
156 | #define CFG_SDRAM_BASE 0x00000000 | |
157 | #define CFG_FLASH_BASE 0x10000000 | |
158 | #ifdef DEBUG | |
159 | #define CFG_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */ | |
160 | #else | |
161 | #if 0 /* need more space for I2C tests */ | |
162 | #define CFG_MONITOR_LEN (128 << 10) /* Reserve 128 kB for Monitor */ | |
163 | #else | |
164 | #define CFG_MONITOR_LEN (256 << 10) | |
165 | #endif | |
166 | #endif | |
167 | #define CFG_MONITOR_BASE CFG_FLASH_BASE | |
168 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
169 | ||
170 | /* | |
171 | * For booting Linux, the board info and command line data | |
172 | * have to be in the first 8 MB of memory, since this is | |
173 | * the maximum mapped by the Linux kernel during initialization. | |
174 | */ | |
175 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
176 | /*----------------------------------------------------------------------- | |
177 | * FLASH organization | |
178 | */ | |
179 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
180 | #define CFG_MAX_FLASH_SECT 124 /* max number of sectors on one chip */ | |
181 | ||
182 | #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ | |
183 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
184 | ||
185 | #undef CFG_ENV_IS_IN_FLASH | |
186 | #undef CFG_ENV_IS_IN_NVRAM | |
187 | #undef CFG_ENV_IS_IN_NVRAM | |
188 | #undef DEBUG_I2C | |
189 | #define CFG_ENV_IS_IN_EEPROM | |
190 | ||
191 | #ifdef CFG_ENV_IS_IN_NVRAM | |
192 | #define CFG_ENV_ADDR 0x20000000 /* use SRAM */ | |
193 | #define CFG_ENV_SIZE (16<<10) /* use 16 kB */ | |
194 | #endif /* CFG_ENV_IS_IN_NVRAM */ | |
195 | ||
196 | #ifdef CFG_ENV_IS_IN_EEPROM | |
197 | #define CFG_ENV_OFFSET 512 /* Leave 512 bytes free for other data */ | |
198 | #define CFG_ENV_SIZE 1536 /* Use remaining space */ | |
199 | #endif /* CFG_ENV_IS_IN_EEPROM */ | |
200 | ||
201 | /*----------------------------------------------------------------------- | |
202 | * Cache Configuration | |
203 | */ | |
204 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
205 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) | |
206 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
207 | #endif | |
208 | ||
209 | /*----------------------------------------------------------------------- | |
210 | * SYPCR - System Protection Control 11-9 | |
211 | * SYPCR can only be written once after reset! | |
212 | *----------------------------------------------------------------------- | |
213 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
214 | * +0x0004 | |
215 | */ | |
216 | #if defined(CONFIG_WATCHDOG) | |
217 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
218 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
219 | #else | |
220 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
221 | #endif | |
222 | ||
223 | /*----------------------------------------------------------------------- | |
224 | * SIUMCR - SIU Module Configuration 11-6 | |
225 | *----------------------------------------------------------------------- | |
226 | * +0x0000 => 0x80600800 | |
227 | */ | |
228 | #define CFG_SIUMCR (SIUMCR_EARB | SIUMCR_EARP0 | \ | |
229 | SIUMCR_DBGC11 | SIUMCR_MLRC10) | |
230 | ||
231 | /*----------------------------------------------------------------------- | |
8bde7f77 | 232 | * Clock Setting - get clock frequency from Board Revision Register |
e2211743 WD |
233 | *----------------------------------------------------------------------- |
234 | */ | |
3bac3513 WD |
235 | #ifndef __ASSEMBLY__ |
236 | extern unsigned long ip860_get_clk_freq (void); | |
237 | #endif | |
238 | #define CONFIG_8xx_GCLK_FREQ ip860_get_clk_freq() | |
e2211743 WD |
239 | |
240 | /*----------------------------------------------------------------------- | |
241 | * TBSCR - Time Base Status and Control 11-26 | |
242 | *----------------------------------------------------------------------- | |
243 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
244 | * +0x0200 => 0x00C2 | |
245 | */ | |
246 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
247 | ||
248 | /*----------------------------------------------------------------------- | |
249 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
250 | *----------------------------------------------------------------------- | |
251 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
252 | * +0x0240 => 0x0082 | |
253 | */ | |
254 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
255 | ||
256 | /*----------------------------------------------------------------------- | |
257 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
258 | *----------------------------------------------------------------------- | |
259 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
260 | * interrupt status bit, set PLL multiplication factor ! | |
261 | */ | |
262 | /* +0x0286 => was: 0x0000D000 */ | |
263 | #define CFG_PLPRCR \ | |
264 | ( PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | \ | |
265 | /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \ | |
266 | PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \ | |
267 | ) | |
268 | ||
269 | /*----------------------------------------------------------------------- | |
270 | * SCCR - System Clock and reset Control Register 15-27 | |
271 | *----------------------------------------------------------------------- | |
272 | * Set clock output, timebase and RTC source and divider, | |
273 | * power management and some other internal clocks | |
274 | */ | |
275 | #define SCCR_MASK SCCR_EBDF11 | |
276 | #define CFG_SCCR (SCCR_COM00 | SCCR_TBS | \ | |
277 | SCCR_RTDIV | SCCR_RTSEL | \ | |
278 | /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \ | |
279 | SCCR_EBDF00 | SCCR_DFSYNC00 | \ | |
280 | SCCR_DFBRG00 | SCCR_DFNL000 | \ | |
281 | SCCR_DFNH000) | |
282 | ||
283 | /*----------------------------------------------------------------------- | |
284 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
285 | *----------------------------------------------------------------------- | |
286 | */ | |
287 | /* +0x0220 => 0x00C3 */ | |
288 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
289 | ||
290 | ||
291 | /*----------------------------------------------------------------------- | |
292 | * RCCR - RISC Controller Configuration Register 19-4 | |
293 | *----------------------------------------------------------------------- | |
294 | */ | |
295 | /* +0x09C4 => TIMEP=1 */ | |
296 | #define CFG_RCCR 0x0100 | |
297 | ||
298 | /*----------------------------------------------------------------------- | |
299 | * RMDS - RISC Microcode Development Support Control Register | |
300 | *----------------------------------------------------------------------- | |
301 | */ | |
302 | #define CFG_RMDS 0 | |
303 | ||
304 | /*----------------------------------------------------------------------- | |
305 | * DER - Debug Event Register | |
306 | *----------------------------------------------------------------------- | |
307 | * | |
308 | */ | |
e2211743 WD |
309 | #define CFG_DER 0 |
310 | ||
311 | /* | |
312 | * Init Memory Controller: | |
313 | */ | |
314 | ||
315 | /* | |
316 | * MAMR settings for SDRAM - 16-14 | |
317 | * => 0xC3804114 | |
318 | */ | |
319 | ||
320 | /* periodic timer for refresh */ | |
321 | #define CFG_MAMR_PTA 0xC3 | |
322 | ||
323 | #define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
324 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
325 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
326 | /* | |
327 | * BR1 and OR1 (FLASH) | |
328 | */ | |
329 | #define FLASH_BASE 0x10000000 /* FLASH bank #0 */ | |
330 | ||
331 | /* used to re-map FLASH | |
332 | * restrict access enough to keep SRAM working (if any) | |
333 | * but not too much to meddle with FLASH accesses | |
334 | */ | |
335 | /* allow for max 8 MB of Flash */ | |
336 | #define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */ | |
337 | #define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */ | |
338 | ||
339 | #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK) | |
340 | ||
341 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
342 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
343 | /* 16 bit, bank valid */ | |
344 | #define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V ) | |
345 | ||
346 | #define CFG_OR1_PRELIM CFG_OR0_PRELIM | |
347 | #define CFG_BR1_PRELIM CFG_BR0_PRELIM | |
348 | ||
349 | /* | |
350 | * BR2/OR2 - SDRAM | |
351 | */ | |
352 | #define SDRAM_BASE 0x00000000 /* SDRAM bank */ | |
353 | #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */ | |
354 | #define SDRAM_TIMING 0x00000A00 /* SDRAM-Timing */ | |
355 | ||
356 | #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */ | |
357 | ||
358 | #define CFG_OR2 (SDRAM_PRELIM_OR_AM | SDRAM_TIMING ) | |
359 | #define CFG_BR2 ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V ) | |
360 | ||
361 | /* | |
362 | * BR3/OR3 - SRAM (16 bit) | |
363 | */ | |
364 | #define SRAM_BASE 0x20000000 | |
365 | #define CFG_OR3 0xFFF00130 /* BI/SCY = 5/TRLX (internal) */ | |
366 | #define CFG_BR3 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) | |
367 | #define SRAM_SIZE (1 + (~(CFG_OR3 & BR_BA_MSK))) | |
368 | #define CFG_OR3_PRELIM CFG_OR3 /* Make sure to map early */ | |
369 | #define CFG_BR3_PRELIM CFG_BR3 /* in case it's used for ENV */ | |
370 | ||
371 | /* | |
372 | * BR4/OR4 - Board Control & Status (8 bit) | |
373 | */ | |
374 | #define BCSR_BASE 0xFC000000 | |
375 | #define CFG_OR4 0xFFFF0120 /* BI (internal) */ | |
376 | #define CFG_BR4 ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) | |
377 | ||
378 | /* | |
379 | * BR5/OR5 - IP Slot A/B (16 bit) | |
380 | */ | |
381 | #define IP_SLOT_BASE 0x40000000 | |
382 | #define CFG_OR5 0xFE00010C /* SETA/TRLX/BI/ SCY=0 (external) */ | |
383 | #define CFG_BR5 ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) | |
384 | ||
385 | /* | |
386 | * BR6/OR6 - VME STD (16 bit) | |
387 | */ | |
388 | #define VME_STD_BASE 0xFE000000 | |
389 | #define CFG_OR6 0xFF00010C /* SETA/TRLX/BI/SCY=0 (external) */ | |
390 | #define CFG_BR6 ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) | |
391 | ||
392 | /* | |
393 | * BR7/OR7 - SHORT I/O + RTC + IACK (16 bit) | |
394 | */ | |
395 | #define VME_SHORT_BASE 0xFF000000 | |
396 | #define CFG_OR7 0xFF00010C /* SETA/TRLX/BI/ SCY=0 (external) */ | |
397 | #define CFG_BR7 ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V) | |
398 | ||
399 | /*----------------------------------------------------------------------- | |
400 | * Board Control and Status Region: | |
401 | *----------------------------------------------------------------------- | |
402 | */ | |
403 | #ifndef __ASSEMBLY__ | |
404 | typedef struct ip860_bcsr_s { | |
405 | unsigned char shmem_addr; /* +00 shared memory address register */ | |
406 | unsigned char reserved0; | |
407 | unsigned char mbox_addr; /* +02 mailbox address register */ | |
408 | unsigned char reserved1; | |
409 | unsigned char vme_int_mask; /* +04 VME Bus interrupt mask register */ | |
410 | unsigned char reserved2; | |
411 | unsigned char vme_int_pend; /* +06 VME interrupt pending register */ | |
412 | unsigned char reserved3; | |
413 | unsigned char bd_int_mask; /* +08 board interrupt mask register */ | |
414 | unsigned char reserved4; | |
415 | unsigned char bd_int_pend; /* +0A board interrupt pending register */ | |
416 | unsigned char reserved5; | |
417 | unsigned char bd_ctrl; /* +0C board control register */ | |
418 | unsigned char reserved6; | |
419 | unsigned char bd_status; /* +0E board status register */ | |
420 | unsigned char reserved7; | |
421 | unsigned char vme_irq; /* +10 VME interrupt request register */ | |
422 | unsigned char reserved8; | |
423 | unsigned char vme_ivec; /* +12 VME interrupt vector register */ | |
424 | unsigned char reserved9; | |
425 | unsigned char cli_mbox; /* +14 clear mailbox irq */ | |
426 | unsigned char reservedA; | |
427 | unsigned char rtc; /* +16 RTC control register */ | |
428 | unsigned char reservedB; | |
429 | unsigned char mbox_data; /* +18 mailbox read/write register */ | |
430 | unsigned char reservedC; | |
431 | unsigned char wd_trigger; /* +1A Watchdog trigger register */ | |
432 | unsigned char reservedD; | |
433 | unsigned char rmw_req; /* +1C RMW request register */ | |
3bac3513 WD |
434 | unsigned char reservedE; |
435 | unsigned char bd_rev; /* +1E Board Revision register */ | |
e2211743 WD |
436 | } ip860_bcsr_t; |
437 | #endif /* __ASSEMBLY__ */ | |
438 | ||
439 | /*----------------------------------------------------------------------- | |
440 | * Board Control Register: bd_ctrl (Offset 0x0C) | |
441 | *----------------------------------------------------------------------- | |
442 | */ | |
443 | #define BD_CTRL_IPLSE 0x80 /* IP Slot Long Select Enable */ | |
444 | #define BD_CTRL_WDOGE 0x40 /* Watchdog Enable */ | |
445 | #define BD_CTRL_FLWE 0x20 /* Flash Write Enable */ | |
446 | #define BD_CTRL_RWDN 0x10 /* VMEBus Requester Release When Done Enable */ | |
447 | ||
448 | /*----------------------------------------------------------------------- | |
449 | * | |
450 | *----------------------------------------------------------------------- | |
451 | * | |
452 | */ | |
453 | ||
454 | /* | |
455 | * Internal Definitions | |
456 | * | |
457 | * Boot Flags | |
458 | */ | |
459 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
460 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
461 | ||
462 | #endif /* __CONFIG_H */ |