[people/ms/u-boot.git] / include / configs / IVML24.h

/*
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC860		1	/* This is a MPC860 CPU		*/
#define CONFIG_IVML24		1	/* ...on a IVML24 board		*/

#define	CONFIG_SYS_TEXT_BASE	0xFF000000

#if defined (CONFIG_IVML24_16M)
# define CONFIG_IDENT_STRING     " IVML24"
#elif defined (CONFIG_IVML24_32M)
# define CONFIG_IDENT_STRING     " IVML24_128"
#elif defined (CONFIG_IVML24_64M)
# define CONFIG_IDENT_STRING     " IVML24_256"
#endif

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */
#define CONFIG_8xx_GCLK_FREQ    50331648

#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/

#define	CONFIG_SHOW_BOOT_PROGRESS 1	/* Show boot progress on LEDs	*/

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif
#define CONFIG_BOOTCOMMAND	"bootp" /* autoboot command		*/

#define CONFIG_BOOTARGS		"root=/dev/nfs rw "			\
				"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx "	\
				"nfsaddrs=10.0.0.99:10.0.0.2"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_IDE


#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x00100000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x00F00000	/* 1 ... 15MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x00100000	/* default load address	*/

#define	CONFIG_SYS_PIO_MODE		0	/* IDE interface in PIO Mode 0	*/

#define CONFIG_SYS_PB_12V_ENABLE	0x00002000		/* PB 18	*/
#define CONFIG_SYS_PB_ILOCK_SWITCH	0x00004000		/* PB 17	*/
#define CONFIG_SYS_PB_SDRAM_CLKE	0x00008000		/* PB 16	*/
#define CONFIG_SYS_PB_ETH_POWERDOWN	0x00010000		/* PB 15	*/
#define CONFIG_SYS_PB_IDE_MOTOR	0x00020000		/* PB 14	*/

#define CONFIG_SYS_PC_ETH_RESET	((ushort)0x0010)	/* PC 11	*/
#define CONFIG_SYS_PC_IDE_RESET	((ushort)0x0020)	/* PC 10	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000 /* was: 0xFF000000 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR

#if defined (CONFIG_IVML24_16M)
# define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#elif defined (CONFIG_IVML24_32M)
# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
#elif defined (CONFIG_IVML24_64M)
# define	CONFIG_SYS_INIT_RAM_SIZE	0x3000	/* Size of used area in DPRAM	*/
#endif

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0xFF000000
#ifdef	DEBUG
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1
#define	CONFIG_ENV_OFFSET		0x7A000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x2000	/* Total Size of Environment Sector	*/
/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)

# if defined (CONFIG_IVML24_16M)
#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
# elif defined (CONFIG_IVML24_32M)
#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWP)
# elif defined (CONFIG_IVML24_64M)
#  define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWP)
# endif

#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
/* EARB, DBGC and DBPC are initialised by the HCW */
/* => 0x000000C0 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_BSC | SIUMCR_GB5E)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit, set PLL multiplication factor !
 */
/* 0x00B0C0C0 */
#define CONFIG_SYS_PLPRCR							\
		(	(11 << PLPRCR_MF_SHIFT) |			\
			PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/	\
			/*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |		\
			PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/	\
		)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
/* 0x01800014 */
#define CONFIG_SYS_SCCR	(SCCR_COM01	| /*SCCR_TBS|*/		\
			 SCCR_RTDIV	|   SCCR_RTSEL	  |	\
			 /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/	\
			 SCCR_EBDF00	|   SCCR_DFSYNC00 |	\
			 SCCR_DFBRG00	|   SCCR_DFNL000  |	\
			 SCCR_DFNH000	|   SCCR_DFLCD101 |	\
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
/* 0x00C3 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)


/*-----------------------------------------------------------------------
 * RCCR - RISC Controller Configuration Register		19-4
 *-----------------------------------------------------------------------
 */
/* TIMEP=2 */
#define CONFIG_SYS_RCCR 0x0200

/*-----------------------------------------------------------------------
 * RMDS - RISC Microcode Development Support Control Register
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RMDS 0

/*-----------------------------------------------------------------------
 *
 * Interrupt Levels
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_CPM_INTERRUPT	13	/* SIU_LEVEL6	*/

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_IDE_PREINIT	1	/* Use preinit IDE hook */
#define CONFIG_IDE_INIT_POSTRESET	1	/* Use postreset IDE hook */
#define CONFIG_IDE_8xx_DIRECT	1	/* PCMCIA interface required	*/
#define CONFIG_IDE_RESET	1	/* reset for ide supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* The IVML24 has only 1 IDE bus*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/*    ... and only 1 IDE device	*/

#define CONFIG_SYS_ATA_BASE_ADDR	0xFE100000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
#undef	CONFIG_SYS_ATA_IDE1_OFFSET		/* only one IDE bus available	*/

#define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_REG_OFFSET	0x0080	/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100	/* Offset for alternate registers	*/

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0 and OR0 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0xFF000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
/* EPROMs are 512kb */
#define CONFIG_SYS_REMAP_OR_AM		0xFFF80000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xFFF80000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_SCY_5_CLK | OR_EHTR)

#define CONFIG_SYS_OR0_REMAP	( CONFIG_SYS_REMAP_OR_AM | OR_ACS_DIV4 | OR_BI | \
				CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV4 | OR_BI | \
				CONFIG_SYS_OR_TIMING_FLASH)
/* 16 bit, bank valid */
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )

/*
 * BR1/OR1 - ELIC SACCO bank  @ 0xFE000000
 *
 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 */
#define ELIC_SACCO_BASE		0xFE000000
#define ELIC_SACCO_OR_AM	0xFFFF8000
#define ELIC_SACCO_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)

#define CONFIG_SYS_OR1	(ELIC_SACCO_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
			ELIC_SACCO_TIMING)
#define CONFIG_SYS_BR1	((ELIC_SACCO_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR2/OR2 - ELIC EPIC bank   @ 0xFE008000
 *
 * AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
 */
#define ELIC_EPIC_BASE		0xFE008000
#define ELIC_EPIC_OR_AM		0xFFFF8000
#define ELIC_EPIC_TIMING	(OR_SCY_2_CLK | OR_TRLX | OR_EHTR)

#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM | OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \
			ELIC_EPIC_TIMING)
#define CONFIG_SYS_BR2	((ELIC_EPIC_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR3/OR3: SDRAM
 *
 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 */
#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank */
#define SDRAM_PRELIM_OR_AM	0xF8000000	/* map max. 128 MB */
#define SDRAM_TIMING		OR_SCY_0_CLK	/* SDRAM-Timing */

#define SDRAM_MAX_SIZE		0x04000000	/* max 64 MB SDRAM */

#define CONFIG_SYS_OR3_PRELIM	(SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
#define CONFIG_SYS_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )

/*
 * BR4/OR4 - HDLC Address
 *
 *  AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
 */
#define HDLC_ADDR_BASE		0xFE108000	/* HDLC Address area */
#define HDLC_ADDR_OR_AM		0xFFFF8000
#define HDLC_ADDR_TIMING	OR_SCY_1_CLK

#define CONFIG_SYS_OR4	(HDLC_ADDR_OR_AM | OR_BI | HDLC_ADDR_TIMING)
#define CONFIG_SYS_BR4	((HDLC_ADDR_BASE & BR_BA_MSK) | BR_PS_8 | BR_WP | BR_V )

/*
 * BR5/OR5: SHARC ADSP-2165L
 *
 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 */
#define SHARC_BASE		0xFE400000
#define SHARC_OR_AM		0xFFC00000
#define SHARC_TIMING		OR_SCY_0_CLK

#define CONFIG_SYS_OR5	(SHARC_OR_AM | OR_ACS_DIV2 | OR_BI | SHARC_TIMING )
#define CONFIG_SYS_BR5	((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CONFIG_SYS_MBMR_PTB	204

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/

#if defined (CONFIG_IVML24_16M)
# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
#elif defined (CONFIG_IVML24_32M)
# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
#elif defined (CONFIG_IVML24_64M)
# define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV8		/* setting for 1 bank	*/
#endif


/*
 * MBMR settings for SDRAM
 */

#if defined (CONFIG_IVML24_16M)
 /* 8 column SDRAM */
# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
			 MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 |	\
			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
#elif defined (CONFIG_IVML24_32M)
/* 128 MBit SDRAM */
# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
#elif defined (CONFIG_IVML24_64M)
/* 128 MBit SDRAM */
# define CONFIG_SYS_MBMR_8COL	((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT)  | \
			 MBMR_AMB_TYPE_1 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A10 |	\
			 MBMR_RLFB_1X	 | MBMR_WLFB_1X	   | MBMR_TLFB_4X)
#endif
#endif	/* __CONFIG_H */
Commit	Line	Data
0f8c9768 WD	1	/*
	2	* (C) Copyright 2001
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
0f8c9768 WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC860 1 /* This is a MPC860 CPU */
	21	#define CONFIG_IVML24 1 /* ...on a IVML24 board */
	22
2ae18241 WD	23	#define CONFIG_SYS_TEXT_BASE 0xFF000000
2ae18241 WD	24
0f8c9768 WD	25	#if defined (CONFIG_IVML24_16M)
	26	# define CONFIG_IDENT_STRING " IVML24"
	27	#elif defined (CONFIG_IVML24_32M)
	28	# define CONFIG_IDENT_STRING " IVML24_128"
	29	#elif defined (CONFIG_IVML24_64M)
	30	# define CONFIG_IDENT_STRING " IVML24_256"
	31	#endif
	32
	33	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	34	#undef CONFIG_8xx_CONS_SMC2
	35	#undef CONFIG_8xx_CONS_NONE
	36	#define CONFIG_BAUDRATE 115200
	37
	38	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	39	#define CONFIG_8xx_GCLK_FREQ 50331648
	40
004eca0c PT	41	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
004eca0c PT	42
0f8c9768 WD	43	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
	44
	45	#if 0
	46	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	47	#else
	48	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	49	#endif
	50	#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
	51
	52	#define CONFIG_BOOTARGS "root=/dev/nfs rw " \
	53	"nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
	54	"nfsaddrs=10.0.0.99:10.0.0.2"
	55
	56	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	57	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
0f8c9768 WD	58
	59	#undef CONFIG_WATCHDOG /* watchdog disabled */
	60
	61	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	62
348f258f JL	63
	64	/*
	65	* Command line configuration.
	66	*/
	67	#include <config_cmd_default.h>
	68
	69	#define CONFIG_CMD_IDE
	70
	71
0f8c9768 WD	72	#define CONFIG_MAC_PARTITION
	73	#define CONFIG_DOS_PARTITION
	74
7be044e4 JL	75	/*
	76	* BOOTP options
	77	*/
	78	#define CONFIG_BOOTP_SUBNETMASK
	79	#define CONFIG_BOOTP_HOSTNAME
	80	#define CONFIG_BOOTP_BOOTPATH
	81	#define CONFIG_BOOTP_BOOTFILESIZE
	82
0f8c9768	83
0f8c9768 WD	84	/*
	85	* Miscellaneous configurable options
	86	*/
6d0f6bcf	87	#define CONFIG_SYS_LONGHELP /* undef to save memory */
348f258f	88	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	89	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
0f8c9768	90	#else
6d0f6bcf	91	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
0f8c9768	92	#endif
6d0f6bcf JCPV	93	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	94	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	95	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
0f8c9768	96
6d0f6bcf JCPV	97	#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
6d0f6bcf JCPV	98	#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
0f8c9768	99
6d0f6bcf	100	#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
0f8c9768	101
6d0f6bcf	102	#define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
0f8c9768	103
6d0f6bcf JCPV	104	#define CONFIG_SYS_PB_12V_ENABLE 0x00002000 /* PB 18 */
	105	#define CONFIG_SYS_PB_ILOCK_SWITCH 0x00004000 /* PB 17 */
	106	#define CONFIG_SYS_PB_SDRAM_CLKE 0x00008000 /* PB 16 */
	107	#define CONFIG_SYS_PB_ETH_POWERDOWN 0x00010000 /* PB 15 */
	108	#define CONFIG_SYS_PB_IDE_MOTOR 0x00020000 /* PB 14 */
0f8c9768	109
6d0f6bcf JCPV	110	#define CONFIG_SYS_PC_ETH_RESET ((ushort)0x0010) /* PC 11 */
6d0f6bcf JCPV	111	#define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0020) /* PC 10 */
0f8c9768	112
0f8c9768 WD	113	/*
	114	* Low Level Configuration Settings
	115	* (address mappings, register initial values, etc.)
	116	* You should know what you are doing if you make changes here.
	117	*/
	118	/*-----------------------------------------------------------------------
	119	* Internal Memory Mapped Register
	120	*/
6d0f6bcf	121	#define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
0f8c9768 WD	122
	123	/*-----------------------------------------------------------------------
	124	* Definitions for initial stack pointer and data area (in DPRAM)
	125	*/
6d0f6bcf	126	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
0f8c9768 WD	127
0f8c9768 WD	128	#if defined (CONFIG_IVML24_16M)
553f0982	129	# define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
0f8c9768	130	#elif defined (CONFIG_IVML24_32M)
553f0982	131	# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
0f8c9768	132	#elif defined (CONFIG_IVML24_64M)
553f0982	133	# define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
0f8c9768 WD	134	#endif
0f8c9768 WD	135
25ddd1fb	136	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	137	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
0f8c9768 WD	138
	139	/*-----------------------------------------------------------------------
	140	* Start addresses for the final memory configuration
	141	* (Set up by the startup code)
6d0f6bcf	142	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
0f8c9768	143	*/
6d0f6bcf JCPV	144	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	145	#define CONFIG_SYS_FLASH_BASE 0xFF000000
0f8c9768	146	#ifdef DEBUG
6d0f6bcf	147	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
0f8c9768	148	#else
6d0f6bcf	149	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
0f8c9768	150	#endif
6d0f6bcf JCPV	151	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	152	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
0f8c9768 WD	153
	154	/*
	155	* For booting Linux, the board info and command line data
	156	* have to be in the first 8 MB of memory, since this is
	157	* the maximum mapped by the Linux kernel during initialization.
	158	*/
6d0f6bcf	159	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
0f8c9768 WD	160	/*-----------------------------------------------------------------------
	161	* FLASH organization
	162	*/
6d0f6bcf JCPV	163	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	164	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
0f8c9768	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	167	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
0f8c9768	168
5a1aceb0	169	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 JCPV	170	#define CONFIG_ENV_OFFSET 0x7A000 /* Offset of Environment Sector */
0e8d1586 JCPV	171	#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
0f8c9768 WD	172	/*-----------------------------------------------------------------------
	173	* Cache Configuration
	174	*/
6d0f6bcf	175	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
348f258f	176	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	177	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
0f8c9768 WD	178	#endif
	179
	180	/*-----------------------------------------------------------------------
	181	* SYPCR - System Protection Control 11-9
	182	* SYPCR can only be written once after reset!
	183	*-----------------------------------------------------------------------
	184	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	185	*/
	186	#if defined(CONFIG_WATCHDOG)
	187
	188	# if defined (CONFIG_IVML24_16M)
6d0f6bcf	189	# define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
53677ef1	190	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
0f8c9768	191	# elif defined (CONFIG_IVML24_32M)
6d0f6bcf	192	# define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0f8c9768 WD	193	SYPCR_SWE \| SYPCR_SWP)
0f8c9768 WD	194	# elif defined (CONFIG_IVML24_64M)
6d0f6bcf	195	# define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
0f8c9768 WD	196	SYPCR_SWE \| SYPCR_SWP)
	197	# endif
	198
	199	#else
6d0f6bcf	200	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
0f8c9768 WD	201	#endif
	202
	203	/*-----------------------------------------------------------------------
	204	* SIUMCR - SIU Module Configuration 11-6
	205	*-----------------------------------------------------------------------
	206	* PCMCIA config., multi-function pin tri-state
	207	*/
	208	/* EARB, DBGC and DBPC are initialised by the HCW */
	209	/* => 0x000000C0 */
6d0f6bcf	210	#define CONFIG_SYS_SIUMCR (SIUMCR_BSC \| SIUMCR_GB5E)
0f8c9768 WD	211
	212	/*-----------------------------------------------------------------------
	213	* TBSCR - Time Base Status and Control 11-26
	214	*-----------------------------------------------------------------------
	215	* Clear Reference Interrupt Status, Timebase freezing enabled
	216	*/
6d0f6bcf	217	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
0f8c9768 WD	218
	219	/*-----------------------------------------------------------------------
	220	* PISCR - Periodic Interrupt Status and Control 11-31
	221	*-----------------------------------------------------------------------
	222	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	223	*/
6d0f6bcf	224	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
0f8c9768 WD	225
	226	/*-----------------------------------------------------------------------
	227	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	228	*-----------------------------------------------------------------------
	229	* Reset PLL lock status sticky bit, timer expired status bit and timer
	230	* interrupt status bit, set PLL multiplication factor !
	231	*/
	232	/* 0x00B0C0C0 */
6d0f6bcf	233	#define CONFIG_SYS_PLPRCR \
0f8c9768 WD	234	( (11 << PLPRCR_MF_SHIFT) \| \
	235	PLPRCR_SPLSS \| PLPRCR_TEXPS \| /PLPRCR_TMIST\|/ \
	236	/PLPRCR_CSRC\|/ PLPRCR_LPM_NORMAL \| \
	237	PLPRCR_CSR \| PLPRCR_LOLRE /\|PLPRCR_FIOPD/ \
	238	)
	239
	240	/*-----------------------------------------------------------------------
	241	* SCCR - System Clock and reset Control Register 15-27
	242	*-----------------------------------------------------------------------
	243	* Set clock output, timebase and RTC source and divider,
	244	* power management and some other internal clocks
	245	*/
	246	#define SCCR_MASK SCCR_EBDF11
	247	/* 0x01800014 */
6d0f6bcf	248	#define CONFIG_SYS_SCCR (SCCR_COM01 \| /SCCR_TBS\|/ \
0f8c9768	249	SCCR_RTDIV \| SCCR_RTSEL \| \
53677ef1	250	/SCCR_CRQEN\|/ /SCCR_PRQEN\|/ \
0f8c9768 WD	251	SCCR_EBDF00 \| SCCR_DFSYNC00 \| \
	252	SCCR_DFBRG00 \| SCCR_DFNL000 \| \
	253	SCCR_DFNH000 \| SCCR_DFLCD101 \| \
	254	SCCR_DFALCD00)
	255
	256	/*-----------------------------------------------------------------------
	257	* RTCSC - Real-Time Clock Status and Control Register 11-27
	258	*-----------------------------------------------------------------------
	259	*/
	260	/* 0x00C3 */
6d0f6bcf	261	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
0f8c9768 WD	262
	263
	264	/*-----------------------------------------------------------------------
	265	* RCCR - RISC Controller Configuration Register 19-4
	266	*-----------------------------------------------------------------------
	267	*/
	268	/* TIMEP=2 */
6d0f6bcf	269	#define CONFIG_SYS_RCCR 0x0200
0f8c9768 WD	270
	271	/*-----------------------------------------------------------------------
	272	* RMDS - RISC Microcode Development Support Control Register
	273	*-----------------------------------------------------------------------
	274	*/
6d0f6bcf	275	#define CONFIG_SYS_RMDS 0
0f8c9768 WD	276
	277	/*-----------------------------------------------------------------------
	278	*
	279	* Interrupt Levels
	280	*-----------------------------------------------------------------------
	281	*/
6d0f6bcf	282	#define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
0f8c9768 WD	283
	284	/*-----------------------------------------------------------------------
	285	* PCMCIA stuff
	286	*-----------------------------------------------------------------------
	287	*
	288	*/
6d0f6bcf JCPV	289	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	290	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	291	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	292	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	293	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	294	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	295	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	296	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
0f8c9768 WD	297
	298	/*-----------------------------------------------------------------------
	299	* IDE/ATA stuff
	300	*-----------------------------------------------------------------------
	301	*/
8d1165e1 PH	302	#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
8d1165e1 PH	303	#define CONFIG_IDE_INIT_POSTRESET 1 /* Use postreset IDE hook */
0f8c9768 WD	304	#define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
	305	#define CONFIG_IDE_RESET 1 /* reset for ide supported */
	306
6d0f6bcf JCPV	307	#define CONFIG_SYS_IDE_MAXBUS 1 /* The IVML24 has only 1 IDE bus*/
6d0f6bcf JCPV	308	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* ... and only 1 IDE device */
0f8c9768	309
6d0f6bcf JCPV	310	#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
	311	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	312	#undef CONFIG_SYS_ATA_IDE1_OFFSET /* only one IDE bus available */
0f8c9768	313
6d0f6bcf JCPV	314	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
	315	#define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
	316	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
0f8c9768 WD	317
	318	/*-----------------------------------------------------------------------
	319	*
	320	*-----------------------------------------------------------------------
	321	*
	322	*/
6d0f6bcf	323	#define CONFIG_SYS_DER 0
0f8c9768 WD	324
	325	/*
	326	* Init Memory Controller:
	327	*
	328	* BR0 and OR0 (FLASH)
	329	*/
	330
	331	#define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
	332
	333	/* used to re-map FLASH both when starting from SRAM or FLASH:
	334	* restrict access enough to keep SRAM working (if any)
	335	* but not too much to meddle with FLASH accesses
	336	*/
	337	/* EPROMs are 512kb */
6d0f6bcf JCPV	338	#define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
6d0f6bcf JCPV	339	#define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
0f8c9768 WD	340
0f8c9768 WD	341	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	342	#define CONFIG_SYS_OR_TIMING_FLASH (OR_SCY_5_CLK \| OR_EHTR)
0f8c9768	343
6d0f6bcf JCPV	344	#define CONFIG_SYS_OR0_REMAP ( CONFIG_SYS_REMAP_OR_AM \| OR_ACS_DIV4 \| OR_BI \| \
	345	CONFIG_SYS_OR_TIMING_FLASH)
	346	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| OR_ACS_DIV4 \| OR_BI \| \
	347	CONFIG_SYS_OR_TIMING_FLASH)
0f8c9768	348	/* 16 bit, bank valid */
6d0f6bcf	349	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
0f8c9768 WD	350
	351	/*
	352	* BR1/OR1 - ELIC SACCO bank @ 0xFE000000
	353	*
	354	* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
	355	*/
	356	#define ELIC_SACCO_BASE 0xFE000000
	357	#define ELIC_SACCO_OR_AM 0xFFFF8000
	358	#define ELIC_SACCO_TIMING (OR_SCY_2_CLK \| OR_TRLX \| OR_EHTR)
	359
6d0f6bcf	360	#define CONFIG_SYS_OR1 (ELIC_SACCO_OR_AM \| OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| \
0f8c9768	361	ELIC_SACCO_TIMING)
6d0f6bcf	362	#define CONFIG_SYS_BR1 ((ELIC_SACCO_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
0f8c9768 WD	363
	364	/*
	365	* BR2/OR2 - ELIC EPIC bank @ 0xFE008000
	366	*
	367	* AM=0xFFFF8 ATM=0 CSNT/SAM=1 ACS/G5LA/G5LS=3 BIH=1 SCY=2 SETA=0 TRLX=1 EHTR=1
	368	*/
	369	#define ELIC_EPIC_BASE 0xFE008000
	370	#define ELIC_EPIC_OR_AM 0xFFFF8000
	371	#define ELIC_EPIC_TIMING (OR_SCY_2_CLK \| OR_TRLX \| OR_EHTR)
	372
6d0f6bcf	373	#define CONFIG_SYS_OR2 (ELIC_EPIC_OR_AM \| OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| \
0f8c9768	374	ELIC_EPIC_TIMING)
6d0f6bcf	375	#define CONFIG_SYS_BR2 ((ELIC_EPIC_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V )
0f8c9768 WD	376
	377	/*
	378	* BR3/OR3: SDRAM
	379	*
	380	* Multiplexed addresses, GPL5 output to GPL5_A (don't care)
	381	*/
	382	#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
	383	#define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
	384	#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
	385
	386	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
	387
6d0f6bcf JCPV	388	#define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM \| OR_CSNT_SAM \| OR_G5LS \| SDRAM_TIMING )
6d0f6bcf JCPV	389	#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMB \| BR_V )
0f8c9768 WD	390
	391	/*
	392	* BR4/OR4 - HDLC Address
	393	*
	394	* AM=0xFFFF8 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=0 BIH=1 SCY=1 SETA=0 TRLX=0 EHTR=0
	395	*/
	396	#define HDLC_ADDR_BASE 0xFE108000 /* HDLC Address area */
	397	#define HDLC_ADDR_OR_AM 0xFFFF8000
	398	#define HDLC_ADDR_TIMING OR_SCY_1_CLK
	399
6d0f6bcf JCPV	400	#define CONFIG_SYS_OR4 (HDLC_ADDR_OR_AM \| OR_BI \| HDLC_ADDR_TIMING)
6d0f6bcf JCPV	401	#define CONFIG_SYS_BR4 ((HDLC_ADDR_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_WP \| BR_V )
0f8c9768 WD	402
	403	/*
	404	* BR5/OR5: SHARC ADSP-2165L
	405	*
	406	* AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
	407	*/
	408	#define SHARC_BASE 0xFE400000
	409	#define SHARC_OR_AM 0xFFC00000
	410	#define SHARC_TIMING OR_SCY_0_CLK
	411
6d0f6bcf JCPV	412	#define CONFIG_SYS_OR5 (SHARC_OR_AM \| OR_ACS_DIV2 \| OR_BI \| SHARC_TIMING )
6d0f6bcf JCPV	413	#define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) \| BR_PS_32 \| BR_MS_UPMA \| BR_V )
0f8c9768 WD	414
	415	/*
	416	* Memory Periodic Timer Prescaler
	417	*/
	418
	419	/* periodic timer for refresh */
6d0f6bcf	420	#define CONFIG_SYS_MBMR_PTB 204
0f8c9768 WD	421
0f8c9768 WD	422	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	423	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	424	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
0f8c9768 WD	425
0f8c9768 WD	426	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf	427	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
0f8c9768 WD	428
0f8c9768 WD	429	#if defined (CONFIG_IVML24_16M)
6d0f6bcf	430	# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
0f8c9768	431	#elif defined (CONFIG_IVML24_32M)
6d0f6bcf	432	# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
0f8c9768	433	#elif defined (CONFIG_IVML24_64M)
6d0f6bcf	434	# define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV8 /* setting for 1 bank */
0f8c9768 WD	435	#endif
	436
	437
	438	/*
	439	* MBMR settings for SDRAM
	440	*/
	441
	442	#if defined (CONFIG_IVML24_16M)
	443	/* 8 column SDRAM */
6d0f6bcf	444	# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) \| \
53677ef1 WD	445	MBMR_AMB_TYPE_0 \| MBMR_DSB_1_CYCL \| MBMR_G0CLB_A11 \| \
53677ef1 WD	446	MBMR_RLFB_1X \| MBMR_WLFB_1X \| MBMR_TLFB_4X)
0f8c9768 WD	447	#elif defined (CONFIG_IVML24_32M)
0f8c9768 WD	448	/* 128 MBit SDRAM */
6d0f6bcf	449	# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) \| \
2535d602 WD	450	MBMR_AMB_TYPE_1 \| MBMR_DSB_1_CYCL \| MBMR_G0CLB_A10 \| \
2535d602 WD	451	MBMR_RLFB_1X \| MBMR_WLFB_1X \| MBMR_TLFB_4X)
0f8c9768 WD	452	#elif defined (CONFIG_IVML24_64M)
0f8c9768 WD	453	/* 128 MBit SDRAM */
6d0f6bcf	454	# define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) \| \
2535d602 WD	455	MBMR_AMB_TYPE_1 \| MBMR_DSB_1_CYCL \| MBMR_G0CLB_A10 \| \
2535d602 WD	456	MBMR_RLFB_1X \| MBMR_WLFB_1X \| MBMR_TLFB_4X)
0f8c9768	457	#endif
0f8c9768	458	#endif /* __CONFIG_H */