[people/ms/u-boot.git] / include / configs / M52277EVB.h

/*
 * Configuation settings for the Freescale MCF52277 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M52277EVB_H
#define _M52277EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF5227x		/* define processor family */
#define CONFIG_M52277		/* define processor type */
#define CONFIG_M52277EVB	/* M52277EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE			115200

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#define CONFIG_CMD_REGINFO
#undef CONFIG_CMD_USB
#undef CONFIG_CMD_BMP
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF

#define CONFIG_HOSTNAME			M52277EVB
#define CONFIG_SYS_UBOOT_END		0x3FFFF
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=loadb ${loadaddr} ${baudrate}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	"updsbf=run loadsbf; run progsbf\0"	\
	"loadsbf=loadb ${loadaddr} ${baudrate};"	\
	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0"	\
	"progsbf=sf probe 0:2 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	""
#endif

#define CONFIG_BOOTDELAY		3	/* autoboot after 3 seconds */
/* LCD */
#ifdef CONFIG_CMD_BMP
#define CONFIG_LCD
#define CONFIG_SPLASH_SCREEN
#define CONFIG_LCD_LOGO
#define CONFIG_SHARP_LQ035Q7DH06
#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_SYS_USB_EHCI_REGS_BASE	0xFC0B0000
#define CONFIG_SYS_USB_EHCI_CPU_INIT
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SYS_DSPI_CS2
#	define CONFIG_SPI_FLASH
#	define CONFIG_SPI_FLASH_STMICRO

#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_SYS_INPUT_CLKSRC	16000000

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_PROMPT	"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE	(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR	(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_HZ		1000

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 32)
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		64	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x43711630
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x81810000
#define CONFIG_SYS_SDRAM_MODE		0x00CD0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x00

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_IS_IN_SPI_FLASH
#	define CONFIG_ENV_SPI_CS	2
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#endif
#define CONFIG_ENV_OVERWRITE		1

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_OFFSET	0x30000
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_SPANSION_BOOT
#	define CONFIG_SYS_FLASH_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE	CONFIG_SYS_CS0_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x1000
#	define CONFIG_ENV_SECT_SIZE	0x8000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_FLASH_SPANSION_S29WS_N	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x40000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x40000)
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

#ifdef CONFIG_CF_SBF
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#else
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00001FA0
#endif

#endif				/* _M52277EVB_H */
Commit	Line	Data
1552af70 TL	1	/*
	2	* Configuation settings for the Freescale MCF52277 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef _M52277EVB_H
	31	#define _M52277EVB_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_MCF5227x /* define processor family */
	38	#define CONFIG_M52277 /* define processor type */
	39	#define CONFIG_M52277EVB /* M52277EVB board */
	40
1552af70	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
a21d0c2c	43	#define CONFIG_BAUDRATE 115200
1552af70 TL	44
	45	#undef CONFIG_WATCHDOG
	46
	47	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	48
	49	/*
	50	* BOOTP options
	51	*/
	52	#define CONFIG_BOOTP_BOOTFILESIZE
	53	#define CONFIG_BOOTP_BOOTPATH
	54	#define CONFIG_BOOTP_GATEWAY
	55	#define CONFIG_BOOTP_HOSTNAME
	56
	57	/* Command line configuration */
	58	#include <config_cmd_default.h>
	59
	60	#define CONFIG_CMD_CACHE
	61	#define CONFIG_CMD_DATE
	62	#define CONFIG_CMD_ELF
	63	#define CONFIG_CMD_FLASH
	64	#define CONFIG_CMD_I2C
	65	#define CONFIG_CMD_JFFS2
	66	#define CONFIG_CMD_LOADB
	67	#define CONFIG_CMD_LOADS
	68	#define CONFIG_CMD_MEMORY
	69	#define CONFIG_CMD_MISC
	70	#undef CONFIG_CMD_NET
90fa92dc	71	#undef CONFIG_CMD_NFS
1552af70 TL	72	#define CONFIG_CMD_REGINFO
	73	#undef CONFIG_CMD_USB
	74	#undef CONFIG_CMD_BMP
a21d0c2c TL	75	#define CONFIG_CMD_SPI
	76	#define CONFIG_CMD_SF
	77
	78	#define CONFIG_HOSTNAME M52277EVB
	79	#define CONFIG_SYS_UBOOT_END 0x3FFFF
	80	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
	81	#ifdef CONFIG_SYS_STMICRO_BOOT
	82	/* ST Micro serial flash */
1552af70	83	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	84	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	85	"loadaddr=0x40010000\0" \
	86	"uboot=u-boot.bin\0" \
	87	"load=loadb ${loadaddr} ${baudrate};" \
5368c55d	88	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
1552af70	89	"upd=run load; run prog\0" \
a21d0c2c TL	90	"prog=sf probe 0:2 10000 1;" \
	91	"sf erase 0 30000;" \
	92	"sf write ${loadaddr} 0 30000;" \
1552af70 TL	93	"save\0" \
1552af70 TL	94	""
a21d0c2c TL	95	#endif
	96	#ifdef CONFIG_SYS_SPANSION_BOOT
	97	#define CONFIG_EXTRA_ENV_SETTINGS \
5368c55d	98	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
a21d0c2c TL	99	"loadaddr=0x40010000\0" \
	100	"uboot=u-boot.bin\0" \
	101	"load=loadb ${loadaddr} ${baudrate}\0" \
	102	"upd=run load; run prog\0" \
5368c55d MV	103	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	104	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	105	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	106	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	107	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
a21d0c2c TL	108	" ${filesize}; save\0" \
	109	"updsbf=run loadsbf; run progsbf\0" \
	110	"loadsbf=loadb ${loadaddr} ${baudrate};" \
5368c55d	111	"loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \
a21d0c2c TL	112	"progsbf=sf probe 0:2 10000 1;" \
	113	"sf erase 0 30000;" \
	114	"sf write ${loadaddr} 0 30000;" \
	115	""
	116	#endif
1552af70	117
a21d0c2c	118	#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
1552af70 TL	119	/* LCD */
	120	#ifdef CONFIG_CMD_BMP
	121	#define CONFIG_LCD
	122	#define CONFIG_SPLASH_SCREEN
	123	#define CONFIG_LCD_LOGO
	124	#define CONFIG_SHARP_LQ035Q7DH06
	125	#endif
	126
	127	/* USB */
	128	#ifdef CONFIG_CMD_USB
	129	#define CONFIG_USB_EHCI
	130	#define CONFIG_USB_STORAGE
	131	#define CONFIG_DOS_PARTITION
	132	#define CONFIG_MAC_PARTITION
	133	#define CONFIG_ISO_PARTITION
a21d0c2c	134	#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000
6d0f6bcf	135	#define CONFIG_SYS_USB_EHCI_CPU_INIT
1552af70 TL	136	#endif
	137
	138	/* Realtime clock */
	139	#define CONFIG_MCFRTC
	140	#undef RTC_DEBUG
6d0f6bcf	141	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
1552af70 TL	142
	143	/* Timer */
	144	#define CONFIG_MCFTMR
	145	#undef CONFIG_MCFPIT
	146
	147	/* I2c */
	148	#define CONFIG_FSL_I2C
	149	#define CONFIG_HARD_I2C /* I2C with hardware support */
6d0f6bcf JCPV	150	#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
	151	#define CONFIG_SYS_I2C_SLAVE 0x7F
	152	#define CONFIG_SYS_I2C_OFFSET 0x58000
a21d0c2c TL	153	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	154
	155	/* DSPI and Serial Flash */
ee0a8462	156	#define CONFIG_CF_SPI
a21d0c2c TL	157	#define CONFIG_CF_DSPI
a21d0c2c TL	158	#define CONFIG_HARD_SPI
a21d0c2c TL	159	#define CONFIG_SYS_SBFHDR_SIZE 0x7
	160	#ifdef CONFIG_CMD_SPI
	161	# define CONFIG_SYS_DSPI_CS2
	162	# define CONFIG_SPI_FLASH
	163	# define CONFIG_SPI_FLASH_STMICRO
	164
ee0a8462 TL	165	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	166	DSPI_CTAR_PCSSCK_1CLK \| \
	167	DSPI_CTAR_PASC(0) \| \
	168	DSPI_CTAR_PDT(0) \| \
	169	DSPI_CTAR_CSSCK(0) \| \
	170	DSPI_CTAR_ASC(0) \| \
	171	DSPI_CTAR_DT(1))
a21d0c2c	172	#endif
1552af70 TL	173
	174	/* Input, PCI, Flexbus, and VCO */
	175	#define CONFIG_EXTRA_CLOCK
	176
6d0f6bcf	177	#define CONFIG_SYS_INPUT_CLKSRC 16000000
1552af70	178
a21d0c2c	179	#define CONFIG_PRAM 2048 /* 2048 KB */
1552af70	180
a21d0c2c	181	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf	182	#define CONFIG_SYS_LONGHELP /* undef to save memory */
1552af70 TL	183
1552af70 TL	184	#if defined(CONFIG_CMD_KGDB)
a21d0c2c	185	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
1552af70	186	#else
a21d0c2c	187	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
1552af70	188	#endif
a21d0c2c TL	189	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	190	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	191	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
1552af70	192
a21d0c2c	193	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
1552af70	194
a21d0c2c	195	#define CONFIG_SYS_HZ 1000
1552af70	196
6d0f6bcf	197	#define CONFIG_SYS_MBAR 0xFC000000
1552af70 TL	198
	199	/*
	200	* Low Level Configuration Settings
	201	* (address mappings, register initial values, etc.)
	202	* You should know what you are doing if you make changes here.
	203	*/
	204
a21d0c2c	205	/*
1552af70 TL	206	* Definitions for initial stack pointer and data area (in DPRAM)
1552af70 TL	207	*/
6d0f6bcf	208	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	209	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
a21d0c2c	210	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	211	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
a21d0c2c	212	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32)
553f0982	213	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
1552af70	214
a21d0c2c	215	/*
1552af70 TL	216	* Start addresses for the final memory configuration
1552af70 TL	217	* (Set up by the startup code)
6d0f6bcf	218	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
1552af70	219	*/
6d0f6bcf JCPV	220	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	221	#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */
	222	#define CONFIG_SYS_SDRAM_CFG1 0x43711630
	223	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	224	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	225	#define CONFIG_SYS_SDRAM_EMOD 0x81810000
	226	#define CONFIG_SYS_SDRAM_MODE 0x00CD0000
a21d0c2c	227	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00
6d0f6bcf JCPV	228
	229	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	230	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
	231
a21d0c2c	232	#ifdef CONFIG_CF_SBF
14d0a02a	233	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
a21d0c2c TL	234	#else
	235	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
	236	#endif
6d0f6bcf JCPV	237	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	238	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	239	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
1552af70 TL	240
1552af70 TL	241	/* Initial Memory map for Linux */
6d0f6bcf	242	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	243	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
1552af70	244
a21d0c2c TL	245	/*
a21d0c2c TL	246	* Configuration for environment
27f7ae70 JJ	247	* Environment is not embedded in u-boot. First time runing may have env
27f7ae70 JJ	248	* crc error warning if there is no correct environment on the flash.
1552af70	249	*/
a21d0c2c TL	250	#ifdef CONFIG_CF_SBF
	251	# define CONFIG_ENV_IS_IN_SPI_FLASH
	252	# define CONFIG_ENV_SPI_CS 2
	253	#else
	254	# define CONFIG_ENV_IS_IN_FLASH 1
	255	#endif
	256	#define CONFIG_ENV_OVERWRITE 1
1552af70 TL	257
	258	/*-----------------------------------------------------------------------
	259	* FLASH organization
	260	*/
a21d0c2c	261	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462	262	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
27f7ae70	263	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
a21d0c2c TL	264	# define CONFIG_ENV_OFFSET 0x30000
	265	# define CONFIG_ENV_SIZE 0x1000
	266	# define CONFIG_ENV_SECT_SIZE 0x10000
	267	#endif
	268	#ifdef CONFIG_SYS_SPANSION_BOOT
	269	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	270	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
27f7ae70	271	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
a21d0c2c TL	272	# define CONFIG_ENV_SIZE 0x1000
	273	# define CONFIG_ENV_SECT_SIZE 0x8000
	274	#endif
1552af70	275
6d0f6bcf JCPV	276	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	277	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	278	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff TL	279	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
bbf6bbff TL	280	# define CONFIG_FLASH_SPANSION_S29WS_N 1
6d0f6bcf JCPV	281	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	282	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	283	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	284	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	285	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	286	# define CONFIG_SYS_FLASH_CHECKSUM
a21d0c2c	287	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
1552af70 TL	288	#endif
	289
	290	/*
	291	* This is setting for JFFS2 support in u-boot.
	292	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	293	*/
	294	#ifdef CONFIG_CMD_JFFS2
	295	# define CONFIG_JFFS2_DEV "nor0"
	296	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000)
6d0f6bcf	297	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000)
1552af70 TL	298	#endif
	299
	300	/*-----------------------------------------------------------------------
	301	* Cache Configuration
	302	*/
a21d0c2c	303	#define CONFIG_SYS_CACHELINE_SIZE 16
1552af70	304
dd9f054e	305	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	306	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	307	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	308	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	309	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	310	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	311	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	312	CF_ACR_EN \| CF_ACR_SM_ALL)
	313	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	314	CF_CACR_DISD \| CF_CACR_INVI \| \
	315	CF_CACR_CEIB \| CF_CACR_DCM \| \
	316	CF_CACR_EUSP)
	317
1552af70 TL	318	/*-----------------------------------------------------------------------
	319	* Memory bank definitions
	320	*/
	321	/*
	322	* CS0 - NOR Flash
	323	* CS1 - Available
	324	* CS2 - Available
	325	* CS3 - Available
	326	* CS4 - Available
	327	* CS5 - Available
	328	*/
	329
a21d0c2c TL	330	#ifdef CONFIG_CF_SBF
	331	#define CONFIG_SYS_CS0_BASE 0x04000000
	332	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	333	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
	334	#else
6d0f6bcf JCPV	335	#define CONFIG_SYS_CS0_BASE 0x00000000
	336	#define CONFIG_SYS_CS0_MASK 0x00FF0001
	337	#define CONFIG_SYS_CS0_CTRL 0x00001FA0
a21d0c2c	338	#endif
1552af70 TL	339
1552af70 TL	340	#endif /* _M52277EVB_H */