[people/ms/u-boot.git] / include / configs / M5235EVB.h

/*
 * Configuation settings for the Freescale MCF5329 FireEngine board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5235EVB_H
#define _M5235EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_i2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000300
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(gpio->par_qspi)
#define CONFIG_SYS_I2C_PINMUX_CLR	~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
#define CONFIG_SYS_I2C_PINMUX_SET	(GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#define CONFIG_BOOTFILE		"u-boot.bin"
#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M5235EVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE+0x20000)

#define CONFIG_SYS_CLK			75000000
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2

#define CONFIG_SYS_MBAR		0x40000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x21
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#ifdef NORFLASH_PS32BIT
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_32BIT
#else
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#endif
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text);

#ifdef NORFLASH_PS32BIT
#	define CONFIG_ENV_OFFSET		(0x8000)
#	define CONFIG_ENV_SIZE		0x4000
#	define CONFIG_ENV_SECT_SIZE	0x4000
#else
#	define CONFIG_ENV_OFFSET		(0x4000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x2000
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 * CS6 - Available
 * CS7 - Available
 */
#ifdef NORFLASH_PS32BIT
#	define CONFIG_SYS_CS0_BASE	0xFFC00000
#	define CONFIG_SYS_CS0_MASK	0x003f0001
#	define CONFIG_SYS_CS0_CTRL	0x00001D00
#else
#	define CONFIG_SYS_CS0_BASE	0xFFE00000
#	define CONFIG_SYS_CS0_MASK	0x001f0001
#	define CONFIG_SYS_CS0_CTRL	0x00001D80
#endif

#endif				/* _M5329EVB_H */
Commit	Line	Data
4a442d31 TL	1	/*
	2	* Configuation settings for the Freescale MCF5329 FireEngine board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
4a442d31 TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M5235EVB_H
	15	#define _M5235EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
4a442d31	21
4a442d31	22	#define CONFIG_MCFUART
6d0f6bcf	23	#define CONFIG_SYS_UART_PORT (0)
4a442d31 TL	24
	25	#undef CONFIG_WATCHDOG
	26	#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
	27
	28	/*
	29	* BOOTP options
	30	*/
	31	#define CONFIG_BOOTP_BOOTFILESIZE
4a442d31	32
4a442d31 TL	33	#define CONFIG_MCFFEC
4a442d31 TL	34	#ifdef CONFIG_MCFFEC
4a442d31	35	# define CONFIG_MII 1
0f3ba7e9	36	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	37	# define CONFIG_SYS_DISCOVER_PHY
	38	# define CONFIG_SYS_RX_ETH_BUFFER 8
	39	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31	40
6d0f6bcf JCPV	41	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	42	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	43	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	44	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	45	# ifndef CONFIG_SYS_DISCOVER_PHY
4a442d31 TL	46	# define FECDUPLEX FULL
	47	# define FECSPEED _100BASET
	48	# else
6d0f6bcf JCPV	49	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	50	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31	51	# endif
6d0f6bcf	52	# endif /* CONFIG_SYS_DISCOVER_PHY */
4a442d31 TL	53	#endif
	54
	55	/* Timer */
	56	#define CONFIG_MCFTMR
	57	#undef CONFIG_MCFPIT
	58
	59	/* I2C */
00f792e0 HS	60	#define CONFIG_SYS_I2C
	61	#define CONFIG_SYS_i2C_FSL
	62	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	63	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	64	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
6d0f6bcf JCPV	65	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	66	#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
	67	#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK \| GPIO_PAR_FECI2C_SDA_MASK)
	68	#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL \| GPIO_PAR_FECI2C_SDA_I2CSDA)
4a442d31 TL	69
4a442d31 TL	70	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
4a442d31 TL	71	#define CONFIG_BOOTFILE "u-boot.bin"
4a442d31 TL	72	#ifdef CONFIG_MCFFEC
4a442d31 TL	73	# define CONFIG_IPADDR 192.162.1.2
	74	# define CONFIG_NETMASK 255.255.255.0
	75	# define CONFIG_SERVERIP 192.162.1.1
	76	# define CONFIG_GATEWAYIP 192.162.1.1
4a442d31 TL	77	#endif /* FEC_ENET */
	78
	79	#define CONFIG_HOSTNAME M5235EVB
	80	#define CONFIG_EXTRA_ENV_SETTINGS \
	81	"netdev=eth0\0" \
	82	"loadaddr=10000\0" \
	83	"u-boot=u-boot.bin\0" \
	84	"load=tftp ${loadaddr) ${u-boot}\0" \
	85	"upd=run load; run prog\0" \
	86	"prog=prot off ffe00000 ffe3ffff;" \
	87	"era ffe00000 ffe3ffff;" \
	88	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	89	"save\0" \
	90	""
	91
	92	#define CONFIG_PRAM 512 /* 512 KB */
4a442d31	93
6d0f6bcf	94	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
4a442d31	95
6d0f6bcf JCPV	96	#define CONFIG_SYS_CLK 75000000
6d0f6bcf JCPV	97	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
4a442d31	98
6d0f6bcf	99	#define CONFIG_SYS_MBAR 0x40000000
4a442d31 TL	100
	101	/*
	102	* Low Level Configuration Settings
	103	* (address mappings, register initial values, etc.)
	104	* You should know what you are doing if you make changes here.
	105	*/
	106	/*-----------------------------------------------------------------------
	107	* Definitions for initial stack pointer and data area (in DPRAM)
	108	*/
6d0f6bcf	109	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	110	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
6d0f6bcf	111	#define CONFIG_SYS_INIT_RAM_CTRL 0x21
25ddd1fb	112	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
6d0f6bcf	113	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
4a442d31 TL	114
	115	/*-----------------------------------------------------------------------
	116	* Start addresses for the final memory configuration
	117	* (Set up by the startup code)
6d0f6bcf	118	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
4a442d31	119	*/
6d0f6bcf JCPV	120	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	121	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
4a442d31	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	124	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
4a442d31	125
6d0f6bcf JCPV	126	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	127	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
4a442d31	128
6d0f6bcf JCPV	129	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	130	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
4a442d31 TL	131
	132	/*
	133	* For booting Linux, the board info and command line data
	134	* have to be in the first 8 MB of memory, since this is
	135	* the maximum mapped by the Linux kernel during initialization ??
	136	*/
	137	/* Initial Memory map for Linux */
6d0f6bcf	138	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	139	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
4a442d31 TL	140
	141	/*-----------------------------------------------------------------------
	142	* FLASH organization
	143	*/
6d0f6bcf JCPV	144	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	145	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	146	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf	147	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
4a442d31	148	#ifdef NORFLASH_PS32BIT
6d0f6bcf	149	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
4a442d31	150	#else
6d0f6bcf	151	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
4a442d31	152	#endif
6d0f6bcf JCPV	153	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	154	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	155	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
4a442d31 TL	156	#endif
4a442d31 TL	157
012522fe	158	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
4a442d31 TL	159
	160	/* Configuration for environment
	161	* Environment is embedded in u-boot in the second sector of the flash
	162	*/
5296cb1d	163
	164	#define LDS_BOARD_TEXT \
	165	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d	166	env/embedded.o(.text);
5296cb1d	167
4a442d31	168	#ifdef NORFLASH_PS32BIT
0e8d1586 JCPV	169	# define CONFIG_ENV_OFFSET (0x8000)
	170	# define CONFIG_ENV_SIZE 0x4000
	171	# define CONFIG_ENV_SECT_SIZE 0x4000
4a442d31	172	#else
0e8d1586 JCPV	173	# define CONFIG_ENV_OFFSET (0x4000)
	174	# define CONFIG_ENV_SIZE 0x2000
	175	# define CONFIG_ENV_SECT_SIZE 0x2000
4a442d31 TL	176	#endif
	177
	178	/*-----------------------------------------------------------------------
	179	* Cache Configuration
	180	*/
6d0f6bcf	181	#define CONFIG_SYS_CACHELINE_SIZE 16
4a442d31	182
dd9f054e	183	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	184	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	185	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	186	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	187	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
	188	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	189	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	190	CF_ACR_EN \| CF_ACR_SM_ALL)
	191	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_DISD \| \
	192	CF_CACR_CEIB \| CF_CACR_DCM \| \
	193	CF_CACR_EUSP)
	194
4a442d31 TL	195	/*-----------------------------------------------------------------------
	196	* Chipselect bank definitions
	197	*/
	198	/*
	199	* CS0 - NOR Flash 1, 2, 4, or 8MB
	200	* CS1 - Available
	201	* CS2 - Available
	202	* CS3 - Available
	203	* CS4 - Available
	204	* CS5 - Available
	205	* CS6 - Available
	206	* CS7 - Available
	207	*/
	208	#ifdef NORFLASH_PS32BIT
012522fe	209	# define CONFIG_SYS_CS0_BASE 0xFFC00000
6d0f6bcf	210	# define CONFIG_SYS_CS0_MASK 0x003f0001
012522fe	211	# define CONFIG_SYS_CS0_CTRL 0x00001D00
4a442d31	212	#else
012522fe	213	# define CONFIG_SYS_CS0_BASE 0xFFE00000
6d0f6bcf	214	# define CONFIG_SYS_CS0_MASK 0x001f0001
012522fe	215	# define CONFIG_SYS_CS0_CTRL 0x00001D80
4a442d31 TL	216	#endif
	217
	218	#endif /* _M5329EVB_H */