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include/configs: drop default definitions of CONFIG_SYS_MAXARGS
[people/ms/u-boot.git] / include / configs / M5235EVB.h
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1/*
2 * Configuation settings for the Freescale MCF5329 FireEngine board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
3765b3e7 7 * SPDX-License-Identifier: GPL-2.0+
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8 */
9
10/*
11 * board/config.h - configuration options, board specific
12 */
13
14#ifndef _M5235EVB_H
15#define _M5235EVB_H
16
17/*
18 * High Level Configuration Options
19 * (easy to change)
20 */
4a442d31 21
4a442d31 22#define CONFIG_MCFUART
6d0f6bcf 23#define CONFIG_SYS_UART_PORT (0)
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24
25#undef CONFIG_WATCHDOG
26#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
27
28/*
29 * BOOTP options
30 */
31#define CONFIG_BOOTP_BOOTFILESIZE
32#define CONFIG_BOOTP_BOOTPATH
33#define CONFIG_BOOTP_GATEWAY
34#define CONFIG_BOOTP_HOSTNAME
35
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36#define CONFIG_MCFFEC
37#ifdef CONFIG_MCFFEC
4a442d31 38# define CONFIG_MII 1
0f3ba7e9 39# define CONFIG_MII_INIT 1
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40# define CONFIG_SYS_DISCOVER_PHY
41# define CONFIG_SYS_RX_ETH_BUFFER 8
42# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31 43
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44# define CONFIG_SYS_FEC0_PINMUX 0
45# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1 46# define MCFFEC_TOUT_LOOP 50000
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47/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
48# ifndef CONFIG_SYS_DISCOVER_PHY
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49# define FECDUPLEX FULL
50# define FECSPEED _100BASET
51# else
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52# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
53# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
4a442d31 54# endif
6d0f6bcf 55# endif /* CONFIG_SYS_DISCOVER_PHY */
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56#endif
57
58/* Timer */
59#define CONFIG_MCFTMR
60#undef CONFIG_MCFPIT
61
62/* I2C */
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63#define CONFIG_SYS_I2C
64#define CONFIG_SYS_i2C_FSL
65#define CONFIG_SYS_FSL_I2C_SPEED 80000
66#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
67#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300
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68#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
69#define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi)
70#define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
71#define CONFIG_SYS_I2C_PINMUX_SET (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
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72
73/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
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74#define CONFIG_BOOTFILE "u-boot.bin"
75#ifdef CONFIG_MCFFEC
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76# define CONFIG_IPADDR 192.162.1.2
77# define CONFIG_NETMASK 255.255.255.0
78# define CONFIG_SERVERIP 192.162.1.1
79# define CONFIG_GATEWAYIP 192.162.1.1
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80#endif /* FEC_ENET */
81
82#define CONFIG_HOSTNAME M5235EVB
83#define CONFIG_EXTRA_ENV_SETTINGS \
84 "netdev=eth0\0" \
85 "loadaddr=10000\0" \
86 "u-boot=u-boot.bin\0" \
87 "load=tftp ${loadaddr) ${u-boot}\0" \
88 "upd=run load; run prog\0" \
89 "prog=prot off ffe00000 ffe3ffff;" \
90 "era ffe00000 ffe3ffff;" \
91 "cp.b ${loadaddr} ffe00000 ${filesize};"\
92 "save\0" \
93 ""
94
95#define CONFIG_PRAM 512 /* 512 KB */
6d0f6bcf 96#define CONFIG_SYS_LONGHELP /* undef to save memory */
4a442d31 97
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98#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
99#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000)
4a442d31 100
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101#define CONFIG_SYS_CLK 75000000
102#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
4a442d31 103
6d0f6bcf 104#define CONFIG_SYS_MBAR 0x40000000
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105
106/*
107 * Low Level Configuration Settings
108 * (address mappings, register initial values, etc.)
109 * You should know what you are doing if you make changes here.
110 */
111/*-----------------------------------------------------------------------
112 * Definitions for initial stack pointer and data area (in DPRAM)
113 */
6d0f6bcf 114#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982 115#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
6d0f6bcf 116#define CONFIG_SYS_INIT_RAM_CTRL 0x21
25ddd1fb 117#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
6d0f6bcf 118#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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119
120/*-----------------------------------------------------------------------
121 * Start addresses for the final memory configuration
122 * (Set up by the startup code)
6d0f6bcf 123 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
4a442d31 124 */
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125#define CONFIG_SYS_SDRAM_BASE 0x00000000
126#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
4a442d31 127
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128#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
129#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
4a442d31 130
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131#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
132#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
4a442d31 133
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134#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
135#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
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136
137/*
138 * For booting Linux, the board info and command line data
139 * have to be in the first 8 MB of memory, since this is
140 * the maximum mapped by the Linux kernel during initialization ??
141 */
142/* Initial Memory map for Linux */
6d0f6bcf 143#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4 144#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
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145
146/*-----------------------------------------------------------------------
147 * FLASH organization
148 */
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149#define CONFIG_SYS_FLASH_CFI
150#ifdef CONFIG_SYS_FLASH_CFI
00b1883a 151# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf 152# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
4a442d31 153#ifdef NORFLASH_PS32BIT
6d0f6bcf 154# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_32BIT
4a442d31 155#else
6d0f6bcf 156# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
4a442d31 157#endif
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158# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
159# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
160# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
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161#endif
162
012522fe 163#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
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164
165/* Configuration for environment
166 * Environment is embedded in u-boot in the second sector of the flash
167 */
5296cb1d 168
169#define LDS_BOARD_TEXT \
170 . = DEFINED(env_offset) ? env_offset : .; \
0649cd0d 171 env/embedded.o(.text);
5296cb1d 172
4a442d31 173#ifdef NORFLASH_PS32BIT
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174# define CONFIG_ENV_OFFSET (0x8000)
175# define CONFIG_ENV_SIZE 0x4000
176# define CONFIG_ENV_SECT_SIZE 0x4000
4a442d31 177#else
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178# define CONFIG_ENV_OFFSET (0x4000)
179# define CONFIG_ENV_SIZE 0x2000
180# define CONFIG_ENV_SECT_SIZE 0x2000
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181#endif
182
183/*-----------------------------------------------------------------------
184 * Cache Configuration
185 */
6d0f6bcf 186#define CONFIG_SYS_CACHELINE_SIZE 16
4a442d31 187
dd9f054e 188#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982 189 CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e 190#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982 191 CONFIG_SYS_INIT_RAM_SIZE - 4)
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192#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV)
193#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
194 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
195 CF_ACR_EN | CF_ACR_SM_ALL)
196#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
197 CF_CACR_CEIB | CF_CACR_DCM | \
198 CF_CACR_EUSP)
199
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200/*-----------------------------------------------------------------------
201 * Chipselect bank definitions
202 */
203/*
204 * CS0 - NOR Flash 1, 2, 4, or 8MB
205 * CS1 - Available
206 * CS2 - Available
207 * CS3 - Available
208 * CS4 - Available
209 * CS5 - Available
210 * CS6 - Available
211 * CS7 - Available
212 */
213#ifdef NORFLASH_PS32BIT
012522fe 214# define CONFIG_SYS_CS0_BASE 0xFFC00000
6d0f6bcf 215# define CONFIG_SYS_CS0_MASK 0x003f0001
012522fe 216# define CONFIG_SYS_CS0_CTRL 0x00001D00
4a442d31 217#else
012522fe 218# define CONFIG_SYS_CS0_BASE 0xFFE00000
6d0f6bcf 219# define CONFIG_SYS_CS0_MASK 0x001f0001
012522fe 220# define CONFIG_SYS_CS0_CTRL 0x00001D80
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221#endif
222
223#endif /* _M5329EVB_H */