[people/ms/u-boot.git] / include / configs / M5253DEMO.h

/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _M5253DEMO_H
#define _M5253DEMO_H

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG		/* disable watchdog */


/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_ENV_OFFSET		0x4000
#	define CONFIG_ENV_SECT_SIZE	0x1000
#else
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x4000)
#	define CONFIG_ENV_SECT_SIZE	0x1000
#endif

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text*);

/*
 * Command line configuration.
 */

#ifdef CONFIG_IDE
/* ATA */
#	define CONFIG_IDE_RESET		1
#	define CONFIG_IDE_PREINIT	1
#	define CONFIG_ATAPI
#	undef CONFIG_LBA48

#	define CONFIG_SYS_IDE_MAXBUS		1
#	define CONFIG_SYS_IDE_MAXDEVICE	2

#	define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#	define CONFIG_SYS_ATA_IDE0_OFFSET	0

#	define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#	define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#	define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#	define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */
#endif

#define CONFIG_DRIVER_DM9000
#ifdef CONFIG_DRIVER_DM9000
#	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
#	define DM9000_IO		CONFIG_DM9000_BASE
#	define DM9000_DATA		(CONFIG_DM9000_BASE + 4)
#	undef CONFIG_DM9000_DEBUG
#	define CONFIG_DM9000_BYTE_SWAPPED

#	define CONFIG_OVERWRITE_ETHADDR_ONCE

#	define CONFIG_EXTRA_ENV_SETTINGS		\
		"netdev=eth0\0"				\
		"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
		"loadaddr=10000\0"			\
		"u-boot=u-boot.bin\0"			\
		"load=tftp ${loadaddr) ${u-boot}\0"	\
		"upd=run load; run prog\0"		\
		"prog=prot off 0xff800000 0xff82ffff;"	\
		"era 0xff800000 0xff82ffff;"		\
		"cp.b ${loadaddr} 0xff800000 ${filesize};"	\
		"save\0"				\
		""
#endif

#define CONFIG_HOSTNAME		M5253DEMO

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00000280
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR
#define CONFIG_SYS_I2C_PINMUX_REG	(*(u32 *) (CONFIG_SYS_MBAR+0x19C))
#define CONFIG_SYS_I2C_PINMUX_CLR	(0xFFFFE7FF)
#define CONFIG_SYS_I2C_PINMUX_SET	(0)

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#	define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define FLASH_SST6401B		0x200
#define SST_ID_xF6401B		0x236D236D

#undef CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
/*
 * Unable to use CFI driver, due to incompatible sector erase command by SST.
 * Amd/Atmel use 0x30 for sector erase, SST use 0x50.
 * 0x30 is block erase in SST
 */
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_FLASH_CFI_LEGACY
#else
#	define CONFIG_SYS_SST_SECT		2048
#	define CONFIG_SYS_SST_SECTSZ		0x1000
#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(8) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		0x007F0021
#define CONFIG_SYS_CS0_CTRL		0x00001D80

#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		0x00000001
#define CONFIG_SYS_CS1_CTRL		0x00003DD8

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253DEMO_H */
Commit	Line	Data
6af3a0ea	1	/* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6d33c6ac TL	2	* Hayden Fraser (Hayden.Fraser@freescale.com)
6d33c6ac TL	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
6d33c6ac TL	5	*/
	6
	7	#ifndef _M5253DEMO_H
	8	#define _M5253DEMO_H
	9
6d33c6ac TL	10	#define CONFIG_MCFTMR
	11
	12	#define CONFIG_MCFUART
6d0f6bcf	13	#define CONFIG_SYS_UART_PORT (0)
6d33c6ac TL	14
	15	#undef CONFIG_WATCHDOG /* disable watchdog */
	16
6d33c6ac TL	17
	18	/* Configuration for environment
	19	* Environment is embedded in u-boot in the second sector of the flash
	20	*/
	21	#ifdef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	22	# define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	23	# define CONFIG_ENV_SECT_SIZE 0x1000
6d33c6ac	24	#else
6d0f6bcf	25	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
0e8d1586	26	# define CONFIG_ENV_SECT_SIZE 0x1000
6d33c6ac TL	27	#endif
6d33c6ac TL	28
5296cb1d	29	#define LDS_BOARD_TEXT \
0649cd0d SG	30	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	31	env/embedded.o(.text*);
5296cb1d	32
6d33c6ac TL	33	/*
	34	* Command line configuration.
	35	*/
6d33c6ac	36
fc843a02	37	#ifdef CONFIG_IDE
6d33c6ac	38	/* ATA */
6d33c6ac TL	39	# define CONFIG_IDE_RESET 1
	40	# define CONFIG_IDE_PREINIT 1
	41	# define CONFIG_ATAPI
	42	# undef CONFIG_LBA48
	43
6d0f6bcf JCPV	44	# define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	45	# define CONFIG_SYS_IDE_MAXDEVICE 2
6d33c6ac	46
6d0f6bcf JCPV	47	# define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	48	# define CONFIG_SYS_ATA_IDE0_OFFSET 0
6d33c6ac	49
6d0f6bcf JCPV	50	# define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	51	# define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	52	# define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	53	# define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
6d33c6ac TL	54	#endif
	55
	56	#define CONFIG_DRIVER_DM9000
	57	#ifdef CONFIG_DRIVER_DM9000
012522fe	58	# define CONFIG_DM9000_BASE (CONFIG_SYS_CS1_BASE \| 0x300)
6d33c6ac TL	59	# define DM9000_IO CONFIG_DM9000_BASE
	60	# define DM9000_DATA (CONFIG_DM9000_BASE + 4)
	61	# undef CONFIG_DM9000_DEBUG
f73e7d67	62	# define CONFIG_DM9000_BYTE_SWAPPED
6d33c6ac	63
6d33c6ac TL	64	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	65
	66	# define CONFIG_EXTRA_ENV_SETTINGS \
	67	"netdev=eth0\0" \
5368c55d	68	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
6d33c6ac TL	69	"loadaddr=10000\0" \
	70	"u-boot=u-boot.bin\0" \
	71	"load=tftp ${loadaddr) ${u-boot}\0" \
	72	"upd=run load; run prog\0" \
ac265f7f TL	73	"prog=prot off 0xff800000 0xff82ffff;" \
ac265f7f TL	74	"era 0xff800000 0xff82ffff;" \
f26a2473	75	"cp.b ${loadaddr} 0xff800000 ${filesize};" \
6d33c6ac TL	76	"save\0" \
	77	""
	78	#endif
	79
	80	#define CONFIG_HOSTNAME M5253DEMO
	81
eec567a6	82	/* I2C */
00f792e0 HS	83	#define CONFIG_SYS_I2C
	84	#define CONFIG_SYS_I2C_FSL
	85	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	86	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	87	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000280
6d0f6bcf JCPV	88	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
	89	#define CONFIG_SYS_I2C_PINMUX_REG ((u32 ) (CONFIG_SYS_MBAR+0x19C))
	90	#define CONFIG_SYS_I2C_PINMUX_CLR (0xFFFFE7FF)
	91	#define CONFIG_SYS_I2C_PINMUX_SET (0)
eec567a6	92
6d0f6bcf	93	#define CONFIG_SYS_LOAD_ADDR 0x00100000
6d33c6ac	94
6d0f6bcf JCPV	95	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	96	#define CONFIG_SYS_MEMTEST_END 0x380000
6d33c6ac	97
6d0f6bcf JCPV	98	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	99	#define CONFIG_SYS_FAST_CLK
	100	#ifdef CONFIG_SYS_FAST_CLK
	101	# define CONFIG_SYS_PLLCR 0x1243E054
	102	# define CONFIG_SYS_CLK 140000000
6d33c6ac	103	#else
6d0f6bcf JCPV	104	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	105	# define CONFIG_SYS_CLK 70000000
6d33c6ac TL	106	#endif
	107
	108	/*
	109	* Low Level Configuration Settings
	110	* (address mappings, register initial values, etc.)
	111	* You should know what you are doing if you make changes here.
	112	*/
	113
6d0f6bcf JCPV	114	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	115	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
6d33c6ac TL	116
	117	/*
	118	* Definitions for initial stack pointer and data area (in DPRAM)
	119	*/
6d0f6bcf	120	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	121	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	122	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	123	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6d33c6ac TL	124
	125	/*
	126	* Start addresses for the final memory configuration
	127	* (Set up by the startup code)
6d0f6bcf	128	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6d33c6ac	129	*/
6d0f6bcf JCPV	130	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	131	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
6d33c6ac TL	132
6d33c6ac TL	133	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	134	# define CONFIG_SYS_MONITOR_BASE 0x20000
6d33c6ac	135	#else
6d0f6bcf	136	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d33c6ac TL	137	#endif
6d33c6ac TL	138
6d0f6bcf JCPV	139	#define CONFIG_SYS_MONITOR_LEN 0x40000
	140	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	141	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
6d33c6ac TL	142
	143	/*
	144	* For booting Linux, the board info and command line data
	145	* have to be in the first 8 MB of memory, since this is
	146	* the maximum mapped by the Linux kernel during initialization ??
	147	*/
6d0f6bcf	148	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	149	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
6d33c6ac TL	150
6d33c6ac TL	151	/* FLASH organization */
012522fe	152	#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
6d0f6bcf JCPV	153	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	154	#define CONFIG_SYS_MAX_FLASH_SECT 2048 /* max number of sectors on one chip */
	155	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
6d33c6ac TL	156
	157	#define FLASH_SST6401B 0x200
	158	#define SST_ID_xF6401B 0x236D236D
	159
6d0f6bcf JCPV	160	#undef CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	161	#ifdef CONFIG_SYS_FLASH_CFI
6d33c6ac TL	162	/*
	163	* Unable to use CFI driver, due to incompatible sector erase command by SST.
	164	* Amd/Atmel use 0x30 for sector erase, SST use 0x50.
	165	* 0x30 is block erase in SST
	166	*/
0de0afbc	167	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	168	# define CONFIG_SYS_FLASH_SIZE 0x800000
6d0f6bcf JCPV	169	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
6d33c6ac TL	170	# define CONFIG_FLASH_CFI_LEGACY
6d33c6ac TL	171	#else
6d0f6bcf JCPV	172	# define CONFIG_SYS_SST_SECT 2048
	173	# define CONFIG_SYS_SST_SECTSZ 0x1000
	174	# define CONFIG_SYS_FLASH_WRITE_TOUT 500
6d33c6ac TL	175	#endif
	176
	177	/* Cache Configuration */
6d0f6bcf	178	#define CONFIG_SYS_CACHELINE_SIZE 16
6d33c6ac	179
dd9f054e	180	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	181	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	182	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	183	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	184	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	185	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	186	CF_ADDRMASK(8) \| \
	187	CF_ACR_EN \| CF_ACR_SM_ALL)
	188	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	189	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	190	CF_ACR_EN \| CF_ACR_SM_ALL)
	191	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	192	CF_CACR_DBWE)
	193
6d33c6ac	194	/* Port configuration */
6d0f6bcf	195	#define CONFIG_SYS_FECI2C 0xF0
6d33c6ac	196
012522fe TL	197	#define CONFIG_SYS_CS0_BASE 0xFF800000
	198	#define CONFIG_SYS_CS0_MASK 0x007F0021
	199	#define CONFIG_SYS_CS0_CTRL 0x00001D80
6d33c6ac	200
012522fe TL	201	#define CONFIG_SYS_CS1_BASE 0xE0000000
	202	#define CONFIG_SYS_CS1_MASK 0x00000001
	203	#define CONFIG_SYS_CS1_CTRL 0x00003DD8
6d33c6ac TL	204
	205	/*-----------------------------------------------------------------------
	206	* Port configuration
	207	*/
6d0f6bcf JCPV	208	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	209	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	210	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	211	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	212	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	213	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	214	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
6d33c6ac TL	215
6d33c6ac TL	216	#endif /* _M5253DEMO_H */