[people/ms/u-boot.git] / include / configs / M5253EVBE.h

/*
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * Hayden Fraser (Hayden.Fraser@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _M5253EVBE_H
#define _M5253EVBE_H

#define CONFIG_M5253EVBE	/* define board type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG		/* disable watchdog */


/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	common/env_embedded.o      (.text)

/*
 * BOOTP options
 */
#undef CONFIG_BOOTP_BOOTFILESIZE
#undef CONFIG_BOOTP_BOOTPATH
#undef CONFIG_BOOTP_GATEWAY
#undef CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_IDE

/* ATA */
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT	1
#define CONFIG_ATAPI
#undef CONFIG_LBA48

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_BASE_ADDR	(CONFIG_SYS_MBAR2 + 0x800)
#define CONFIG_SYS_ATA_IDE0_OFFSET	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O */
#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers */
#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#undef CONFIG_SYS_PLL_BYPASS		/* bypass PLL for test purpose */
#define CONFIG_SYS_FAST_CLK
#ifdef CONFIG_SYS_FAST_CLK
#	define CONFIG_SYS_PLLCR	0x1243E054
#	define CONFIG_SYS_CLK		140000000
#else
#	define CONFIG_SYS_PLLCR	0x135a4140
#	define CONFIG_SYS_CLK		70000000
#endif

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_MBAR2		0x80000000	/* Module Base Addrs 2 */

/*
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		8	/* SDRAM size in MB */

#ifdef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x40000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	(64*1024)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#define CONFIG_SYS_MAX_FLASH_SECT	35	/* max number of sectors on one chip */
#define CONFIG_SYS_FLASH_ERASE_TOUT	1000

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#define CONFIG_SYS_FLASH_SIZE		0x200000
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_FLASH_BASE | \
					 CF_ADDRMASK(2) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ACR1		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
					 CF_CACR_DBWE)

/* Port configuration */
#define CONFIG_SYS_FECI2C		0xF0

#define CONFIG_SYS_CS0_BASE		0xFFE00000
#define CONFIG_SYS_CS0_MASK		0x001F0021
#define CONFIG_SYS_CS0_CTRL		0x00001D80

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_GPIO_FUNC		0x00000008	/* Set gpio pins: none */
#define CONFIG_SYS_GPIO1_FUNC		0x00df00f0	/* 36-39(SWITCH),48-52(FPGAs),54 */
#define CONFIG_SYS_GPIO_EN		0x00000008	/* Set gpio output enable */
#define CONFIG_SYS_GPIO1_EN		0x00c70000	/* Set gpio output enable */
#define CONFIG_SYS_GPIO_OUT		0x00000008	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_OUT		0x00c70000	/* Set outputs to default state */
#define CONFIG_SYS_GPIO1_LED		0x00400000	/* user led */

#endif				/* _M5253EVB_H */
Commit	Line	Data
a1436a84 TL	1	/*
	2	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	3	* Hayden Fraser (Hayden.Fraser@freescale.com)
	4	*
3765b3e7	5	* SPDX-License-Identifier: GPL-2.0+
a1436a84 TL	6	*/
	7
	8	#ifndef _M5253EVBE_H
	9	#define _M5253EVBE_H
	10
a1436a84 TL	11	#define CONFIG_M5253EVBE /* define board type */
	12
	13	#define CONFIG_MCFTMR
	14
	15	#define CONFIG_MCFUART
6d0f6bcf	16	#define CONFIG_SYS_UART_PORT (0)
80ba61fd	17	#define CONFIG_BAUDRATE 115200
a1436a84 TL	18
	19	#undef CONFIG_WATCHDOG /* disable watchdog */
	20
a1436a84 TL	21
	22	/* Configuration for environment
	23	* Environment is embedded in u-boot in the second sector of the flash
	24	*/
	25	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	26	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	27	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	28	#define CONFIG_ENV_IS_IN_FLASH 1
a1436a84	29	#else
0e8d1586 JCPV	30	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	31	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	32	#define CONFIG_ENV_IS_IN_FLASH 1
a1436a84 TL	33	#endif
a1436a84 TL	34
5296cb1d	35	#define LDS_BOARD_TEXT \
	36	. = DEFINED(env_offset) ? env_offset : .; \
	37	common/env_embedded.o (.text)
	38
a1436a84 TL	39	/*
	40	* BOOTP options
	41	*/
	42	#undef CONFIG_BOOTP_BOOTFILESIZE
	43	#undef CONFIG_BOOTP_BOOTPATH
	44	#undef CONFIG_BOOTP_GATEWAY
	45	#undef CONFIG_BOOTP_HOSTNAME
	46
	47	/*
	48	* Command line configuration.
	49	*/
a1436a84	50	#define CONFIG_CMD_IDE
a1436a84 TL	51
	52	/* ATA */
	53	#define CONFIG_DOS_PARTITION
	54	#define CONFIG_MAC_PARTITION
	55	#define CONFIG_IDE_RESET 1
	56	#define CONFIG_IDE_PREINIT 1
	57	#define CONFIG_ATAPI
	58	#undef CONFIG_LBA48
	59
6d0f6bcf JCPV	60	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	61	#define CONFIG_SYS_IDE_MAXDEVICE 2
a1436a84	62
6d0f6bcf JCPV	63	#define CONFIG_SYS_ATA_BASE_ADDR (CONFIG_SYS_MBAR2 + 0x800)
6d0f6bcf JCPV	64	#define CONFIG_SYS_ATA_IDE0_OFFSET 0
a1436a84	65
6d0f6bcf JCPV	66	#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	67	#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	68	#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	69	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
a1436a84	70
6d0f6bcf	71	#define CONFIG_SYS_LONGHELP /* undef to save memory */
a1436a84 TL	72
a1436a84 TL	73	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	74	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
a1436a84	75	#else
6d0f6bcf	76	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
a1436a84	77	#endif
6d0f6bcf JCPV	78	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	79	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	80	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
a1436a84	81
6d0f6bcf	82	#define CONFIG_SYS_LOAD_ADDR 0x00100000
a1436a84	83
6d0f6bcf JCPV	84	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	85	#define CONFIG_SYS_MEMTEST_END 0x380000
a1436a84	86
6d0f6bcf JCPV	87	#undef CONFIG_SYS_PLL_BYPASS /* bypass PLL for test purpose */
	88	#define CONFIG_SYS_FAST_CLK
	89	#ifdef CONFIG_SYS_FAST_CLK
	90	# define CONFIG_SYS_PLLCR 0x1243E054
	91	# define CONFIG_SYS_CLK 140000000
a1436a84	92	#else
6d0f6bcf JCPV	93	# define CONFIG_SYS_PLLCR 0x135a4140
6d0f6bcf JCPV	94	# define CONFIG_SYS_CLK 70000000
a1436a84 TL	95	#endif
	96
	97	/*
	98	* Low Level Configuration Settings
	99	* (address mappings, register initial values, etc.)
	100	* You should know what you are doing if you make changes here.
	101	*/
	102
6d0f6bcf JCPV	103	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
6d0f6bcf JCPV	104	#define CONFIG_SYS_MBAR2 0x80000000 /* Module Base Addrs 2 */
a1436a84 TL	105
	106	/*
	107	* Definitions for initial stack pointer and data area (in DPRAM)
	108	*/
6d0f6bcf	109	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	110	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
25ddd1fb	111	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	112	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
a1436a84 TL	113
	114	/*
	115	* Start addresses for the final memory configuration
	116	* (Set up by the startup code)
6d0f6bcf	117	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
a1436a84	118	*/
6d0f6bcf JCPV	119	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	120	#define CONFIG_SYS_SDRAM_SIZE 8 /* SDRAM size in MB */
a1436a84 TL	121
a1436a84 TL	122	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	123	#define CONFIG_SYS_MONITOR_BASE 0x20000
a1436a84	124	#else
6d0f6bcf	125	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
a1436a84 TL	126	#endif
a1436a84 TL	127
6d0f6bcf JCPV	128	#define CONFIG_SYS_MONITOR_LEN 0x40000
	129	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	130	#define CONFIG_SYS_BOOTPARAMS_LEN (64*1024)
a1436a84 TL	131
	132	/*
	133	* For booting Linux, the board info and command line data
	134	* have to be in the first 8 MB of memory, since this is
	135	* the maximum mapped by the Linux kernel during initialization ??
	136	*/
6d0f6bcf	137	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	138	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
a1436a84 TL	139
a1436a84 TL	140	/* FLASH organization */
012522fe	141	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
6d0f6bcf JCPV	142	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	143	#define CONFIG_SYS_MAX_FLASH_SECT 35 /* max number of sectors on one chip */
	144	#define CONFIG_SYS_FLASH_ERASE_TOUT 1000
a1436a84	145
6d0f6bcf	146	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	147	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	148	#define CONFIG_SYS_FLASH_SIZE 0x200000
6d0f6bcf JCPV	149	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
a1436a84 TL	150
a1436a84 TL	151	/* Cache Configuration */
6d0f6bcf	152	#define CONFIG_SYS_CACHELINE_SIZE 16
a1436a84	153
dd9f054e	154	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	155	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	156	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	157	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	158	#define CONFIG_SYS_ICACHE_INV (CF_CACR_DCM)
	159	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_FLASH_BASE \| \
	160	CF_ADDRMASK(2) \| \
	161	CF_ACR_EN \| CF_ACR_SM_ALL)
	162	#define CONFIG_SYS_CACHE_ACR1 (CONFIG_SYS_SDRAM_BASE \| \
	163	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	164	CF_ACR_EN \| CF_ACR_SM_ALL)
	165	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CEIB \| \
	166	CF_CACR_DBWE)
	167
a1436a84	168	/* Port configuration */
6d0f6bcf	169	#define CONFIG_SYS_FECI2C 0xF0
a1436a84	170
012522fe TL	171	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	172	#define CONFIG_SYS_CS0_MASK 0x001F0021
	173	#define CONFIG_SYS_CS0_CTRL 0x00001D80
a1436a84 TL	174
	175	/*-----------------------------------------------------------------------
	176	* Port configuration
	177	*/
6d0f6bcf JCPV	178	#define CONFIG_SYS_GPIO_FUNC 0x00000008 /* Set gpio pins: none */
	179	#define CONFIG_SYS_GPIO1_FUNC 0x00df00f0 /* 36-39(SWITCH),48-52(FPGAs),54 */
	180	#define CONFIG_SYS_GPIO_EN 0x00000008 /* Set gpio output enable */
	181	#define CONFIG_SYS_GPIO1_EN 0x00c70000 /* Set gpio output enable */
	182	#define CONFIG_SYS_GPIO_OUT 0x00000008 /* Set outputs to default state */
	183	#define CONFIG_SYS_GPIO1_OUT 0x00c70000 /* Set outputs to default state */
	184	#define CONFIG_SYS_GPIO1_LED 0x00400000 /* user led */
a1436a84 TL	185
a1436a84 TL	186	#endif /* _M5253EVB_H */