[people/ms/u-boot.git] / include / configs / M5272C3.h

/*
 * Configuation settings for the Motorola MC5272C3 board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5272C3_H
#define _M5272C3_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */

#undef CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#endif

#define LDS_BOARD_TEXT \
	. = DEFINED(env_offset) ? env_offset : .; \
	env/embedded.o(.text);

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		M5272C3
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
#endif

#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR		0x20000
#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000
#define CONFIG_SYS_CLK			66000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_SCR			0x0003
#define CONFIG_SYS_SPR			0xffff

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		4	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		0xffe00000

#ifdef	CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
#define CONFIG_SYS_BR1_PRELIM		0
#define CONFIG_SYS_OR1_PRELIM		0
#define CONFIG_SYS_BR2_PRELIM		0x30000001
#define CONFIG_SYS_OR2_PRELIM		0xFFF80000
#define CONFIG_SYS_BR3_PRELIM		0
#define CONFIG_SYS_OR3_PRELIM		0
#define CONFIG_SYS_BR4_PRELIM		0
#define CONFIG_SYS_OR4_PRELIM		0
#define CONFIG_SYS_BR5_PRELIM		0
#define CONFIG_SYS_OR5_PRELIM		0
#define CONFIG_SYS_BR6_PRELIM		0
#define CONFIG_SYS_OR6_PRELIM		0
#define CONFIG_SYS_BR7_PRELIM		0x00000701
#define CONFIG_SYS_OR7_PRELIM		0xFFC0007C

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_PACNT		0x00000000
#define CONFIG_SYS_PADDR		0x0000
#define CONFIG_SYS_PADAT		0x0000
#define CONFIG_SYS_PBCNT		0x55554155	/* Ethernet/UART configuration */
#define CONFIG_SYS_PBDDR		0x0000
#define CONFIG_SYS_PBDAT		0x0000
#define CONFIG_SYS_PDCNT		0x00000000
#endif				/* _M5272C3_H */
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* Configuation settings for the Motorola MC5272C3 board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
bf9e3b38	7	*/
4e5ca3eb	8
bf9e3b38 WD	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
	13	#ifndef _M5272C3_H
	14	#define _M5272C3_H
	15
	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
f28e1bd9	20	#define CONFIG_MCFTMR
4e5ca3eb	21
f28e1bd9	22	#define CONFIG_MCFUART
6d0f6bcf	23	#define CONFIG_SYS_UART_PORT (0)
bf9e3b38	24
f28e1bd9	25	#undef CONFIG_WATCHDOG
bf9e3b38 WD	26	#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
bf9e3b38 WD	27
f28e1bd9	28	#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
bf9e3b38 WD	29
	30	/* Configuration for environment
	31	* Environment is embedded in u-boot in the second sector of the flash
	32	*/
	33	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	34	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	35	#define CONFIG_ENV_SECT_SIZE 0x2000
bf9e3b38	36	#else
0e8d1586 JCPV	37	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	38	#define CONFIG_ENV_SECT_SIZE 0x2000
bf9e3b38 WD	39	#endif
bf9e3b38 WD	40
5296cb1d	41	#define LDS_BOARD_TEXT \
0649cd0d SG	42	. = DEFINED(env_offset) ? env_offset : .; \
0649cd0d SG	43	env/embedded.o(.text);
5296cb1d	44
659e2f67 JL	45	/*
	46	* BOOTP options
	47	*/
	48	#define CONFIG_BOOTP_BOOTFILESIZE
	49	#define CONFIG_BOOTP_BOOTPATH
	50	#define CONFIG_BOOTP_GATEWAY
	51	#define CONFIG_BOOTP_HOSTNAME
	52
8353e139 JL	53	/*
	54	* Command line configuration.
	55	*/
8353e139	56
f28e1bd9 TL	57	#define CONFIG_MCFFEC
f28e1bd9 TL	58	#ifdef CONFIG_MCFFEC
f28e1bd9	59	# define CONFIG_MII 1
d53cf6a9	60	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	61	# define CONFIG_SYS_DISCOVER_PHY
	62	# define CONFIG_SYS_RX_ETH_BUFFER 8
	63	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	64
6d0f6bcf JCPV	65	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	66	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	67	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	68	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	69	# ifndef CONFIG_SYS_DISCOVER_PHY
f28e1bd9 TL	70	# define FECDUPLEX FULL
	71	# define FECSPEED _100BASET
	72	# else
6d0f6bcf JCPV	73	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	74	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	75	# endif
6d0f6bcf	76	# endif /* CONFIG_SYS_DISCOVER_PHY */
f28e1bd9 TL	77	#endif
	78
	79	#ifdef CONFIG_MCFFEC
f28e1bd9 TL	80	# define CONFIG_IPADDR 192.162.1.2
	81	# define CONFIG_NETMASK 255.255.255.0
	82	# define CONFIG_SERVERIP 192.162.1.1
	83	# define CONFIG_GATEWAYIP 192.162.1.1
f28e1bd9 TL	84	#endif /* CONFIG_MCFFEC */
	85
	86	#define CONFIG_HOSTNAME M5272C3
	87	#define CONFIG_EXTRA_ENV_SETTINGS \
	88	"netdev=eth0\0" \
	89	"loadaddr=10000\0" \
	90	"u-boot=u-boot.bin\0" \
	91	"load=tftp ${loadaddr) ${u-boot}\0" \
	92	"upd=run load; run prog\0" \
	93	"prog=prot off ffe00000 ffe3ffff;" \
	94	"era ffe00000 ffe3ffff;" \
	95	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	96	"save\0" \
	97	""
bf9e3b38	98
6d0f6bcf	99	#define CONFIG_SYS_LONGHELP /* undef to save memory */
bf9e3b38	100
8353e139	101	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	102	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
bf9e3b38	103	#else
6d0f6bcf	104	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
bf9e3b38	105	#endif
bf9e3b38	106
6d0f6bcf JCPV	107	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	108	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	109	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	110	#define CONFIG_SYS_LOAD_ADDR 0x20000
	111	#define CONFIG_SYS_MEMTEST_START 0x400
	112	#define CONFIG_SYS_MEMTEST_END 0x380000
6d0f6bcf	113	#define CONFIG_SYS_CLK 66000000
bf9e3b38 WD	114
	115	/*
	116	* Low Level Configuration Settings
	117	* (address mappings, register initial values, etc.)
	118	* You should know what you are doing if you make changes here.
	119	*/
6d0f6bcf JCPV	120	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
	121	#define CONFIG_SYS_SCR 0x0003
	122	#define CONFIG_SYS_SPR 0xffff
bf9e3b38	123
bf9e3b38 WD	124	/*-----------------------------------------------------------------------
	125	* Definitions for initial stack pointer and data area (in DPRAM)
	126	*/
6d0f6bcf	127	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	128	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	129	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	130	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
bf9e3b38 WD	131
	132	/*-----------------------------------------------------------------------
	133	* Start addresses for the final memory configuration
	134	* (Set up by the startup code)
6d0f6bcf	135	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
bf9e3b38	136	*/
6d0f6bcf JCPV	137	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	138	#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
	139	#define CONFIG_SYS_FLASH_BASE 0xffe00000
bf9e3b38 WD	140
bf9e3b38 WD	141	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	142	#define CONFIG_SYS_MONITOR_BASE 0x20000
bf9e3b38	143	#else
6d0f6bcf	144	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
bf9e3b38 WD	145	#endif
bf9e3b38 WD	146
6d0f6bcf JCPV	147	#define CONFIG_SYS_MONITOR_LEN 0x20000
	148	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	149	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
bf9e3b38 WD	150
	151	/*
	152	* For booting Linux, the board info and command line data
	153	* have to be in the first 8 MB of memory, since this is
	154	* the maximum mapped by the Linux kernel during initialization ??
	155	*/
6d0f6bcf	156	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
bf9e3b38	157
b202816c	158	/*
bf9e3b38 WD	159	* FLASH organization
bf9e3b38 WD	160	*/
b202816c TL	161	#define CONFIG_SYS_FLASH_CFI
	162	#ifdef CONFIG_SYS_FLASH_CFI
	163	# define CONFIG_FLASH_CFI_DRIVER 1
	164	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
	165	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	166	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	167	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	168	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	169	#endif
bf9e3b38 WD	170
	171	/*-----------------------------------------------------------------------
	172	* Cache Configuration
	173	*/
6d0f6bcf	174	#define CONFIG_SYS_CACHELINE_SIZE 16
bf9e3b38	175
dd9f054e	176	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	177	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	178	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	179	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	180	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	181	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	182	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	183	CF_ACR_EN \| CF_ACR_SM_ALL)
	184	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	185	CF_CACR_DISD \| CF_CACR_INVI \| \
	186	CF_CACR_CEIB \| CF_CACR_DCM \| \
	187	CF_CACR_EUSP)
	188
bf9e3b38 WD	189	/*-----------------------------------------------------------------------
	190	* Memory bank definitions
	191	*/
6d0f6bcf JCPV	192	#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
	193	#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
	194	#define CONFIG_SYS_BR1_PRELIM 0
	195	#define CONFIG_SYS_OR1_PRELIM 0
	196	#define CONFIG_SYS_BR2_PRELIM 0x30000001
	197	#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
	198	#define CONFIG_SYS_BR3_PRELIM 0
	199	#define CONFIG_SYS_OR3_PRELIM 0
	200	#define CONFIG_SYS_BR4_PRELIM 0
	201	#define CONFIG_SYS_OR4_PRELIM 0
	202	#define CONFIG_SYS_BR5_PRELIM 0
	203	#define CONFIG_SYS_OR5_PRELIM 0
	204	#define CONFIG_SYS_BR6_PRELIM 0
	205	#define CONFIG_SYS_OR6_PRELIM 0
	206	#define CONFIG_SYS_BR7_PRELIM 0x00000701
	207	#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
bf9e3b38 WD	208
	209	/*-----------------------------------------------------------------------
	210	* Port configuration
	211	*/
6d0f6bcf JCPV	212	#define CONFIG_SYS_PACNT 0x00000000
	213	#define CONFIG_SYS_PADDR 0x0000
	214	#define CONFIG_SYS_PADAT 0x0000
	215	#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
	216	#define CONFIG_SYS_PBDDR 0x0000
	217	#define CONFIG_SYS_PBDAT 0x0000
	218	#define CONFIG_SYS_PDCNT 0x00000000
f28e1bd9	219	#endif /* _M5272C3_H */