[people/ms/u-boot.git] / include / configs / M5272C3.h

/*
 * Configuation settings for the Motorola MC5272C3 board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5272C3_H
#define _M5272C3_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT 10000	/* timeout in milliseconds */

#undef CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#ifndef CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#else
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1
#endif

#define LDS_BOARD_TEXT \
        . = DEFINED(env_offset) ? env_offset : .; \
        common/env_embedded.o (.text);

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */

#define CONFIG_BOOTDELAY	5
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		M5272C3
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
#else
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
#endif

#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR		0x20000
#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000
#define CONFIG_SYS_CLK			66000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define CONFIG_SYS_MBAR		0x10000000	/* Register Base Addrs */
#define CONFIG_SYS_SCR			0x0003
#define CONFIG_SYS_SPR			0xffff

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM    */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_SIZE		4	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		0xffe00000

#ifdef	CONFIG_MONITOR_IS_IN_RAM
#define CONFIG_SYS_MONITOR_BASE	0x20000
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
					 CF_CACR_DISD | CF_CACR_INVI | \
					 CF_CACR_CEIB | CF_CACR_DCM | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
#define CONFIG_SYS_BR0_PRELIM		0xFFE00201
#define CONFIG_SYS_OR0_PRELIM		0xFFE00014
#define CONFIG_SYS_BR1_PRELIM		0
#define CONFIG_SYS_OR1_PRELIM		0
#define CONFIG_SYS_BR2_PRELIM		0x30000001
#define CONFIG_SYS_OR2_PRELIM		0xFFF80000
#define CONFIG_SYS_BR3_PRELIM		0
#define CONFIG_SYS_OR3_PRELIM		0
#define CONFIG_SYS_BR4_PRELIM		0
#define CONFIG_SYS_OR4_PRELIM		0
#define CONFIG_SYS_BR5_PRELIM		0
#define CONFIG_SYS_OR5_PRELIM		0
#define CONFIG_SYS_BR6_PRELIM		0
#define CONFIG_SYS_OR6_PRELIM		0
#define CONFIG_SYS_BR7_PRELIM		0x00000701
#define CONFIG_SYS_OR7_PRELIM		0xFFC0007C

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_PACNT		0x00000000
#define CONFIG_SYS_PADDR		0x0000
#define CONFIG_SYS_PADAT		0x0000
#define CONFIG_SYS_PBCNT		0x55554155	/* Ethernet/UART configuration */
#define CONFIG_SYS_PBDDR		0x0000
#define CONFIG_SYS_PBDAT		0x0000
#define CONFIG_SYS_PDCNT		0x00000000
#endif				/* _M5272C3_H */
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* Configuation settings for the Motorola MC5272C3 board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
bf9e3b38	7	*/
4e5ca3eb	8
bf9e3b38 WD	9	/*
	10	* board/config.h - configuration options, board specific
	11	*/
	12
	13	#ifndef _M5272C3_H
	14	#define _M5272C3_H
	15
	16	/*
	17	* High Level Configuration Options
	18	* (easy to change)
	19	*/
f28e1bd9	20	#define CONFIG_MCFTMR
4e5ca3eb	21
f28e1bd9	22	#define CONFIG_MCFUART
6d0f6bcf	23	#define CONFIG_SYS_UART_PORT (0)
79e0799c	24	#define CONFIG_BAUDRATE 115200
bf9e3b38	25
f28e1bd9	26	#undef CONFIG_WATCHDOG
bf9e3b38 WD	27	#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
bf9e3b38 WD	28
f28e1bd9	29	#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
bf9e3b38 WD	30
	31	/* Configuration for environment
	32	* Environment is embedded in u-boot in the second sector of the flash
	33	*/
	34	#ifndef CONFIG_MONITOR_IS_IN_RAM
0e8d1586 JCPV	35	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	36	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	37	#define CONFIG_ENV_IS_IN_FLASH 1
bf9e3b38	38	#else
0e8d1586 JCPV	39	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	40	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	41	#define CONFIG_ENV_IS_IN_FLASH 1
bf9e3b38 WD	42	#endif
bf9e3b38 WD	43
5296cb1d	44	#define LDS_BOARD_TEXT \
	45	. = DEFINED(env_offset) ? env_offset : .; \
	46	common/env_embedded.o (.text);
	47
659e2f67 JL	48	/*
	49	* BOOTP options
	50	*/
	51	#define CONFIG_BOOTP_BOOTFILESIZE
	52	#define CONFIG_BOOTP_BOOTPATH
	53	#define CONFIG_BOOTP_GATEWAY
	54	#define CONFIG_BOOTP_HOSTNAME
	55
8353e139 JL	56	/*
	57	* Command line configuration.
	58	*/
8353e139	59
bf9e3b38	60	#define CONFIG_BOOTDELAY 5
f28e1bd9 TL	61	#define CONFIG_MCFFEC
f28e1bd9 TL	62	#ifdef CONFIG_MCFFEC
f28e1bd9	63	# define CONFIG_MII 1
d53cf6a9	64	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	65	# define CONFIG_SYS_DISCOVER_PHY
	66	# define CONFIG_SYS_RX_ETH_BUFFER 8
	67	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	68
6d0f6bcf JCPV	69	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	70	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	71	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	72	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	73	# ifndef CONFIG_SYS_DISCOVER_PHY
f28e1bd9 TL	74	# define FECDUPLEX FULL
	75	# define FECSPEED _100BASET
	76	# else
6d0f6bcf JCPV	77	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	78	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	79	# endif
6d0f6bcf	80	# endif /* CONFIG_SYS_DISCOVER_PHY */
f28e1bd9 TL	81	#endif
	82
	83	#ifdef CONFIG_MCFFEC
f28e1bd9 TL	84	# define CONFIG_IPADDR 192.162.1.2
	85	# define CONFIG_NETMASK 255.255.255.0
	86	# define CONFIG_SERVERIP 192.162.1.1
	87	# define CONFIG_GATEWAYIP 192.162.1.1
f28e1bd9 TL	88	#endif /* CONFIG_MCFFEC */
	89
	90	#define CONFIG_HOSTNAME M5272C3
	91	#define CONFIG_EXTRA_ENV_SETTINGS \
	92	"netdev=eth0\0" \
	93	"loadaddr=10000\0" \
	94	"u-boot=u-boot.bin\0" \
	95	"load=tftp ${loadaddr) ${u-boot}\0" \
	96	"upd=run load; run prog\0" \
	97	"prog=prot off ffe00000 ffe3ffff;" \
	98	"era ffe00000 ffe3ffff;" \
	99	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	100	"save\0" \
	101	""
bf9e3b38	102
6d0f6bcf	103	#define CONFIG_SYS_LONGHELP /* undef to save memory */
bf9e3b38	104
8353e139	105	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	106	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
bf9e3b38	107	#else
6d0f6bcf	108	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
bf9e3b38	109	#endif
bf9e3b38	110
6d0f6bcf JCPV	111	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	112	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	113	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	114	#define CONFIG_SYS_LOAD_ADDR 0x20000
	115	#define CONFIG_SYS_MEMTEST_START 0x400
	116	#define CONFIG_SYS_MEMTEST_END 0x380000
6d0f6bcf	117	#define CONFIG_SYS_CLK 66000000
bf9e3b38 WD	118
	119	/*
	120	* Low Level Configuration Settings
	121	* (address mappings, register initial values, etc.)
	122	* You should know what you are doing if you make changes here.
	123	*/
6d0f6bcf JCPV	124	#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
	125	#define CONFIG_SYS_SCR 0x0003
	126	#define CONFIG_SYS_SPR 0xffff
bf9e3b38	127
bf9e3b38 WD	128	/*-----------------------------------------------------------------------
	129	* Definitions for initial stack pointer and data area (in DPRAM)
	130	*/
6d0f6bcf	131	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982	132	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb	133	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	134	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
bf9e3b38 WD	135
	136	/*-----------------------------------------------------------------------
	137	* Start addresses for the final memory configuration
	138	* (Set up by the startup code)
6d0f6bcf	139	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
bf9e3b38	140	*/
6d0f6bcf JCPV	141	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	142	#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
	143	#define CONFIG_SYS_FLASH_BASE 0xffe00000
bf9e3b38 WD	144
bf9e3b38 WD	145	#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf	146	#define CONFIG_SYS_MONITOR_BASE 0x20000
bf9e3b38	147	#else
6d0f6bcf	148	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
bf9e3b38 WD	149	#endif
bf9e3b38 WD	150
6d0f6bcf JCPV	151	#define CONFIG_SYS_MONITOR_LEN 0x20000
	152	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	153	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
bf9e3b38 WD	154
	155	/*
	156	* For booting Linux, the board info and command line data
	157	* have to be in the first 8 MB of memory, since this is
	158	* the maximum mapped by the Linux kernel during initialization ??
	159	*/
6d0f6bcf	160	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
bf9e3b38	161
b202816c	162	/*
bf9e3b38 WD	163	* FLASH organization
bf9e3b38 WD	164	*/
b202816c TL	165	#define CONFIG_SYS_FLASH_CFI
	166	#ifdef CONFIG_SYS_FLASH_CFI
	167	# define CONFIG_FLASH_CFI_DRIVER 1
	168	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
	169	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	170	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	171	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	172	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	173	#endif
bf9e3b38 WD	174
	175	/*-----------------------------------------------------------------------
	176	* Cache Configuration
	177	*/
6d0f6bcf	178	#define CONFIG_SYS_CACHELINE_SIZE 16
bf9e3b38	179
dd9f054e	180	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	181	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	182	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	183	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	184	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV \| CF_CACR_INVI)
	185	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	186	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	187	CF_ACR_EN \| CF_ACR_SM_ALL)
	188	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_CINV \| \
	189	CF_CACR_DISD \| CF_CACR_INVI \| \
	190	CF_CACR_CEIB \| CF_CACR_DCM \| \
	191	CF_CACR_EUSP)
	192
bf9e3b38 WD	193	/*-----------------------------------------------------------------------
	194	* Memory bank definitions
	195	*/
6d0f6bcf JCPV	196	#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
	197	#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
	198	#define CONFIG_SYS_BR1_PRELIM 0
	199	#define CONFIG_SYS_OR1_PRELIM 0
	200	#define CONFIG_SYS_BR2_PRELIM 0x30000001
	201	#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
	202	#define CONFIG_SYS_BR3_PRELIM 0
	203	#define CONFIG_SYS_OR3_PRELIM 0
	204	#define CONFIG_SYS_BR4_PRELIM 0
	205	#define CONFIG_SYS_OR4_PRELIM 0
	206	#define CONFIG_SYS_BR5_PRELIM 0
	207	#define CONFIG_SYS_OR5_PRELIM 0
	208	#define CONFIG_SYS_BR6_PRELIM 0
	209	#define CONFIG_SYS_OR6_PRELIM 0
	210	#define CONFIG_SYS_BR7_PRELIM 0x00000701
	211	#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
bf9e3b38 WD	212
	213	/*-----------------------------------------------------------------------
	214	* Port configuration
	215	*/
6d0f6bcf JCPV	216	#define CONFIG_SYS_PACNT 0x00000000
	217	#define CONFIG_SYS_PADDR 0x0000
	218	#define CONFIG_SYS_PADAT 0x0000
	219	#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
	220	#define CONFIG_SYS_PBDDR 0x0000
	221	#define CONFIG_SYS_PBDAT 0x0000
	222	#define CONFIG_SYS_PDCNT 0x00000000
f28e1bd9	223	#endif /* _M5272C3_H */