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1/*
2 * Configuation settings for the Motorola MC5272C3 board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
3765b3e7 6 * SPDX-License-Identifier: GPL-2.0+
bf9e3b38 7 */
4e5ca3eb 8
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9/*
10 * board/config.h - configuration options, board specific
11 */
12
13#ifndef _M5272C3_H
14#define _M5272C3_H
15
16/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
f28e1bd9 20#define CONFIG_MCFTMR
4e5ca3eb 21
f28e1bd9 22#define CONFIG_MCFUART
6d0f6bcf 23#define CONFIG_SYS_UART_PORT (0)
79e0799c 24#define CONFIG_BAUDRATE 115200
bf9e3b38 25
f28e1bd9 26#undef CONFIG_WATCHDOG
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27#define CONFIG_WATCHDOG_TIMEOUT 10000 /* timeout in milliseconds */
28
f28e1bd9 29#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
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30
31/* Configuration for environment
32 * Environment is embedded in u-boot in the second sector of the flash
33 */
34#ifndef CONFIG_MONITOR_IS_IN_RAM
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35#define CONFIG_ENV_OFFSET 0x4000
36#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0 37#define CONFIG_ENV_IS_IN_FLASH 1
bf9e3b38 38#else
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39#define CONFIG_ENV_ADDR 0xffe04000
40#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0 41#define CONFIG_ENV_IS_IN_FLASH 1
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42#endif
43
5296cb1d 44#define LDS_BOARD_TEXT \
45 . = DEFINED(env_offset) ? env_offset : .; \
46 common/env_embedded.o (.text);
47
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48/*
49 * BOOTP options
50 */
51#define CONFIG_BOOTP_BOOTFILESIZE
52#define CONFIG_BOOTP_BOOTPATH
53#define CONFIG_BOOTP_GATEWAY
54#define CONFIG_BOOTP_HOSTNAME
55
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56/*
57 * Command line configuration.
58 */
dd9f054e 59#define CONFIG_CMD_CACHE
8353e139 60#define CONFIG_CMD_MII
f28e1bd9 61#define CONFIG_CMD_PING
8353e139 62
8353e139 63
bf9e3b38 64#define CONFIG_BOOTDELAY 5
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65#define CONFIG_MCFFEC
66#ifdef CONFIG_MCFFEC
f28e1bd9 67# define CONFIG_MII 1
d53cf6a9 68# define CONFIG_MII_INIT 1
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69# define CONFIG_SYS_DISCOVER_PHY
70# define CONFIG_SYS_RX_ETH_BUFFER 8
71# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9 72
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73# define CONFIG_SYS_FEC0_PINMUX 0
74# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1 75# define MCFFEC_TOUT_LOOP 50000
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76/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
77# ifndef CONFIG_SYS_DISCOVER_PHY
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78# define FECDUPLEX FULL
79# define FECSPEED _100BASET
80# else
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81# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
82# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9 83# endif
6d0f6bcf 84# endif /* CONFIG_SYS_DISCOVER_PHY */
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85#endif
86
87#ifdef CONFIG_MCFFEC
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88# define CONFIG_IPADDR 192.162.1.2
89# define CONFIG_NETMASK 255.255.255.0
90# define CONFIG_SERVERIP 192.162.1.1
91# define CONFIG_GATEWAYIP 192.162.1.1
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92#endif /* CONFIG_MCFFEC */
93
94#define CONFIG_HOSTNAME M5272C3
95#define CONFIG_EXTRA_ENV_SETTINGS \
96 "netdev=eth0\0" \
97 "loadaddr=10000\0" \
98 "u-boot=u-boot.bin\0" \
99 "load=tftp ${loadaddr) ${u-boot}\0" \
100 "upd=run load; run prog\0" \
101 "prog=prot off ffe00000 ffe3ffff;" \
102 "era ffe00000 ffe3ffff;" \
103 "cp.b ${loadaddr} ffe00000 ${filesize};"\
104 "save\0" \
105 ""
bf9e3b38 106
6d0f6bcf 107#define CONFIG_SYS_LONGHELP /* undef to save memory */
bf9e3b38 108
8353e139 109#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 110#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
bf9e3b38 111#else
6d0f6bcf 112#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
bf9e3b38 113#endif
bf9e3b38 114
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115#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
116#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
117#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
118#define CONFIG_SYS_LOAD_ADDR 0x20000
119#define CONFIG_SYS_MEMTEST_START 0x400
120#define CONFIG_SYS_MEMTEST_END 0x380000
6d0f6bcf 121#define CONFIG_SYS_CLK 66000000
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122
123/*
124 * Low Level Configuration Settings
125 * (address mappings, register initial values, etc.)
126 * You should know what you are doing if you make changes here.
127 */
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128#define CONFIG_SYS_MBAR 0x10000000 /* Register Base Addrs */
129#define CONFIG_SYS_SCR 0x0003
130#define CONFIG_SYS_SPR 0xffff
bf9e3b38 131
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132/*-----------------------------------------------------------------------
133 * Definitions for initial stack pointer and data area (in DPRAM)
134 */
6d0f6bcf 135#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
553f0982 136#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
25ddd1fb 137#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 138#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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139
140/*-----------------------------------------------------------------------
141 * Start addresses for the final memory configuration
142 * (Set up by the startup code)
6d0f6bcf 143 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
bf9e3b38 144 */
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145#define CONFIG_SYS_SDRAM_BASE 0x00000000
146#define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */
147#define CONFIG_SYS_FLASH_BASE 0xffe00000
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148
149#ifdef CONFIG_MONITOR_IS_IN_RAM
6d0f6bcf 150#define CONFIG_SYS_MONITOR_BASE 0x20000
bf9e3b38 151#else
6d0f6bcf 152#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
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153#endif
154
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155#define CONFIG_SYS_MONITOR_LEN 0x20000
156#define CONFIG_SYS_MALLOC_LEN (256 << 10)
157#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
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158
159/*
160 * For booting Linux, the board info and command line data
161 * have to be in the first 8 MB of memory, since this is
162 * the maximum mapped by the Linux kernel during initialization ??
163 */
6d0f6bcf 164#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
bf9e3b38 165
b202816c 166/*
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167 * FLASH organization
168 */
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169#define CONFIG_SYS_FLASH_CFI
170#ifdef CONFIG_SYS_FLASH_CFI
171# define CONFIG_FLASH_CFI_DRIVER 1
172# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
173# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
174# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
175# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
176# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
177#endif
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178
179/*-----------------------------------------------------------------------
180 * Cache Configuration
181 */
6d0f6bcf 182#define CONFIG_SYS_CACHELINE_SIZE 16
bf9e3b38 183
dd9f054e 184#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982 185 CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e 186#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982 187 CONFIG_SYS_INIT_RAM_SIZE - 4)
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188#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI)
189#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
190 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
191 CF_ACR_EN | CF_ACR_SM_ALL)
192#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \
193 CF_CACR_DISD | CF_CACR_INVI | \
194 CF_CACR_CEIB | CF_CACR_DCM | \
195 CF_CACR_EUSP)
196
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197/*-----------------------------------------------------------------------
198 * Memory bank definitions
199 */
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200#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
201#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
202#define CONFIG_SYS_BR1_PRELIM 0
203#define CONFIG_SYS_OR1_PRELIM 0
204#define CONFIG_SYS_BR2_PRELIM 0x30000001
205#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
206#define CONFIG_SYS_BR3_PRELIM 0
207#define CONFIG_SYS_OR3_PRELIM 0
208#define CONFIG_SYS_BR4_PRELIM 0
209#define CONFIG_SYS_OR4_PRELIM 0
210#define CONFIG_SYS_BR5_PRELIM 0
211#define CONFIG_SYS_OR5_PRELIM 0
212#define CONFIG_SYS_BR6_PRELIM 0
213#define CONFIG_SYS_OR6_PRELIM 0
214#define CONFIG_SYS_BR7_PRELIM 0x00000701
215#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
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216
217/*-----------------------------------------------------------------------
218 * Port configuration
219 */
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220#define CONFIG_SYS_PACNT 0x00000000
221#define CONFIG_SYS_PADDR 0x0000
222#define CONFIG_SYS_PADAT 0x0000
223#define CONFIG_SYS_PBCNT 0x55554155 /* Ethernet/UART configuration */
224#define CONFIG_SYS_PBDDR 0x0000
225#define CONFIG_SYS_PBDAT 0x0000
226#define CONFIG_SYS_PDCNT 0x00000000
f28e1bd9 227#endif /* _M5272C3_H */