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545c8e0a MF |
1 | /* |
2 | * Configuation settings for the Motorola MC5275EVB board. | |
3 | * | |
4 | * By Arthur Shipkowski <art@videon-central.com> | |
5 | * Copyright (C) 2005 Videon Central, Inc. | |
6 | * | |
7 | * Based off of M5272C3 board code by Josef Baumgartner | |
8 | * <josef.baumgartner@telex.de> | |
9 | * | |
3765b3e7 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
545c8e0a MF |
11 | */ |
12 | ||
13 | /* | |
14 | * board/config.h - configuration options, board specific | |
15 | */ | |
16 | ||
17 | #ifndef _M5275EVB_H | |
18 | #define _M5275EVB_H | |
19 | ||
20 | /* | |
21 | * High Level Configuration Options | |
22 | * (easy to change) | |
23 | */ | |
545c8e0a MF |
24 | |
25 | #define CONFIG_MCFTMR | |
26 | ||
27 | #define CONFIG_MCFUART | |
6d0f6bcf | 28 | #define CONFIG_SYS_UART_PORT (0) |
545c8e0a MF |
29 | |
30 | /* Configuration for environment | |
31 | * Environment is embedded in u-boot in the second sector of the flash | |
32 | */ | |
33 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
34 | #define CONFIG_ENV_OFFSET 0x4000 |
35 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
545c8e0a | 36 | #else |
0e8d1586 JCPV |
37 | #define CONFIG_ENV_ADDR 0xffe04000 |
38 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
545c8e0a MF |
39 | #endif |
40 | ||
5296cb1d | 41 | #define LDS_BOARD_TEXT \ |
0649cd0d SG |
42 | . = DEFINED(env_offset) ? env_offset : .; \ |
43 | env/embedded.o(.text); | |
5296cb1d | 44 | |
545c8e0a MF |
45 | /* |
46 | * BOOTP options | |
47 | */ | |
48 | #define CONFIG_BOOTP_BOOTFILESIZE | |
545c8e0a MF |
49 | |
50 | /* Available command configuration */ | |
545c8e0a | 51 | |
545c8e0a MF |
52 | #define CONFIG_MCFFEC |
53 | #ifdef CONFIG_MCFFEC | |
545c8e0a | 54 | #define CONFIG_MII 1 |
0f3ba7e9 | 55 | #define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
56 | #define CONFIG_SYS_DISCOVER_PHY |
57 | #define CONFIG_SYS_RX_ETH_BUFFER 8 | |
58 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
59 | #define CONFIG_SYS_FEC0_PINMUX 0 | |
60 | #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
61 | #define CONFIG_SYS_FEC1_PINMUX 0 | |
62 | #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE | |
545c8e0a MF |
63 | #define MCFFEC_TOUT_LOOP 50000 |
64 | #define CONFIG_HAS_ETH1 | |
6d0f6bcf JCPV |
65 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
66 | #ifndef CONFIG_SYS_DISCOVER_PHY | |
545c8e0a MF |
67 | #define FECDUPLEX FULL |
68 | #define FECSPEED _100BASET | |
69 | #else | |
6d0f6bcf JCPV |
70 | #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
71 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
545c8e0a MF |
72 | #endif |
73 | #endif | |
74 | #endif | |
75 | ||
76 | /* I2C */ | |
00f792e0 HS |
77 | #define CONFIG_SYS_I2C |
78 | #define CONFIG_SYS_I2C_FSL | |
79 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
80 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
81 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 | |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
83 | #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) | |
84 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) | |
85 | #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) | |
545c8e0a | 86 | |
6d0f6bcf | 87 | #define CONFIG_SYS_LOAD_ADDR 0x800000 |
545c8e0a | 88 | |
545c8e0a | 89 | #define CONFIG_BOOTCOMMAND "bootm ffe40000" |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_MEMTEST_START 0x400 |
91 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
545c8e0a | 92 | |
0e8a7555 TL |
93 | #ifdef CONFIG_MCFFEC |
94 | # define CONFIG_NET_RETRY_COUNT 5 | |
95 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
96 | #endif /* FEC_ENET */ | |
97 | ||
98 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
99 | "netdev=eth0\0" \ | |
100 | "loadaddr=10000\0" \ | |
101 | "uboot=u-boot.bin\0" \ | |
102 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
103 | "upd=run load; run prog\0" \ | |
104 | "prog=prot off ffe00000 ffe3ffff;" \ | |
105 | "era ffe00000 ffe3ffff;" \ | |
106 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
107 | "save\0" \ | |
108 | "" | |
109 | ||
6d0f6bcf | 110 | #define CONFIG_SYS_CLK 150000000 |
545c8e0a MF |
111 | |
112 | /* | |
113 | * Low Level Configuration Settings | |
114 | * (address mappings, register initial values, etc.) | |
115 | * You should know what you are doing if you make changes here. | |
116 | */ | |
117 | ||
6d0f6bcf | 118 | #define CONFIG_SYS_MBAR 0x40000000 |
545c8e0a MF |
119 | |
120 | /*----------------------------------------------------------------------- | |
121 | * Definitions for initial stack pointer and data area (in DPRAM) | |
122 | */ | |
6d0f6bcf | 123 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 124 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 125 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 126 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
545c8e0a MF |
127 | |
128 | /*----------------------------------------------------------------------- | |
129 | * Start addresses for the final memory configuration | |
130 | * (Set up by the startup code) | |
6d0f6bcf | 131 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
545c8e0a | 132 | */ |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
134 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 135 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
545c8e0a MF |
136 | |
137 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 138 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
545c8e0a | 139 | #else |
6d0f6bcf | 140 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
545c8e0a MF |
141 | #endif |
142 | ||
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
144 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
145 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
545c8e0a MF |
146 | |
147 | /* | |
148 | * For booting Linux, the board info and command line data | |
149 | * have to be in the first 8 MB of memory, since this is | |
150 | * the maximum mapped by the Linux kernel during initialization ?? | |
151 | */ | |
d6e4baf4 TL |
152 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
153 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) | |
545c8e0a MF |
154 | |
155 | /*----------------------------------------------------------------------- | |
156 | * FLASH organization | |
157 | */ | |
6d0f6bcf JCPV |
158 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
159 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ | |
160 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
545c8e0a | 161 | |
6d0f6bcf | 162 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 163 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 164 | #define CONFIG_SYS_FLASH_SIZE 0x200000 |
545c8e0a MF |
165 | |
166 | /*----------------------------------------------------------------------- | |
167 | * Cache Configuration | |
168 | */ | |
6d0f6bcf | 169 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
545c8e0a | 170 | |
dd9f054e | 171 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 172 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 173 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 174 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
175 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
176 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
177 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
178 | CF_ACR_EN | CF_ACR_SM_ALL) | |
179 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
180 | CF_CACR_DISD | CF_CACR_INVI | \ | |
181 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
182 | CF_CACR_EUSP) | |
183 | ||
545c8e0a MF |
184 | /*----------------------------------------------------------------------- |
185 | * Memory bank definitions | |
186 | */ | |
012522fe TL |
187 | #define CONFIG_SYS_CS0_BASE 0xffe00000 |
188 | #define CONFIG_SYS_CS0_CTRL 0x00001980 | |
189 | #define CONFIG_SYS_CS0_MASK 0x001F0001 | |
545c8e0a | 190 | |
012522fe TL |
191 | #define CONFIG_SYS_CS1_BASE 0x30000000 |
192 | #define CONFIG_SYS_CS1_CTRL 0x00001900 | |
193 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
545c8e0a MF |
194 | |
195 | /*----------------------------------------------------------------------- | |
196 | * Port configuration | |
197 | */ | |
6d0f6bcf | 198 | #define CONFIG_SYS_FECI2C 0x0FA0 |
545c8e0a MF |
199 | |
200 | #endif /* _M5275EVB_H */ |