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545c8e0a MF |
1 | /* |
2 | * Configuation settings for the Motorola MC5275EVB board. | |
3 | * | |
4 | * By Arthur Shipkowski <art@videon-central.com> | |
5 | * Copyright (C) 2005 Videon Central, Inc. | |
6 | * | |
7 | * Based off of M5272C3 board code by Josef Baumgartner | |
8 | * <josef.baumgartner@telex.de> | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
545c8e0a MF |
11 | */ |
12 | ||
13 | /* | |
14 | * board/config.h - configuration options, board specific | |
15 | */ | |
16 | ||
17 | #ifndef _M5275EVB_H | |
18 | #define _M5275EVB_H | |
19 | ||
20 | /* | |
21 | * High Level Configuration Options | |
22 | * (easy to change) | |
23 | */ | |
24 | #define CONFIG_MCF52x2 /* define processor family */ | |
25 | #define CONFIG_M5275 /* define processor type */ | |
26 | #define CONFIG_M5275EVB /* define board type */ | |
27 | ||
28 | #define CONFIG_MCFTMR | |
29 | ||
30 | #define CONFIG_MCFUART | |
6d0f6bcf | 31 | #define CONFIG_SYS_UART_PORT (0) |
79e0799c | 32 | #define CONFIG_BAUDRATE 115200 |
545c8e0a MF |
33 | |
34 | /* Configuration for environment | |
35 | * Environment is embedded in u-boot in the second sector of the flash | |
36 | */ | |
37 | #ifndef CONFIG_MONITOR_IS_IN_RAM | |
0e8d1586 JCPV |
38 | #define CONFIG_ENV_OFFSET 0x4000 |
39 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 40 | #define CONFIG_ENV_IS_IN_FLASH 1 |
545c8e0a | 41 | #else |
0e8d1586 JCPV |
42 | #define CONFIG_ENV_ADDR 0xffe04000 |
43 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
5a1aceb0 | 44 | #define CONFIG_ENV_IS_IN_FLASH 1 |
545c8e0a MF |
45 | #endif |
46 | ||
47 | /* | |
48 | * BOOTP options | |
49 | */ | |
50 | #define CONFIG_BOOTP_BOOTFILESIZE | |
51 | #define CONFIG_BOOTP_BOOTPATH | |
52 | #define CONFIG_BOOTP_GATEWAY | |
53 | #define CONFIG_BOOTP_HOSTNAME | |
54 | ||
55 | /* Available command configuration */ | |
56 | #include <config_cmd_default.h> | |
57 | ||
dd9f054e | 58 | #define CONFIG_CMD_CACHE |
545c8e0a MF |
59 | #define CONFIG_CMD_PING |
60 | #define CONFIG_CMD_MII | |
61 | #define CONFIG_CMD_NET | |
62 | #define CONFIG_CMD_ELF | |
63 | #define CONFIG_CMD_FLASH | |
64 | #define CONFIG_CMD_I2C | |
65 | #define CONFIG_CMD_MEMORY | |
66 | #define CONFIG_CMD_DHCP | |
67 | ||
68 | #undef CONFIG_CMD_LOADS | |
69 | #undef CONFIG_CMD_LOADB | |
70 | ||
71 | #define CONFIG_MCFFEC | |
72 | #ifdef CONFIG_MCFFEC | |
545c8e0a | 73 | #define CONFIG_MII 1 |
0f3ba7e9 | 74 | #define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
75 | #define CONFIG_SYS_DISCOVER_PHY |
76 | #define CONFIG_SYS_RX_ETH_BUFFER 8 | |
77 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
78 | #define CONFIG_SYS_FEC0_PINMUX 0 | |
79 | #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
80 | #define CONFIG_SYS_FEC1_PINMUX 0 | |
81 | #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC1_IOBASE | |
545c8e0a MF |
82 | #define MCFFEC_TOUT_LOOP 50000 |
83 | #define CONFIG_HAS_ETH1 | |
6d0f6bcf JCPV |
84 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
85 | #ifndef CONFIG_SYS_DISCOVER_PHY | |
545c8e0a MF |
86 | #define FECDUPLEX FULL |
87 | #define FECSPEED _100BASET | |
88 | #else | |
6d0f6bcf JCPV |
89 | #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
90 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
545c8e0a MF |
91 | #endif |
92 | #endif | |
93 | #endif | |
94 | ||
95 | /* I2C */ | |
96 | #define CONFIG_FSL_I2C | |
97 | #define CONFIG_HARD_I2C /* I2C with hw support */ | |
98 | #undef CONFIG_SOFT_I2C | |
6d0f6bcf JCPV |
99 | #define CONFIG_SYS_I2C_SPEED 80000 |
100 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
101 | #define CONFIG_SYS_I2C_OFFSET 0x00000300 | |
102 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR | |
103 | #define CONFIG_SYS_I2C_PINMUX_REG (gpio_reg->par_feci2c) | |
104 | #define CONFIG_SYS_I2C_PINMUX_CLR (0xFFF0) | |
105 | #define CONFIG_SYS_I2C_PINMUX_SET (0x000F) | |
545c8e0a | 106 | |
6d0f6bcf JCPV |
107 | #define CONFIG_SYS_PROMPT "-> " |
108 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
545c8e0a MF |
109 | |
110 | #if (CONFIG_CMD_KGDB) | |
6d0f6bcf | 111 | # define CONFIG_SYS_CBSIZE 1024 |
545c8e0a | 112 | #else |
6d0f6bcf | 113 | # define CONFIG_SYS_CBSIZE 256 |
545c8e0a | 114 | #endif |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
116 | #define CONFIG_SYS_MAXARGS 16 | |
117 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
545c8e0a | 118 | |
6d0f6bcf | 119 | #define CONFIG_SYS_LOAD_ADDR 0x800000 |
545c8e0a MF |
120 | |
121 | #define CONFIG_BOOTDELAY 5 | |
122 | #define CONFIG_BOOTCOMMAND "bootm ffe40000" | |
6d0f6bcf JCPV |
123 | #define CONFIG_SYS_MEMTEST_START 0x400 |
124 | #define CONFIG_SYS_MEMTEST_END 0x380000 | |
545c8e0a | 125 | |
0e8a7555 TL |
126 | #ifdef CONFIG_MCFFEC |
127 | # define CONFIG_NET_RETRY_COUNT 5 | |
128 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
129 | #endif /* FEC_ENET */ | |
130 | ||
131 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
132 | "netdev=eth0\0" \ | |
133 | "loadaddr=10000\0" \ | |
134 | "uboot=u-boot.bin\0" \ | |
135 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
136 | "upd=run load; run prog\0" \ | |
137 | "prog=prot off ffe00000 ffe3ffff;" \ | |
138 | "era ffe00000 ffe3ffff;" \ | |
139 | "cp.b ${loadaddr} ffe00000 ${filesize};"\ | |
140 | "save\0" \ | |
141 | "" | |
142 | ||
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_HZ 1000 |
144 | #define CONFIG_SYS_CLK 150000000 | |
545c8e0a MF |
145 | |
146 | /* | |
147 | * Low Level Configuration Settings | |
148 | * (address mappings, register initial values, etc.) | |
149 | * You should know what you are doing if you make changes here. | |
150 | */ | |
151 | ||
6d0f6bcf | 152 | #define CONFIG_SYS_MBAR 0x40000000 |
545c8e0a MF |
153 | |
154 | /*----------------------------------------------------------------------- | |
155 | * Definitions for initial stack pointer and data area (in DPRAM) | |
156 | */ | |
6d0f6bcf | 157 | #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 |
553f0982 | 158 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ |
25ddd1fb | 159 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 160 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
545c8e0a MF |
161 | |
162 | /*----------------------------------------------------------------------- | |
163 | * Start addresses for the final memory configuration | |
164 | * (Set up by the startup code) | |
6d0f6bcf | 165 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
545c8e0a | 166 | */ |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
168 | #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ | |
012522fe | 169 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
545c8e0a MF |
170 | |
171 | #ifdef CONFIG_MONITOR_IS_IN_RAM | |
6d0f6bcf | 172 | #define CONFIG_SYS_MONITOR_BASE 0x20000 |
545c8e0a | 173 | #else |
6d0f6bcf | 174 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
545c8e0a MF |
175 | #endif |
176 | ||
6d0f6bcf JCPV |
177 | #define CONFIG_SYS_MONITOR_LEN 0x20000 |
178 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
179 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 | |
545c8e0a MF |
180 | |
181 | /* | |
182 | * For booting Linux, the board info and command line data | |
183 | * have to be in the first 8 MB of memory, since this is | |
184 | * the maximum mapped by the Linux kernel during initialization ?? | |
185 | */ | |
d6e4baf4 TL |
186 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
187 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) | |
545c8e0a MF |
188 | |
189 | /*----------------------------------------------------------------------- | |
190 | * FLASH organization | |
191 | */ | |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
193 | #define CONFIG_SYS_MAX_FLASH_SECT 11 /* max number of sectors on one chip */ | |
194 | #define CONFIG_SYS_FLASH_ERASE_TOUT 1000 | |
545c8e0a | 195 | |
6d0f6bcf | 196 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 197 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf | 198 | #define CONFIG_SYS_FLASH_SIZE 0x200000 |
545c8e0a MF |
199 | |
200 | /*----------------------------------------------------------------------- | |
201 | * Cache Configuration | |
202 | */ | |
6d0f6bcf | 203 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
545c8e0a | 204 | |
dd9f054e | 205 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 206 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 207 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 208 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
209 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) |
210 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
211 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
212 | CF_ACR_EN | CF_ACR_SM_ALL) | |
213 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ | |
214 | CF_CACR_DISD | CF_CACR_INVI | \ | |
215 | CF_CACR_CEIB | CF_CACR_DCM | \ | |
216 | CF_CACR_EUSP) | |
217 | ||
545c8e0a MF |
218 | /*----------------------------------------------------------------------- |
219 | * Memory bank definitions | |
220 | */ | |
012522fe TL |
221 | #define CONFIG_SYS_CS0_BASE 0xffe00000 |
222 | #define CONFIG_SYS_CS0_CTRL 0x00001980 | |
223 | #define CONFIG_SYS_CS0_MASK 0x001F0001 | |
545c8e0a | 224 | |
012522fe TL |
225 | #define CONFIG_SYS_CS1_BASE 0x30000000 |
226 | #define CONFIG_SYS_CS1_CTRL 0x00001900 | |
227 | #define CONFIG_SYS_CS1_MASK 0x00070001 | |
545c8e0a MF |
228 | |
229 | /*----------------------------------------------------------------------- | |
230 | * Port configuration | |
231 | */ | |
6d0f6bcf | 232 | #define CONFIG_SYS_FECI2C 0x0FA0 |
545c8e0a MF |
233 | |
234 | #endif /* _M5275EVB_H */ |