[people/ms/u-boot.git] / include / configs / M5282EVB.h

/*
 * Configuation settings for the Motorola MC5282EVB board.
 *
 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _CONFIG_M5282EVB_H
#define _CONFIG_M5282EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define	CONFIG_MCF52x2		/* define processor family */
#define CONFIG_M5282		/* define processor type */

#define CONFIG_MCFTMR

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#undef	CONFIG_MONITOR_IS_IN_RAM	/* define if monitor is started from a pre-loader */

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_ADDR		0xffe04000
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_IS_IN_FLASH	1

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_MII

#undef CONFIG_CMD_LOADS
#undef CONFIG_CMD_LOADB

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_MULTI		1
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_BOOTDELAY	5
#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* CONFIG_MCFFEC */

#define CONFIG_HOSTNAME		M5282EVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off ffe00000 ffe3ffff;"	\
	"era ffe00000 ffe3ffff;"		\
	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_SYS_PROMPT		"-> "
#define	CONFIG_SYS_LONGHELP		/* undef to save memory         */

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024	/* Console I/O Buffer Size      */
#else
#define	CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size      */
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS		16	/* max number of command args   */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		0x20000

#define CONFIG_SYS_MEMTEST_START	0x400
#define CONFIG_SYS_MEMTEST_END		0x380000

#define CONFIG_SYS_HZ			1000
#define	CONFIG_SYS_CLK			64000000

/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */

#define CONFIG_SYS_MFD			0x02	/* PLL Multiplication Factor Devider */
#define CONFIG_SYS_RFD			0x00	/* PLL Reduce Frecuency Devider */

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
#define	CONFIG_SYS_MBAR		0x40000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
#define CONFIG_SYS_INIT_RAM_END	0x10000	/* End of used area in internal SRAM    */
#define CONFIG_SYS_GBL_DATA_SIZE	64	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define	CONFIG_SYS_SDRAM_SIZE		16	/* SDRAM size in MB */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#define	CONFIG_SYS_INT_FLASH_BASE	0xf0000000
#define CONFIG_SYS_INT_FLASH_ENABLE	0x21

/* If M5282 port is fully implemented the monitor base will be behind
 * the vector table. */
#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#else
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x418)	/* 24 Byte for CFM-Config */
#endif

#define CONFIG_SYS_MONITOR_LEN		0x20000
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_END - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_END - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV + CF_CACR_DCM)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_DISD | \
					 CF_CACR_CEIB | CF_CACR_DBWE | \
					 CF_CACR_EUSP)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
#define CONFIG_SYS_CS0_BASE		0xFFE00000
#define CONFIG_SYS_CS0_CTRL		0x00001980
#define CONFIG_SYS_CS0_MASK		0x001F0001

/*-----------------------------------------------------------------------
 * Port configuration
 */
#define CONFIG_SYS_PACNT		0x0000000	/* Port A D[31:24] */
#define CONFIG_SYS_PADDR		0x0000000
#define CONFIG_SYS_PADAT		0x0000000

#define CONFIG_SYS_PBCNT		0x0000000	/* Port B D[23:16] */
#define CONFIG_SYS_PBDDR		0x0000000
#define CONFIG_SYS_PBDAT		0x0000000

#define CONFIG_SYS_PCCNT		0x0000000	/* Port C D[15:08] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PDCNT		0x0000000	/* Port D D[07:00] */
#define CONFIG_SYS_PCDDR		0x0000000
#define CONFIG_SYS_PCDAT		0x0000000

#define CONFIG_SYS_PEHLPAR		0xC0
#define CONFIG_SYS_PUAPAR		0x0F	/* UA0..UA3 = Uart 0 +1 */
#define CONFIG_SYS_DDRUA		0x05
#define CONFIG_SYS_PJPAR		0xFF

#endif				/* _CONFIG_M5282EVB_H */
Commit	Line	Data
bf9e3b38 WD	1	/*
	2	* Configuation settings for the Motorola MC5282EVB board.
	3	*
	4	* (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	/*
	26	* board/config.h - configuration options, board specific
	27	*/
	28
4e5ca3eb WD	29	#ifndef _CONFIG_M5282EVB_H
	30	#define _CONFIG_M5282EVB_H
	31
bf9e3b38 WD	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
f28e1bd9 TL	36	#define CONFIG_MCF52x2 /* define processor family */
f28e1bd9 TL	37	#define CONFIG_M5282 /* define processor type */
bf9e3b38	38
f28e1bd9	39	#define CONFIG_MCFTMR
bf9e3b38	40
f28e1bd9	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
79e0799c	43	#define CONFIG_BAUDRATE 115200
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
4e5ca3eb	45
f28e1bd9	46	#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
bf9e3b38 WD	47
	48	/* Configuration for environment
	49	* Environment is embedded in u-boot in the second sector of the flash
	50	*/
0e8d1586 JCPV	51	#define CONFIG_ENV_ADDR 0xffe04000
0e8d1586 JCPV	52	#define CONFIG_ENV_SIZE 0x2000
5a1aceb0	53	#define CONFIG_ENV_IS_IN_FLASH 1
bf9e3b38	54
659e2f67 JL	55	/*
	56	* BOOTP options
	57	*/
	58	#define CONFIG_BOOTP_BOOTFILESIZE
	59	#define CONFIG_BOOTP_BOOTPATH
	60	#define CONFIG_BOOTP_GATEWAY
	61	#define CONFIG_BOOTP_HOSTNAME
	62
8353e139 JL	63	/*
	64	* Command line configuration.
	65	*/
	66	#include <config_cmd_default.h>
dd9f054e	67	#define CONFIG_CMD_CACHE
f28e1bd9 TL	68	#define CONFIG_CMD_NET
	69	#define CONFIG_CMD_PING
	70	#define CONFIG_CMD_MII
8353e139 JL	71
	72	#undef CONFIG_CMD_LOADS
	73	#undef CONFIG_CMD_LOADB
	74
f28e1bd9 TL	75	#define CONFIG_MCFFEC
	76	#ifdef CONFIG_MCFFEC
	77	# define CONFIG_NET_MULTI 1
	78	# define CONFIG_MII 1
0f3ba7e9	79	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	80	# define CONFIG_SYS_DISCOVER_PHY
	81	# define CONFIG_SYS_RX_ETH_BUFFER 8
	82	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	83
6d0f6bcf JCPV	84	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	85	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	86	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	87	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	88	# ifndef CONFIG_SYS_DISCOVER_PHY
f28e1bd9 TL	89	# define FECDUPLEX FULL
	90	# define FECSPEED _100BASET
	91	# else
6d0f6bcf JCPV	92	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	93	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
f28e1bd9	94	# endif
6d0f6bcf	95	# endif /* CONFIG_SYS_DISCOVER_PHY */
f28e1bd9	96	#endif
bf9e3b38	97
bf9e3b38	98	#define CONFIG_BOOTDELAY 5
f28e1bd9 TL	99	#ifdef CONFIG_MCFFEC
	100	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	101	# define CONFIG_IPADDR 192.162.1.2
	102	# define CONFIG_NETMASK 255.255.255.0
	103	# define CONFIG_SERVERIP 192.162.1.1
	104	# define CONFIG_GATEWAYIP 192.162.1.1
	105	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	106	#endif /* CONFIG_MCFFEC */
	107
4cb4e654	108	#define CONFIG_HOSTNAME M5282EVB
f28e1bd9 TL	109	#define CONFIG_EXTRA_ENV_SETTINGS \
	110	"netdev=eth0\0" \
	111	"loadaddr=10000\0" \
	112	"u-boot=u-boot.bin\0" \
	113	"load=tftp ${loadaddr) ${u-boot}\0" \
	114	"upd=run load; run prog\0" \
	115	"prog=prot off ffe00000 ffe3ffff;" \
	116	"era ffe00000 ffe3ffff;" \
	117	"cp.b ${loadaddr} ffe00000 ${filesize};"\
	118	"save\0" \
	119	""
bf9e3b38	120
6d0f6bcf JCPV	121	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	122	#define CONFIG_SYS_LONGHELP /* undef to save memory */
bf9e3b38	123
8353e139	124	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	125	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
bf9e3b38	126	#else
6d0f6bcf	127	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
bf9e3b38	128	#endif
6d0f6bcf JCPV	129	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	130	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	131	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
bf9e3b38	132
6d0f6bcf	133	#define CONFIG_SYS_LOAD_ADDR 0x20000
bf9e3b38	134
6d0f6bcf JCPV	135	#define CONFIG_SYS_MEMTEST_START 0x400
6d0f6bcf JCPV	136	#define CONFIG_SYS_MEMTEST_END 0x380000
bf9e3b38	137
6d0f6bcf JCPV	138	#define CONFIG_SYS_HZ 1000
6d0f6bcf JCPV	139	#define CONFIG_SYS_CLK 64000000
bf9e3b38	140
f28e1bd9 TL	141	/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
f28e1bd9 TL	142
6d0f6bcf JCPV	143	#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
6d0f6bcf JCPV	144	#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
bf9e3b38 WD	145
	146	/*
	147	* Low Level Configuration Settings
	148	* (address mappings, register initial values, etc.)
	149	* You should know what you are doing if you make changes here.
	150	*/
6d0f6bcf	151	#define CONFIG_SYS_MBAR 0x40000000
bf9e3b38	152
bf9e3b38 WD	153	/*-----------------------------------------------------------------------
	154	* Definitions for initial stack pointer and data area (in DPRAM)
	155	*/
6d0f6bcf JCPV	156	#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
	157	#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */
	158	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	159	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	160	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
bf9e3b38 WD	161
	162	/*-----------------------------------------------------------------------
	163	* Start addresses for the final memory configuration
	164	* (Set up by the startup code)
6d0f6bcf	165	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
bf9e3b38	166	*/
6d0f6bcf JCPV	167	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	168	#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
012522fe	169	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
6d0f6bcf JCPV	170	#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
6d0f6bcf JCPV	171	#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
bf9e3b38 WD	172
	173	/* If M5282 port is fully implemented the monitor base will be behind
	174	* the vector table. */
14d0a02a	175	#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
6d0f6bcf	176	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
f28e1bd9	177	#else
14d0a02a	178	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
f28e1bd9	179	#endif
bf9e3b38	180
6d0f6bcf JCPV	181	#define CONFIG_SYS_MONITOR_LEN 0x20000
	182	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
	183	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
bf9e3b38	184
bf9e3b38 WD	185	/*
	186	* For booting Linux, the board info and command line data
	187	* have to be in the first 8 MB of memory, since this is
	188	* the maximum mapped by the Linux kernel during initialization ??
	189	*/
6d0f6bcf	190	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
bf9e3b38 WD	191
	192	/*-----------------------------------------------------------------------
	193	* FLASH organization
	194	*/
6d0f6bcf JCPV	195	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	196	#ifdef CONFIG_SYS_FLASH_CFI
f28e1bd9	197
00b1883a	198	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	199	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	200	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	201	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	202	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	203	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	204	# define CONFIG_SYS_FLASH_CHECKSUM
	205	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
f28e1bd9	206	#endif
bf9e3b38 WD	207
	208	/*-----------------------------------------------------------------------
	209	* Cache Configuration
	210	*/
6d0f6bcf	211	#define CONFIG_SYS_CACHELINE_SIZE 16
bf9e3b38	212
dd9f054e TL	213	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	214	CONFIG_SYS_INIT_RAM_END - 8)
	215	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	216	CONFIG_SYS_INIT_RAM_END - 4)
	217	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
	218	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	219	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	220	CF_ACR_EN \| CF_ACR_SM_ALL)
	221	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB \| CF_CACR_DISD \| \
	222	CF_CACR_CEIB \| CF_CACR_DBWE \| \
	223	CF_CACR_EUSP)
	224
bf9e3b38 WD	225	/*-----------------------------------------------------------------------
	226	* Memory bank definitions
	227	*/
012522fe TL	228	#define CONFIG_SYS_CS0_BASE 0xFFE00000
	229	#define CONFIG_SYS_CS0_CTRL 0x00001980
	230	#define CONFIG_SYS_CS0_MASK 0x001F0001
	231
bf9e3b38 WD	232	/*-----------------------------------------------------------------------
	233	* Port configuration
	234	*/
6d0f6bcf JCPV	235	#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
	236	#define CONFIG_SYS_PADDR 0x0000000
	237	#define CONFIG_SYS_PADAT 0x0000000
	238
	239	#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
	240	#define CONFIG_SYS_PBDDR 0x0000000
	241	#define CONFIG_SYS_PBDAT 0x0000000
	242
	243	#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
	244	#define CONFIG_SYS_PCDDR 0x0000000
	245	#define CONFIG_SYS_PCDAT 0x0000000
	246
	247	#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
	248	#define CONFIG_SYS_PCDDR 0x0000000
	249	#define CONFIG_SYS_PCDAT 0x0000000
	250
	251	#define CONFIG_SYS_PEHLPAR 0xC0
	252	#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
	253	#define CONFIG_SYS_DDRUA 0x05
	254	#define CONFIG_SYS_PJPAR 0xFF
4e5ca3eb	255
f28e1bd9	256	#endif /* _CONFIG_M5282EVB_H */