]>
Commit | Line | Data |
---|---|---|
8e585f02 TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF5329 FireEngine board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
8e585f02 TL |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M5329EVB_H | |
15 | #define _M5329EVB_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
8e585f02 | 21 | |
9998bd37 | 22 | #define CONFIG_MCFUART |
6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
8e585f02 TL |
24 | |
25 | #undef CONFIG_WATCHDOG | |
26 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ | |
27 | ||
6d0f6bcf | 28 | #define CONFIG_SYS_UNIFY_CACHE |
8e585f02 TL |
29 | |
30 | #define CONFIG_MCFFEC | |
31 | #ifdef CONFIG_MCFFEC | |
8e585f02 | 32 | # define CONFIG_MII 1 |
0f3ba7e9 | 33 | # define CONFIG_MII_INIT 1 |
6d0f6bcf JCPV |
34 | # define CONFIG_SYS_DISCOVER_PHY |
35 | # define CONFIG_SYS_RX_ETH_BUFFER 8 | |
36 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8e585f02 | 37 | |
6d0f6bcf JCPV |
38 | # define CONFIG_SYS_FEC0_PINMUX 0 |
39 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
53677ef1 | 40 | # define MCFFEC_TOUT_LOOP 50000 |
6d0f6bcf JCPV |
41 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
42 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
8e585f02 TL |
43 | # define FECDUPLEX FULL |
44 | # define FECSPEED _100BASET | |
45 | # else | |
6d0f6bcf JCPV |
46 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
47 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
8e585f02 | 48 | # endif |
6d0f6bcf | 49 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
8e585f02 TL |
50 | #endif |
51 | ||
8e585f02 | 52 | #define CONFIG_MCFRTC |
48dbfeab | 53 | #undef RTC_DEBUG |
8e585f02 TL |
54 | |
55 | /* Timer */ | |
56 | #define CONFIG_MCFTMR | |
8e585f02 | 57 | #undef CONFIG_MCFPIT |
8e585f02 | 58 | |
eaf9e447 | 59 | /* I2C */ |
00f792e0 HS |
60 | #define CONFIG_SYS_I2C |
61 | #define CONFIG_SYS_I2C_FSL | |
62 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
63 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
64 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 | |
6d0f6bcf | 65 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
eaf9e447 | 66 | |
ab77bc54 TL |
67 | #define CONFIG_UDP_CHECKSUM |
68 | ||
8e585f02 | 69 | #ifdef CONFIG_MCFFEC |
eaf9e447 TL |
70 | # define CONFIG_IPADDR 192.162.1.2 |
71 | # define CONFIG_NETMASK 255.255.255.0 | |
72 | # define CONFIG_SERVERIP 192.162.1.1 | |
8e585f02 | 73 | # define CONFIG_GATEWAYIP 192.162.1.1 |
8e585f02 TL |
74 | #endif /* FEC_ENET */ |
75 | ||
76 | #define CONFIG_HOSTNAME M5329EVB | |
77 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
78 | "netdev=eth0\0" \ | |
79 | "loadaddr=40010000\0" \ | |
80 | "u-boot=u-boot.bin\0" \ | |
81 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
82 | "upd=run load; run prog\0" \ | |
09933fb0 JJ |
83 | "prog=prot off 0 3ffff;" \ |
84 | "era 0 3ffff;" \ | |
8e585f02 TL |
85 | "cp.b ${loadaddr} 0 ${filesize};" \ |
86 | "save\0" \ | |
87 | "" | |
88 | ||
eaf9e447 | 89 | #define CONFIG_PRAM 512 /* 512 KB */ |
6d0f6bcf | 90 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
8e585f02 | 91 | |
6d0f6bcf JCPV |
92 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
93 | #define CONFIG_SYS_LOAD_ADDR 0x40010000 | |
8e585f02 | 94 | |
6d0f6bcf JCPV |
95 | #define CONFIG_SYS_CLK 80000000 |
96 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3 | |
8e585f02 | 97 | |
6d0f6bcf | 98 | #define CONFIG_SYS_MBAR 0xFC000000 |
8e585f02 | 99 | |
6d0f6bcf | 100 | #define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000) |
1a33ce65 | 101 | |
8e585f02 TL |
102 | /* |
103 | * Low Level Configuration Settings | |
104 | * (address mappings, register initial values, etc.) | |
105 | * You should know what you are doing if you make changes here. | |
106 | */ | |
107 | /*----------------------------------------------------------------------- | |
108 | * Definitions for initial stack pointer and data area (in DPRAM) | |
109 | */ | |
6d0f6bcf | 110 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 |
553f0982 | 111 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ |
6d0f6bcf | 112 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 |
25ddd1fb | 113 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
6d0f6bcf | 114 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
8e585f02 TL |
115 | |
116 | /*----------------------------------------------------------------------- | |
117 | * Start addresses for the final memory configuration | |
118 | * (Set up by the startup code) | |
6d0f6bcf | 119 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
8e585f02 | 120 | */ |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
122 | #define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */ | |
123 | #define CONFIG_SYS_SDRAM_CFG1 0x53722730 | |
124 | #define CONFIG_SYS_SDRAM_CFG2 0x56670000 | |
125 | #define CONFIG_SYS_SDRAM_CTRL 0xE1092000 | |
126 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
127 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 | |
8e585f02 | 128 | |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
130 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
8e585f02 | 131 | |
6d0f6bcf JCPV |
132 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
133 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
8e585f02 | 134 | |
6d0f6bcf JCPV |
135 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
136 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
8e585f02 TL |
137 | |
138 | /* | |
139 | * For booting Linux, the board info and command line data | |
140 | * have to be in the first 8 MB of memory, since this is | |
141 | * the maximum mapped by the Linux kernel during initialization ?? | |
142 | */ | |
6d0f6bcf | 143 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
d6e4baf4 | 144 | #define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) |
8e585f02 TL |
145 | |
146 | /*----------------------------------------------------------------------- | |
147 | * FLASH organization | |
148 | */ | |
6d0f6bcf JCPV |
149 | #define CONFIG_SYS_FLASH_CFI |
150 | #ifdef CONFIG_SYS_FLASH_CFI | |
00b1883a | 151 | # define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
152 | # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ |
153 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
154 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
155 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
156 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
8e585f02 TL |
157 | #endif |
158 | ||
96d94385 | 159 | #ifdef CONFIG_NANDFLASH_SIZE |
6d0f6bcf JCPV |
160 | # define CONFIG_SYS_MAX_NAND_DEVICE 1 |
161 | # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE | |
162 | # define CONFIG_SYS_NAND_SIZE 1 | |
163 | # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } | |
ab77bc54 TL |
164 | # define NAND_ALLOW_ERASE_ALL 1 |
165 | # define CONFIG_JFFS2_NAND 1 | |
166 | # define CONFIG_JFFS2_DEV "nand0" | |
6d0f6bcf | 167 | # define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1) |
ab77bc54 | 168 | # define CONFIG_JFFS2_PART_OFFSET 0x00000000 |
1a33ce65 TL |
169 | #endif |
170 | ||
6d0f6bcf | 171 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE |
8e585f02 TL |
172 | |
173 | /* Configuration for environment | |
174 | * Environment is embedded in u-boot in the second sector of the flash | |
175 | */ | |
0e8d1586 JCPV |
176 | #define CONFIG_ENV_OFFSET 0x4000 |
177 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
8e585f02 | 178 | |
5296cb1d | 179 | #define LDS_BOARD_TEXT \ |
0649cd0d SG |
180 | . = DEFINED(env_offset) ? env_offset : .; \ |
181 | env/embedded.o(.text*); | |
5296cb1d | 182 | |
8e585f02 TL |
183 | /*----------------------------------------------------------------------- |
184 | * Cache Configuration | |
185 | */ | |
6d0f6bcf | 186 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
8e585f02 | 187 | |
dd9f054e | 188 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 189 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
dd9f054e | 190 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
553f0982 | 191 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
dd9f054e TL |
192 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA) |
193 | #define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ | |
194 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
195 | CF_ACR_EN | CF_ACR_SM_ALL) | |
196 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC | CF_CACR_CINVA | \ | |
197 | CF_CACR_DCM_P) | |
198 | ||
8e585f02 TL |
199 | /*----------------------------------------------------------------------- |
200 | * Chipselect bank definitions | |
201 | */ | |
202 | /* | |
203 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
204 | * CS1 - CompactFlash and registers | |
205 | * CS2 - NAND Flash 16, 32, or 64MB | |
206 | * CS3 - Available | |
207 | * CS4 - Available | |
208 | * CS5 - Available | |
209 | */ | |
6d0f6bcf JCPV |
210 | #define CONFIG_SYS_CS0_BASE 0 |
211 | #define CONFIG_SYS_CS0_MASK 0x007f0001 | |
212 | #define CONFIG_SYS_CS0_CTRL 0x00001fa0 | |
8e585f02 | 213 | |
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_CS1_BASE 0x10000000 |
215 | #define CONFIG_SYS_CS1_MASK 0x001f0001 | |
216 | #define CONFIG_SYS_CS1_CTRL 0x002A3780 | |
8e585f02 | 217 | |
96d94385 | 218 | #ifdef CONFIG_NANDFLASH_SIZE |
6d0f6bcf | 219 | #define CONFIG_SYS_CS2_BASE 0x20000000 |
96d94385 | 220 | #define CONFIG_SYS_CS2_MASK ((CONFIG_NANDFLASH_SIZE << 20) | 1) |
6d0f6bcf | 221 | #define CONFIG_SYS_CS2_CTRL 0x00001f60 |
8e585f02 TL |
222 | #endif |
223 | ||
8e585f02 | 224 | #endif /* _M5329EVB_H */ |