[people/ms/u-boot.git] / include / configs / M5373EVB.h

/*
 * Configuation settings for the Freescale MCF5373 FireEngine board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5373EVB_H
#define _M5373EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF532x		/* define processor family */
#define CONFIG_M5373		/* define processor type */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#undef CONFIG_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	3360	/* timeout in ms, max is 3.36 sec */

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO

#ifdef NANDFLASH_SIZE
#      define CONFIG_CMD_NAND
#endif

#define CONFIG_SYS_UNIFY_CACHE

#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_MULTI		1
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_MCFRTC
#undef RTC_DEBUG

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hw support */
#undef CONFIG_SOFT_I2C		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		80000
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_ETHADDR	00:e0:0c:bc:e5:60
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M5373EVB
#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"			\
	"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0"	\
	"u-boot=u-boot.bin\0"	\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"	\
	"prog=prot off 0 2ffff;"	\
	"era 0 2ffff;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"	\
	""

#define CONFIG_PRAM		512	/* 512 KB */
#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#ifdef CONFIG_CMD_KGDB
#	define CONFIG_SYS_CBSIZE	1024	/* Console I/O Buffer Size */
#else
#	define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE			(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */
#define CONFIG_SYS_LOAD_ADDR		0x40010000

#define CONFIG_SYS_HZ			1000
#define CONFIG_SYS_CLK			80000000
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 3

#define CONFIG_SYS_MBAR		0xFC000000

#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		32	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x53722730
#define CONFIG_SYS_SDRAM_CFG2		0x56670000
#define CONFIG_SYS_SDRAM_CTRL		0xE1092000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x018D0000

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#endif

#ifdef NANDFLASH_SIZE
#	define CONFIG_SYS_MAX_NAND_DEVICE	1
#	define CONFIG_SYS_NAND_BASE		CONFIG_SYS_CS2_BASE
#	define CONFIG_SYS_NAND_SIZE		1
#	define CONFIG_SYS_NAND_BASE_LIST	{ CONFIG_SYS_NAND_BASE }
#	define NAND_ALLOW_ERASE_ALL	1
#	define CONFIG_JFFS2_NAND	1
#	define CONFIG_JFFS2_DEV		"nand0"
#	define CONFIG_JFFS2_PART_SIZE	(CONFIG_SYS_CS2_MASK & ~1)
#	define CONFIG_JFFS2_PART_OFFSET	0x00000000
#endif

#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#define CONFIG_ENV_OFFSET		0x4000
#define CONFIG_ENV_SECT_SIZE	0x2000
#define CONFIG_ENV_IS_IN_FLASH	1

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINVA)
#define CONFIG_SYS_CACHE_ACR0		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_EC | CF_CACR_CINVA | \
					 CF_CACR_DCM_P)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - CompactFlash and registers
 * CS2 - NAND Flash 16, 32, or 64MB
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0
#define CONFIG_SYS_CS0_MASK		0x007f0001
#define CONFIG_SYS_CS0_CTRL		0x00001fa0

#define CONFIG_SYS_CS1_BASE		0x10000000
#define CONFIG_SYS_CS1_MASK		0x001f0001
#define CONFIG_SYS_CS1_CTRL		0x002A3780

#ifdef NANDFLASH_SIZE
#define CONFIG_SYS_CS2_BASE		0x20000000
#define CONFIG_SYS_CS2_MASK		((NANDFLASH_SIZE << 20) | 1)
#define CONFIG_SYS_CS2_CTRL		0x00001f60
#endif

#endif				/* _M5373EVB_H */
Commit	Line	Data
aa5f1f9d TL	1	/*
	2	* Configuation settings for the Freescale MCF5373 FireEngine board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef _M5373EVB_H
	31	#define _M5373EVB_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_MCF532x /* define processor family */
	38	#define CONFIG_M5373 /* define processor type */
	39
aa5f1f9d	40	#define CONFIG_MCFUART
6d0f6bcf	41	#define CONFIG_SYS_UART_PORT (0)
aa5f1f9d	42	#define CONFIG_BAUDRATE 115200
6d0f6bcf	43	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
aa5f1f9d TL	44
	45	#undef CONFIG_WATCHDOG
	46	#define CONFIG_WATCHDOG_TIMEOUT 3360 /* timeout in ms, max is 3.36 sec */
	47
	48	/* Command line configuration */
	49	#include <config_cmd_default.h>
	50
	51	#define CONFIG_CMD_CACHE
	52	#define CONFIG_CMD_DATE
	53	#define CONFIG_CMD_ELF
	54	#define CONFIG_CMD_FLASH
	55	#define CONFIG_CMD_I2C
	56	#define CONFIG_CMD_MEMORY
	57	#define CONFIG_CMD_MISC
	58	#define CONFIG_CMD_MII
	59	#define CONFIG_CMD_NET
	60	#define CONFIG_CMD_PING
	61	#define CONFIG_CMD_REGINFO
	62
	63	#ifdef NANDFLASH_SIZE
	64	# define CONFIG_CMD_NAND
	65	#endif
	66
6d0f6bcf	67	#define CONFIG_SYS_UNIFY_CACHE
aa5f1f9d TL	68
	69	#define CONFIG_MCFFEC
	70	#ifdef CONFIG_MCFFEC
	71	# define CONFIG_NET_MULTI 1
	72	# define CONFIG_MII 1
0f3ba7e9	73	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	74	# define CONFIG_SYS_DISCOVER_PHY
	75	# define CONFIG_SYS_RX_ETH_BUFFER 8
	76	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
aa5f1f9d	77
6d0f6bcf JCPV	78	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	79	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
53677ef1	80	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	81	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	82	# ifndef CONFIG_SYS_DISCOVER_PHY
aa5f1f9d TL	83	# define FECDUPLEX FULL
	84	# define FECSPEED _100BASET
	85	# else
6d0f6bcf JCPV	86	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	87	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
aa5f1f9d	88	# endif
6d0f6bcf	89	# endif /* CONFIG_SYS_DISCOVER_PHY */
aa5f1f9d TL	90	#endif
	91
	92	#define CONFIG_MCFRTC
	93	#undef RTC_DEBUG
	94
	95	/* Timer */
	96	#define CONFIG_MCFTMR
	97	#undef CONFIG_MCFPIT
	98
	99	/* I2C */
	100	#define CONFIG_FSL_I2C
	101	#define CONFIG_HARD_I2C /* I2C with hw support */
	102	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	103	#define CONFIG_SYS_I2C_SPEED 80000
	104	#define CONFIG_SYS_I2C_SLAVE 0x7F
	105	#define CONFIG_SYS_I2C_OFFSET 0x58000
	106	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
aa5f1f9d TL	107
	108	#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	109	#define CONFIG_UDP_CHECKSUM
	110
	111	#ifdef CONFIG_MCFFEC
	112	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	113	# define CONFIG_IPADDR 192.162.1.2
	114	# define CONFIG_NETMASK 255.255.255.0
	115	# define CONFIG_SERVERIP 192.162.1.1
	116	# define CONFIG_GATEWAYIP 192.162.1.1
	117	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	118	#endif /* FEC_ENET */
	119
	120	#define CONFIG_HOSTNAME M5373EVB
	121	#define CONFIG_EXTRA_ENV_SETTINGS \
	122	"netdev=eth0\0" \
6d0f6bcf	123	"loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0" \
aa5f1f9d TL	124	"u-boot=u-boot.bin\0" \
	125	"load=tftp ${loadaddr) ${u-boot}\0" \
	126	"upd=run load; run prog\0" \
	127	"prog=prot off 0 2ffff;" \
	128	"era 0 2ffff;" \
	129	"cp.b ${loadaddr} 0 ${filesize};" \
	130	"save\0" \
	131	""
	132
	133	#define CONFIG_PRAM 512 /* 512 KB */
6d0f6bcf JCPV	134	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	135	#define CONFIG_SYS_LONGHELP /* undef to save memory */
aa5f1f9d TL	136
aa5f1f9d TL	137	#ifdef CONFIG_CMD_KGDB
6d0f6bcf	138	# define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
aa5f1f9d	139	#else
6d0f6bcf	140	# define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
aa5f1f9d TL	141	#endif
aa5f1f9d TL	142
6d0f6bcf JCPV	143	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	144	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	145	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	146	#define CONFIG_SYS_LOAD_ADDR 0x40010000
aa5f1f9d	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_HZ 1000
	149	#define CONFIG_SYS_CLK 80000000
	150	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 3
aa5f1f9d	151
6d0f6bcf	152	#define CONFIG_SYS_MBAR 0xFC000000
aa5f1f9d	153
6d0f6bcf	154	#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)
aa5f1f9d TL	155
	156	/*
	157	* Low Level Configuration Settings
	158	* (address mappings, register initial values, etc.)
	159	* You should know what you are doing if you make changes here.
	160	*/
	161	/*-----------------------------------------------------------------------
	162	* Definitions for initial stack pointer and data area (in DPRAM)
	163	*/
6d0f6bcf	164	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	165	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf JCPV	166	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
6d0f6bcf JCPV	167	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
553f0982	168	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - CONFIG_SYS_GBL_DATA_SIZE) - 0x10)
6d0f6bcf	169	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
aa5f1f9d TL	170
	171	/*-----------------------------------------------------------------------
	172	* Start addresses for the final memory configuration
	173	* (Set up by the startup code)
6d0f6bcf	174	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
aa5f1f9d	175	*/
6d0f6bcf JCPV	176	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	177	#define CONFIG_SYS_SDRAM_SIZE 32 /* SDRAM size in MB */
	178	#define CONFIG_SYS_SDRAM_CFG1 0x53722730
	179	#define CONFIG_SYS_SDRAM_CFG2 0x56670000
	180	#define CONFIG_SYS_SDRAM_CTRL 0xE1092000
	181	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	182	#define CONFIG_SYS_SDRAM_MODE 0x018D0000
aa5f1f9d	183
6d0f6bcf JCPV	184	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	185	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
aa5f1f9d	186
6d0f6bcf JCPV	187	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	188	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
aa5f1f9d	189
6d0f6bcf JCPV	190	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	191	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
aa5f1f9d TL	192
	193	/*
	194	* For booting Linux, the board info and command line data
	195	* have to be in the first 8 MB of memory, since this is
	196	* the maximum mapped by the Linux kernel during initialization ??
	197	*/
6d0f6bcf	198	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
d6e4baf4	199	#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20)
aa5f1f9d TL	200
	201	/*-----------------------------------------------------------------------
	202	* FLASH organization
	203	*/
6d0f6bcf JCPV	204	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	205	#ifdef CONFIG_SYS_FLASH_CFI
00b1883a	206	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	207	# define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */
	208	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	209	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	210	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	211	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
aa5f1f9d TL	212	#endif
	213
	214	#ifdef NANDFLASH_SIZE
6d0f6bcf JCPV	215	# define CONFIG_SYS_MAX_NAND_DEVICE 1
	216	# define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE
	217	# define CONFIG_SYS_NAND_SIZE 1
	218	# define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
aa5f1f9d TL	219	# define NAND_ALLOW_ERASE_ALL 1
	220	# define CONFIG_JFFS2_NAND 1
	221	# define CONFIG_JFFS2_DEV "nand0"
6d0f6bcf	222	# define CONFIG_JFFS2_PART_SIZE (CONFIG_SYS_CS2_MASK & ~1)
aa5f1f9d TL	223	# define CONFIG_JFFS2_PART_OFFSET 0x00000000
	224	#endif
	225
6d0f6bcf	226	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
aa5f1f9d TL	227
	228	/* Configuration for environment
	229	* Environment is embedded in u-boot in the second sector of the flash
	230	*/
0e8d1586 JCPV	231	#define CONFIG_ENV_OFFSET 0x4000
0e8d1586 JCPV	232	#define CONFIG_ENV_SECT_SIZE 0x2000
5a1aceb0	233	#define CONFIG_ENV_IS_IN_FLASH 1
aa5f1f9d TL	234
	235	/*-----------------------------------------------------------------------
	236	* Cache Configuration
	237	*/
6d0f6bcf	238	#define CONFIG_SYS_CACHELINE_SIZE 16
aa5f1f9d	239
dd9f054e	240	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	241	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	242	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	243	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	244	#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINVA)
	245	#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE \| \
	246	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	247	CF_ACR_EN \| CF_ACR_SM_ALL)
	248	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_EC \| CF_CACR_CINVA \| \
	249	CF_CACR_DCM_P)
	250
aa5f1f9d TL	251	/*-----------------------------------------------------------------------
	252	* Chipselect bank definitions
	253	*/
	254	/*
	255	* CS0 - NOR Flash 1, 2, 4, or 8MB
	256	* CS1 - CompactFlash and registers
	257	* CS2 - NAND Flash 16, 32, or 64MB
	258	* CS3 - Available
	259	* CS4 - Available
	260	* CS5 - Available
	261	*/
6d0f6bcf JCPV	262	#define CONFIG_SYS_CS0_BASE 0
	263	#define CONFIG_SYS_CS0_MASK 0x007f0001
	264	#define CONFIG_SYS_CS0_CTRL 0x00001fa0
aa5f1f9d	265
6d0f6bcf JCPV	266	#define CONFIG_SYS_CS1_BASE 0x10000000
	267	#define CONFIG_SYS_CS1_MASK 0x001f0001
	268	#define CONFIG_SYS_CS1_CTRL 0x002A3780
aa5f1f9d TL	269
aa5f1f9d TL	270	#ifdef NANDFLASH_SIZE
6d0f6bcf JCPV	271	#define CONFIG_SYS_CS2_BASE 0x20000000
	272	#define CONFIG_SYS_CS2_MASK ((NANDFLASH_SIZE << 20) \| 1)
	273	#define CONFIG_SYS_CS2_CTRL 0x00001f60
aa5f1f9d TL	274	#endif
	275
	276	#endif /* _M5373EVB_H */