]>
Commit | Line | Data |
---|---|---|
186fc4db AW |
1 | /* |
2 | * Configuation settings for the Freescale MCF54418 TWR board. | |
3 | * | |
4 | * Copyright 2010-2012 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
186fc4db AW |
8 | */ |
9 | ||
10 | /* | |
11 | * board/config.h - configuration options, board specific | |
12 | */ | |
13 | ||
14 | #ifndef _M54418TWR_H | |
15 | #define _M54418TWR_H | |
16 | ||
17 | /* | |
18 | * High Level Configuration Options | |
19 | * (easy to change) | |
20 | */ | |
186fc4db AW |
21 | #define CONFIG_M54418TWR /* M54418TWR board */ |
22 | ||
23 | #define CONFIG_MCFUART | |
24 | #define CONFIG_SYS_UART_PORT (0) | |
25 | #define CONFIG_BAUDRATE 115200 | |
26 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } | |
27 | ||
28 | #undef CONFIG_WATCHDOG | |
29 | ||
30 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
31 | ||
32 | /* | |
33 | * BOOTP options | |
34 | */ | |
35 | #define CONFIG_BOOTP_BOOTFILESIZE | |
36 | #define CONFIG_BOOTP_BOOTPATH | |
37 | #define CONFIG_BOOTP_GATEWAY | |
38 | #define CONFIG_BOOTP_HOSTNAME | |
39 | ||
40 | /* Command line configuration */ | |
186fc4db | 41 | #undef CONFIG_CMD_DATE |
186fc4db AW |
42 | #undef CONFIG_CMD_JFFS2 |
43 | #undef CONFIG_CMD_UBI | |
186fc4db | 44 | #undef CONFIG_CMD_NAND |
186fc4db | 45 | #define CONFIG_CMD_REGINFO |
186fc4db AW |
46 | |
47 | /* | |
48 | * NAND FLASH | |
49 | */ | |
50 | #ifdef CONFIG_CMD_NAND | |
51 | #define CONFIG_JFFS2_NAND | |
52 | #define CONFIG_NAND_FSL_NFC | |
53 | #define CONFIG_SYS_NAND_BASE 0xFC0FC000 | |
54 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
55 | #define NAND_MAX_CHIPS CONFIG_SYS_MAX_NAND_DEVICE | |
56 | #define CONFIG_SYS_NAND_SELECT_DEVICE | |
186fc4db AW |
57 | #endif |
58 | ||
59 | /* Network configuration */ | |
60 | #define CONFIG_MCFFEC | |
61 | #ifdef CONFIG_MCFFEC | |
186fc4db AW |
62 | #define CONFIG_MII 1 |
63 | #define CONFIG_MII_INIT 1 | |
64 | #define CONFIG_SYS_DISCOVER_PHY | |
65 | #define CONFIG_SYS_RX_ETH_BUFFER 2 | |
66 | #define CONFIG_SYS_FAULT_ECCONFIG_SYS_NO_FLASHHO_LINK_DOWN | |
67 | #define CONFIG_SYS_TX_ETH_BUFFER 2 | |
68 | #define CONFIG_HAS_ETH1 | |
69 | ||
70 | #define CONFIG_SYS_FEC0_PINMUX 0 | |
71 | #define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
72 | #define CONFIG_SYS_FEC1_PINMUX 0 | |
73 | #define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_MIIBASE | |
74 | #define MCFFEC_TOUT_LOOP 50000 | |
75 | #define CONFIG_SYS_FEC0_PHYADDR 0 | |
76 | #define CONFIG_SYS_FEC1_PHYADDR 1 | |
77 | ||
186fc4db AW |
78 | |
79 | #ifdef CONFIG_SYS_NAND_BOOT | |
80 | #define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw rootfstype=jffs2 " \ | |
81 | "mtdparts=NAND:1M(u-boot)ro,7M(kernel)ro," \ | |
82 | "-(jffs2) console=ttyS0,115200" | |
83 | #else | |
84 | #define CONFIG_BOOTARGS "root=/dev/nfs rw nfsroot=" \ | |
85 | __stringify(CONFIG_SERVERIP) ":/tftpboot/" \ | |
86 | __stringify(CONFIG_IPADDR) " ip=" \ | |
87 | __stringify(CONFIG_IPADDR) ":" \ | |
88 | __stringify(CONFIG_SERVERIP)":" \ | |
89 | __stringify(CONFIG_GATEWAYIP)": " \ | |
90 | __stringify(CONFIG_NETMASK) \ | |
91 | "::eth0:off:rw console=ttyS0,115200" | |
92 | #endif | |
93 | ||
186fc4db AW |
94 | #define CONFIG_ETHPRIME "FEC0" |
95 | #define CONFIG_IPADDR 192.168.1.2 | |
96 | #define CONFIG_NETMASK 255.255.255.0 | |
97 | #define CONFIG_SERVERIP 192.168.1.1 | |
98 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
99 | ||
186fc4db AW |
100 | #define CONFIG_SYS_FEC_BUF_USE_SRAM |
101 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ | |
102 | #ifndef CONFIG_SYS_DISCOVER_PHY | |
103 | #define FECDUPLEX FULL | |
104 | #define FECSPEED _100BASET | |
105 | #define LINKSTATUS 1 | |
106 | #else | |
107 | #define LINKSTATUS 0 | |
108 | #ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
109 | #define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
110 | #endif | |
111 | #endif /* CONFIG_SYS_DISCOVER_PHY */ | |
112 | #endif | |
113 | ||
114 | #define CONFIG_HOSTNAME M54418TWR | |
115 | ||
116 | #if defined(CONFIG_CF_SBF) | |
117 | /* ST Micro serial flash */ | |
118 | #define CONFIG_SYS_LOAD_ADDR2 0x40010007 | |
119 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
120 | "netdev=eth0\0" \ | |
121 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ | |
122 | "loadaddr=0x40010000\0" \ | |
123 | "sbfhdr=sbfhdr.bin\0" \ | |
124 | "uboot=u-boot.bin\0" \ | |
125 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
126 | "tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \ | |
127 | "upd=run load; run prog\0" \ | |
128 | "prog=sf probe 0:1 1000000 3;" \ | |
129 | "sf erase 0 40000;" \ | |
130 | "sf write ${loadaddr} 0 40000;" \ | |
131 | "save\0" \ | |
132 | "" | |
133 | #elif defined(CONFIG_SYS_NAND_BOOT) | |
134 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
135 | "netdev=eth0\0" \ | |
136 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ | |
137 | "loadaddr=0x40010000\0" \ | |
138 | "u-boot=u-boot.bin\0" \ | |
139 | "load=tftp ${loadaddr} ${u-boot};\0" \ | |
140 | "upd=run load; run prog\0" \ | |
141 | "prog=nand device 0;" \ | |
142 | "nand erase 0 40000;" \ | |
143 | "nb_update ${loadaddr} ${filesize};" \ | |
144 | "save\0" \ | |
145 | "" | |
146 | #else | |
147 | #define CONFIG_SYS_UBOOT_END 0x3FFFF | |
148 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
149 | "netdev=eth0\0" \ | |
150 | "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ | |
151 | "loadaddr=40010000\0" \ | |
152 | "u-boot=u-boot.bin\0" \ | |
153 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
154 | "upd=run load; run prog\0" \ | |
155 | "prog=prot off mram" " ;" \ | |
156 | "cp.b ${loadaddr} 0 ${filesize};" \ | |
157 | "save\0" \ | |
158 | "" | |
159 | #endif | |
160 | ||
161 | /* Realtime clock */ | |
162 | #undef CONFIG_MCFRTC | |
163 | #define CONFIG_RTC_MCFRRTC | |
164 | #define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 | |
165 | ||
166 | /* Timer */ | |
167 | #define CONFIG_MCFTMR | |
168 | #undef CONFIG_MCFPIT | |
169 | ||
170 | /* I2c */ | |
00f792e0 | 171 | #undef CONFIG_SYS_FSL_I2C |
186fc4db | 172 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ |
ea818dbb | 173 | #undef CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
186fc4db AW |
174 | /* I2C speed and slave address */ |
175 | #define CONFIG_SYS_I2C_SPEED 80000 | |
176 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
177 | #define CONFIG_SYS_I2C_OFFSET 0x58000 | |
178 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR | |
179 | ||
180 | /* DSPI and Serial Flash */ | |
181 | #define CONFIG_CF_SPI | |
182 | #define CONFIG_CF_DSPI | |
183 | #define CONFIG_SERIAL_FLASH | |
184 | #define CONFIG_HARD_SPI | |
185 | #define CONFIG_SYS_SBFHDR_SIZE 0x7 | |
186 | #ifdef CONFIG_CMD_SPI | |
186fc4db AW |
187 | |
188 | # define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ | |
189 | DSPI_CTAR_PCSSCK_1CLK | \ | |
190 | DSPI_CTAR_PASC(0) | \ | |
191 | DSPI_CTAR_PDT(0) | \ | |
192 | DSPI_CTAR_CSSCK(0) | \ | |
193 | DSPI_CTAR_ASC(0) | \ | |
194 | DSPI_CTAR_DT(1)) | |
195 | # define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0) | |
196 | # define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0) | |
197 | #endif | |
198 | ||
199 | /* Input, PCI, Flexbus, and VCO */ | |
200 | #define CONFIG_EXTRA_CLOCK | |
201 | ||
202 | #define CONFIG_PRAM 2048 /* 2048 KB */ | |
203 | ||
186fc4db AW |
204 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
205 | ||
206 | #if defined(CONFIG_CMD_KGDB) | |
207 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
208 | #else | |
209 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
210 | #endif | |
211 | /* Print Buffer Size */ | |
212 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
213 | sizeof(CONFIG_SYS_PROMPT) + 16) | |
214 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
215 | /* Boot Argument Buffer Size */ | |
216 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
217 | ||
218 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) | |
219 | ||
186fc4db AW |
220 | #define CONFIG_SYS_MBAR 0xFC000000 |
221 | ||
222 | /* | |
223 | * Low Level Configuration Settings | |
224 | * (address mappings, register initial values, etc.) | |
225 | * You should know what you are doing if you make changes here. | |
226 | */ | |
227 | ||
228 | /*----------------------------------------------------------------------- | |
229 | * Definitions for initial stack pointer and data area (in DPRAM) | |
230 | */ | |
231 | #define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 | |
232 | /* End of used area in internal SRAM */ | |
233 | #define CONFIG_SYS_INIT_RAM_SIZE 0x10000 | |
234 | #define CONFIG_SYS_INIT_RAM_CTRL 0x221 | |
186fc4db | 235 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - \ |
627b73e2 | 236 | GENERATED_GBL_DATA_SIZE) - 32) |
186fc4db AW |
237 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
238 | #define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) | |
239 | ||
240 | /*----------------------------------------------------------------------- | |
241 | * Start addresses for the final memory configuration | |
242 | * (Set up by the startup code) | |
243 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 | |
244 | */ | |
245 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 | |
246 | #define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */ | |
247 | ||
248 | #define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE + 0x400) | |
249 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
250 | #define CONFIG_SYS_DRAM_TEST | |
251 | ||
252 | #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT) | |
253 | #define CONFIG_SERIAL_BOOT | |
254 | #endif | |
255 | ||
256 | #if defined(CONFIG_SERIAL_BOOT) | |
61a4392a | 257 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) |
186fc4db AW |
258 | #else |
259 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) | |
260 | #endif | |
261 | ||
262 | #define CONFIG_SYS_BOOTPARAMS_LEN (64 * 1024) | |
263 | /* Reserve 256 kB for Monitor */ | |
264 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
265 | /* Reserve 256 kB for malloc() */ | |
266 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
267 | ||
268 | /* | |
269 | * For booting Linux, the board info and command line data | |
270 | * have to be in the first 8 MB of memory, since this is | |
271 | * the maximum mapped by the Linux kernel during initialization ?? | |
272 | */ | |
273 | /* Initial Memory map for Linux */ | |
274 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + \ | |
275 | (CONFIG_SYS_SDRAM_SIZE << 20)) | |
276 | ||
277 | /* Configuration for environment | |
278 | * Environment is embedded in u-boot in the second sector of the flash | |
279 | */ | |
280 | #if !defined(CONFIG_SERIAL_BOOT) /*MRAM boot*/ | |
281 | #define CONFIG_SYS_NO_FLASH | |
282 | #define CONFIG_ENV_IS_IN_MRAM 1 | |
283 | #define CONFIG_ENV_ADDR (0x40000 - 0x1000) /*MRAM size 40000*/ | |
284 | #define CONFIG_ENV_SIZE 0x1000 | |
285 | #endif | |
286 | ||
287 | #if defined(CONFIG_CF_SBF) | |
288 | #define CONFIG_SYS_NO_FLASH | |
289 | #define CONFIG_ENV_IS_IN_SPI_FLASH 1 | |
290 | #define CONFIG_ENV_SPI_CS 1 | |
291 | #define CONFIG_ENV_OFFSET 0x40000 | |
292 | #define CONFIG_ENV_SIZE 0x2000 | |
293 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
294 | #endif | |
295 | #if defined(CONFIG_SYS_NAND_BOOT) | |
296 | #define CONFIG_SYS_NO_FLASH | |
b765fce9 | 297 | #define CONFIG_ENV_IS_NOWHERE |
186fc4db AW |
298 | #define CONFIG_ENV_OFFSET 0x80000 |
299 | #define CONFIG_ENV_SIZE 0x20000 | |
300 | #define CONFIG_ENV_SECT_SIZE 0x20000 | |
301 | #endif | |
302 | #undef CONFIG_ENV_OVERWRITE | |
303 | ||
304 | /* FLASH organization */ | |
305 | #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE | |
306 | ||
307 | #undef CONFIG_SYS_FLASH_CFI | |
308 | #ifdef CONFIG_SYS_FLASH_CFI | |
309 | ||
310 | #define CONFIG_FLASH_CFI_DRIVER 1 | |
311 | /* Max size that the board might have */ | |
312 | #define CONFIG_SYS_FLASH_SIZE 0x1000000 | |
313 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
314 | /* max number of memory banks */ | |
315 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
316 | /* max number of sectors on one chip */ | |
317 | #define CONFIG_SYS_MAX_FLASH_SECT 270 | |
318 | /* "Real" (hardware) sectors protection */ | |
319 | #define CONFIG_SYS_FLASH_PROTECTION | |
320 | #define CONFIG_SYS_FLASH_CHECKSUM | |
321 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } | |
322 | #else | |
323 | /* max number of sectors on one chip */ | |
324 | #define CONFIG_SYS_MAX_FLASH_SECT 270 | |
325 | /* max number of sectors on one chip */ | |
326 | #define CONFIG_SYS_MAX_FLASH_BANKS 0 | |
327 | #endif | |
328 | ||
329 | /* | |
330 | * This is setting for JFFS2 support in u-boot. | |
331 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
332 | */ | |
333 | #ifdef CONFIG_CMD_JFFS2 | |
334 | #define CONFIG_JFFS2_DEV "nand0" | |
335 | #define CONFIG_JFFS2_PART_OFFSET (0x800000) | |
336 | #define CONFIG_CMD_MTDPARTS | |
337 | #define CONFIG_MTD_DEVICE | |
338 | #define MTDIDS_DEFAULT "nand0=m54418twr.nand" | |
339 | ||
340 | #define MTDPARTS_DEFAULT "mtdparts=m54418twr.nand:1m(data)," \ | |
341 | "7m(kernel)," \ | |
342 | "-(rootfs)" | |
343 | ||
344 | #endif | |
345 | ||
346 | #ifdef CONFIG_CMD_UBI | |
347 | #define CONFIG_CMD_MTDPARTS | |
348 | #define CONFIG_MTD_DEVICE /* needed for mtdparts command */ | |
349 | #define CONFIG_MTD_PARTITIONS /* mtdparts and UBI support */ | |
350 | #define CONFIG_RBTREE | |
351 | #define MTDIDS_DEFAULT "nand0=NAND" | |
352 | #define MTDPARTS_DEFAULT "mtdparts=NAND:1m(u-boot)," \ | |
353 | "-(ubi)" | |
354 | #endif | |
355 | /* Cache Configuration */ | |
356 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
357 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
358 | CONFIG_SYS_INIT_RAM_SIZE - 8) | |
359 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
360 | CONFIG_SYS_INIT_RAM_SIZE - 4) | |
361 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA) | |
362 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
363 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
364 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
365 | CF_ACR_EN | CF_ACR_SM_ALL) | |
366 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \ | |
367 | CF_CACR_ICINVA | CF_CACR_EUSP) | |
368 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
369 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
370 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
371 | ||
372 | #define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ | |
373 | CONFIG_SYS_INIT_RAM_SIZE - 12) | |
374 | ||
375 | /*----------------------------------------------------------------------- | |
376 | * Memory bank definitions | |
377 | */ | |
378 | /* | |
379 | * CS0 - NOR Flash 16MB | |
380 | * CS1 - Available | |
381 | * CS2 - Available | |
382 | * CS3 - Available | |
383 | * CS4 - Available | |
384 | * CS5 - Available | |
385 | */ | |
386 | ||
387 | /* Flash */ | |
388 | #define CONFIG_SYS_CS0_BASE 0x00000000 | |
389 | #define CONFIG_SYS_CS0_MASK 0x000F0101 | |
390 | #define CONFIG_SYS_CS0_CTRL 0x00001D60 | |
391 | ||
392 | #endif /* _M54418TWR_H */ |