[people/ms/u-boot.git] / include / configs / M54451EVB.h

/*
 * Configuation settings for the Freescale MCF54451 EVB board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54451EVB_H
#define _M54451EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M54451EVB	/* M54451EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#define CONFIG_CMD_REGINFO

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000

#	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54451EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 1000000 3;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#else
#define CONFIG_SYS_UBOOT_END	0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END)	\
	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI

#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM			2048	/* 2048 KB */

#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR			0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
#define CONFIG_SYS_SDRAM_CFG2		0x57670000
#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
#define CONFIG_SYS_SDRAM_EMOD		0x80810000
#define CONFIG_SYS_SDRAM_MODE		0x008D0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SERIAL_BOOT
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/* Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#if defined(CONFIG_SYS_STMICRO_BOOT)
#	define CONFIG_ENV_IS_IN_SPI_FLASH	1
#	define CONFIG_ENV_SPI_CS		1
#	define CONFIG_ENV_OFFSET		0x20000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x20000
#endif
#undef CONFIG_ENV_OVERWRITE

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }

#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 16MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

 /* Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00004D80

#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE

#endif				/* _M54451EVB_H */
Commit	Line	Data
05316f8e TL	1	/*
	2	* Configuation settings for the Freescale MCF54451 EVB board.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
05316f8e TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M54451EVB_H
	15	#define _M54451EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
05316f8e TL	21	#define CONFIG_M54451EVB /* M54451EVB board */
	22
	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
05316f8e TL	25
	26	#undef CONFIG_WATCHDOG
	27
	28	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	29
	30	/*
	31	* BOOTP options
	32	*/
	33	#define CONFIG_BOOTP_BOOTFILESIZE
	34	#define CONFIG_BOOTP_BOOTPATH
	35	#define CONFIG_BOOTP_GATEWAY
	36	#define CONFIG_BOOTP_HOSTNAME
	37
	38	/* Command line configuration */
05316f8e	39	#define CONFIG_CMD_REGINFO
05316f8e TL	40
	41	/* Network configuration */
	42	#define CONFIG_MCFFEC
	43	#ifdef CONFIG_MCFFEC
05316f8e TL	44	# define CONFIG_MII 1
05316f8e TL	45	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	46	# define CONFIG_SYS_DISCOVER_PHY
	47	# define CONFIG_SYS_RX_ETH_BUFFER 8
	48	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	49
6d0f6bcf JCPV	50	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	51	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
05316f8e TL	52	# define MCFFEC_TOUT_LOOP 50000
05316f8e TL	53
052c0891	54	# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
05316f8e TL	55	# define CONFIG_ETHPRIME "FEC0"
	56	# define CONFIG_IPADDR 192.162.1.2
	57	# define CONFIG_NETMASK 255.255.255.0
	58	# define CONFIG_SERVERIP 192.162.1.1
	59	# define CONFIG_GATEWAYIP 192.162.1.1
05316f8e	60
6d0f6bcf JCPV	61	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	62	# ifndef CONFIG_SYS_DISCOVER_PHY
05316f8e TL	63	# define FECDUPLEX FULL
	64	# define FECSPEED _100BASET
	65	# else
6d0f6bcf JCPV	66	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	67	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	68	# endif
6d0f6bcf	69	# endif /* CONFIG_SYS_DISCOVER_PHY */
05316f8e TL	70	#endif
	71
	72	#define CONFIG_HOSTNAME M54451EVB
6d0f6bcf	73	#ifdef CONFIG_SYS_STMICRO_BOOT
05316f8e	74	/* ST Micro serial flash */
6d0f6bcf	75	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
05316f8e TL	76	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	77	"netdev=eth0\0" \
5368c55d	78	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	79	"loadaddr=0x40010000\0" \
	80	"sbfhdr=sbfhdr.bin\0" \
	81	"uboot=u-boot.bin\0" \
	82	"load=tftp ${loadaddr} ${sbfhdr};" \
5368c55d	83	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
05316f8e	84	"upd=run load; run prog\0" \
09933fb0	85	"prog=sf probe 0:1 1000000 3;" \
05316f8e TL	86	"sf erase 0 30000;" \
	87	"sf write ${loadaddr} 0 30000;" \
	88	"save\0" \
	89	""
	90	#else
6d0f6bcf	91	#define CONFIG_SYS_UBOOT_END 0x3FFFF
05316f8e TL	92	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	93	"netdev=eth0\0" \
5368c55d	94	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	95	"loadaddr=40010000\0" \
	96	"u-boot=u-boot.bin\0" \
	97	"load=tftp ${loadaddr) ${u-boot}\0" \
	98	"upd=run load; run prog\0" \
5368c55d MV	99	"prog=prot off 0 " __stringify(CONFIG_SYS_UBOOT_END) \
5368c55d MV	100	"; era 0 " __stringify(CONFIG_SYS_UBOOT_END) " ;" \
05316f8e TL	101	"cp.b ${loadaddr} 0 ${filesize};" \
	102	"save\0" \
	103	""
	104	#endif
	105
	106	/* Realtime clock */
	107	#define CONFIG_MCFRTC
	108	#undef RTC_DEBUG
6d0f6bcf	109	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
05316f8e TL	110
	111	/* Timer */
	112	#define CONFIG_MCFTMR
	113	#undef CONFIG_MCFPIT
	114
	115	/* I2c */
00f792e0 HS	116	#define CONFIG_SYS_I2C
	117	#define CONFIG_SYS_I2C_FSL
	118	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	119	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	120	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
709b384b	121	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
05316f8e TL	122
05316f8e TL	123	/* DSPI and Serial Flash */
ee0a8462	124	#define CONFIG_CF_SPI
05316f8e TL	125	#define CONFIG_CF_DSPI
	126	#define CONFIG_SERIAL_FLASH
	127	#define CONFIG_HARD_SPI
6d0f6bcf	128	#define CONFIG_SYS_SBFHDR_SIZE 0x7
05316f8e	129	#ifdef CONFIG_CMD_SPI
05316f8e	130
ee0a8462 TL	131	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	132	DSPI_CTAR_PCSSCK_1CLK \| \
	133	DSPI_CTAR_PASC(0) \| \
	134	DSPI_CTAR_PDT(0) \| \
	135	DSPI_CTAR_CSSCK(0) \| \
	136	DSPI_CTAR_ASC(0) \| \
	137	DSPI_CTAR_DT(1))
	138	# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
	139	# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
05316f8e TL	140	#endif
	141
	142	/* Input, PCI, Flexbus, and VCO */
	143	#define CONFIG_EXTRA_CLOCK
	144
709b384b	145	#define CONFIG_PRAM 2048 /* 2048 KB */
05316f8e	146
6d0f6bcf	147	#define CONFIG_SYS_LONGHELP /* undef to save memory */
05316f8e TL	148
05316f8e TL	149	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	150	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
05316f8e	151	#else
6d0f6bcf	152	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
05316f8e	153	#endif
6d0f6bcf JCPV	154	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	155	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	156	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
05316f8e	157
6d0f6bcf	158	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
05316f8e	159
709b384b	160	#define CONFIG_SYS_MBAR 0xFC000000
05316f8e TL	161
	162	/*
	163	* Low Level Configuration Settings
	164	* (address mappings, register initial values, etc.)
	165	* You should know what you are doing if you make changes here.
	166	*/
	167
	168	/*-----------------------------------------------------------------------
	169	* Definitions for initial stack pointer and data area (in DPRAM)
	170	*/
6d0f6bcf	171	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	172	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	173	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	174	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
6d0f6bcf	175	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
553f0982	176	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
05316f8e TL	177
	178	/*-----------------------------------------------------------------------
	179	* Start addresses for the final memory configuration
	180	* (Set up by the startup code)
6d0f6bcf	181	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
05316f8e	182	*/
6d0f6bcf JCPV	183	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	184	#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
	185	#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
	186	#define CONFIG_SYS_SDRAM_CFG2 0x57670000
	187	#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
	188	#define CONFIG_SYS_SDRAM_EMOD 0x80810000
	189	#define CONFIG_SYS_SDRAM_MODE 0x008D0000
	190	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
	191
	192	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	193	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
05316f8e TL	194
05316f8e TL	195	#ifdef CONFIG_CF_SBF
09933fb0	196	# define CONFIG_SERIAL_BOOT
14d0a02a	197	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
05316f8e	198	#else
6d0f6bcf	199	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
05316f8e	200	#endif
6d0f6bcf JCPV	201	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	202	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
05316f8e	203
09933fb0 JJ	204	/* Reserve 256 kB for malloc() */
09933fb0 JJ	205	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
05316f8e TL	206	/*
	207	* For booting Linux, the board info and command line data
	208	* have to be in the first 8 MB of memory, since this is
	209	* the maximum mapped by the Linux kernel during initialization ??
	210	*/
	211	/* Initial Memory map for Linux */
6d0f6bcf	212	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
05316f8e TL	213
05316f8e TL	214	/* Configuration for environment
09933fb0 JJ	215	* Environment is not embedded in u-boot. First time runing may have env
09933fb0 JJ	216	* crc error warning if there is no correct environment on the flash.
05316f8e	217	*/
709b384b	218	#if defined(CONFIG_SYS_STMICRO_BOOT)
0b5099a8	219	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
0e8d1586 JCPV	220	# define CONFIG_ENV_SPI_CS 1
	221	# define CONFIG_ENV_OFFSET 0x20000
	222	# define CONFIG_ENV_SIZE 0x2000
	223	# define CONFIG_ENV_SECT_SIZE 0x10000
05316f8e	224	#else
5a1aceb0	225	# define CONFIG_ENV_IS_IN_FLASH 1
09933fb0	226	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
709b384b	227	# define CONFIG_ENV_SIZE 0x2000
09933fb0	228	# define CONFIG_ENV_SECT_SIZE 0x20000
05316f8e TL	229	#endif
05316f8e TL	230	#undef CONFIG_ENV_OVERWRITE
05316f8e	231
ee0a8462 TL	232	/* FLASH organization */
ee0a8462 TL	233	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
05316f8e	234
6d0f6bcf JCPV	235	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	236	#ifdef CONFIG_SYS_FLASH_CFI
05316f8e TL	237
05316f8e TL	238	# define CONFIG_FLASH_CFI_DRIVER 1
709b384b	239	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
6d0f6bcf JCPV	240	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	241	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	242	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	243	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	244	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	245	# define CONFIG_SYS_FLASH_CHECKSUM
	246	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
05316f8e TL	247
	248	#endif
	249
	250	/*
	251	* This is setting for JFFS2 support in u-boot.
	252	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	253	*/
709b384b	254	#ifdef CONFIG_CMD_JFFS2
05316f8e TL	255	# define CONFIG_JFFS2_DEV "nor0"
05316f8e TL	256	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	257	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
05316f8e TL	258	#endif
05316f8e TL	259
709b384b	260	/* Cache Configuration */
6d0f6bcf	261	#define CONFIG_SYS_CACHELINE_SIZE 16
05316f8e	262
dd9f054e	263	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	264	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	265	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	266	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	267	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	268	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	269	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	270	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	271	CF_ACR_EN \| CF_ACR_SM_ALL)
	272	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	273	CF_CACR_ICINVA \| CF_CACR_EUSP)
	274	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	275	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	276	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	277
05316f8e TL	278	/*-----------------------------------------------------------------------
	279	* Memory bank definitions
	280	*/
	281	/*
709b384b	282	* CS0 - NOR Flash 16MB
05316f8e TL	283	* CS1 - Available
	284	* CS2 - Available
	285	* CS3 - Available
	286	* CS4 - Available
	287	* CS5 - Available
	288	*/
	289
709b384b	290	/* Flash */
6d0f6bcf	291	#define CONFIG_SYS_CS0_BASE 0x00000000
709b384b TL	292	#define CONFIG_SYS_CS0_MASK 0x00FF0001
709b384b TL	293	#define CONFIG_SYS_CS0_CTRL 0x00004D80
05316f8e	294
6d0f6bcf	295	#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
05316f8e TL	296
05316f8e TL	297	#endif /* _M54451EVB_H */