[people/ms/u-boot.git] / include / configs / M54451EVB.h

/*
 * Configuation settings for the Freescale MCF54451 EVB board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54451EVB_H
#define _M54451EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MCF5445x		/* define processor family */
#define CONFIG_M54451		/* define processor type */
#define CONFIG_M54451EVB	/* M54451EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)
#define CONFIG_BAUDRATE		115200
#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600 , 19200 , 38400 , 57600, 115200 }

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Command line configuration */
#include <config_cmd_default.h>

#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_ELF
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_I2C
#undef CONFIG_CMD_JFFS2
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_MISC
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_REGINFO
#define CONFIG_CMD_SPI
#define CONFIG_CMD_SF

#undef CONFIG_CMD_LOADB
#undef CONFIG_CMD_LOADS

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_NET_MULTI		1
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000

#	define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds */
#	define CONFIG_BOOTARGS		"root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
#	define CONFIG_ETHADDR		00:e0:0c:bc:e5:60
#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1
#	define CONFIG_OVERWRITE_ETHADDR_ONCE

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54451EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010007
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 10000 1;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 30000;"		\
	"save\0"				\
	""
#else
#define CONFIG_SYS_UBOOT_END	0x3FFFF
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=40010000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END)	\
	"; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;"	\
	"cp.b ${loadaddr} 0 ${filesize};"	\
	"save\0"				\
	""
#endif

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#undef	CONFIG_SOFT_I2C		/* I2C bit-banged               */
#define CONFIG_SYS_I2C_SPEED		80000	/* I2C speed and slave address  */
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_OFFSET		0x58000
#define CONFIG_SYS_IMMR			CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_SPI
#define CONFIG_CF_DSPI
#define CONFIG_SERIAL_FLASH
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x7
#ifdef CONFIG_CMD_SPI
#	define CONFIG_SPI_FLASH
#	define CONFIG_SPI_FLASH_STMICRO

#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
#endif

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM			2048	/* 2048 KB */

#define CONFIG_SYS_PROMPT		"-> "
#define CONFIG_SYS_LONGHELP		/* undef to save memory */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE			1024	/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE			256	/* Console I/O Buffer Size */
#endif
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size    */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_HZ			1000

#define CONFIG_SYS_MBAR			0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_END	0x8000	/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_SIZE	256	/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x33633F30
#define CONFIG_SYS_SDRAM_CFG2		0x57670000
#define CONFIG_SYS_SDRAM_CTRL		0xE20D2C00
#define CONFIG_SYS_SDRAM_EMOD		0x80810000
#define CONFIG_SYS_SDRAM_MODE		0x008D0000
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0x44

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SYS_MONITOR_BASE	(TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */
#define CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc() */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/* Configuration for environment
 * Environment is embedded in u-boot in the second sector of the flash
 */
#if defined(CONFIG_SYS_STMICRO_BOOT)
#	define CONFIG_ENV_IS_IN_SPI_FLASH	1
#	define CONFIG_ENV_SPI_CS		1
#	define CONFIG_ENV_OFFSET		0x20000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#else
#	define CONFIG_ENV_IS_IN_FLASH	1
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x8000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x8000
#endif
#undef CONFIG_ENV_OVERWRITE

/* FLASH organization */
#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }

#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif

/* Cache Configuration */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_END - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_END - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 16MB
 * CS1 - Available
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */

 /* Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x00FF0001
#define CONFIG_SYS_CS0_CTRL		0x00004D80

#define CONFIG_SYS_SPANSION_BASE	CONFIG_SYS_CS0_BASE

#endif				/* _M54451EVB_H */
Commit	Line	Data
05316f8e TL	1	/*
	2	* Configuation settings for the Freescale MCF54451 EVB board.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	/*
	27	* board/config.h - configuration options, board specific
	28	*/
	29
	30	#ifndef _M54451EVB_H
	31	#define _M54451EVB_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37	#define CONFIG_MCF5445x /* define processor family */
	38	#define CONFIG_M54451 /* define processor type */
	39	#define CONFIG_M54451EVB /* M54451EVB board */
	40
	41	#define CONFIG_MCFUART
6d0f6bcf	42	#define CONFIG_SYS_UART_PORT (0)
05316f8e	43	#define CONFIG_BAUDRATE 115200
6d0f6bcf	44	#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
05316f8e TL	45
	46	#undef CONFIG_WATCHDOG
	47
	48	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	49
	50	/*
	51	* BOOTP options
	52	*/
	53	#define CONFIG_BOOTP_BOOTFILESIZE
	54	#define CONFIG_BOOTP_BOOTPATH
	55	#define CONFIG_BOOTP_GATEWAY
	56	#define CONFIG_BOOTP_HOSTNAME
	57
	58	/* Command line configuration */
	59	#include <config_cmd_default.h>
	60
	61	#define CONFIG_CMD_BOOTD
	62	#define CONFIG_CMD_CACHE
	63	#define CONFIG_CMD_DATE
	64	#define CONFIG_CMD_DHCP
	65	#define CONFIG_CMD_ELF
	66	#define CONFIG_CMD_FLASH
	67	#define CONFIG_CMD_I2C
	68	#undef CONFIG_CMD_JFFS2
	69	#define CONFIG_CMD_MEMORY
	70	#define CONFIG_CMD_MISC
	71	#define CONFIG_CMD_MII
	72	#define CONFIG_CMD_NET
709b384b	73	#define CONFIG_CMD_NFS
05316f8e TL	74	#define CONFIG_CMD_PING
	75	#define CONFIG_CMD_REGINFO
	76	#define CONFIG_CMD_SPI
	77	#define CONFIG_CMD_SF
	78
	79	#undef CONFIG_CMD_LOADB
	80	#undef CONFIG_CMD_LOADS
	81
	82	/* Network configuration */
	83	#define CONFIG_MCFFEC
	84	#ifdef CONFIG_MCFFEC
	85	# define CONFIG_NET_MULTI 1
	86	# define CONFIG_MII 1
	87	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	88	# define CONFIG_SYS_DISCOVER_PHY
	89	# define CONFIG_SYS_RX_ETH_BUFFER 8
	90	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	91
6d0f6bcf JCPV	92	# define CONFIG_SYS_FEC0_PINMUX 0
6d0f6bcf JCPV	93	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
05316f8e TL	94	# define MCFFEC_TOUT_LOOP 50000
	95
	96	# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
052c0891	97	# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:2M(kernel)ro,-(jffs2)"
05316f8e TL	98	# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
	99	# define CONFIG_ETHPRIME "FEC0"
	100	# define CONFIG_IPADDR 192.162.1.2
	101	# define CONFIG_NETMASK 255.255.255.0
	102	# define CONFIG_SERVERIP 192.162.1.1
	103	# define CONFIG_GATEWAYIP 192.162.1.1
	104	# define CONFIG_OVERWRITE_ETHADDR_ONCE
	105
6d0f6bcf JCPV	106	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	107	# ifndef CONFIG_SYS_DISCOVER_PHY
05316f8e TL	108	# define FECDUPLEX FULL
	109	# define FECSPEED _100BASET
	110	# else
6d0f6bcf JCPV	111	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	112	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
05316f8e	113	# endif
6d0f6bcf	114	# endif /* CONFIG_SYS_DISCOVER_PHY */
05316f8e TL	115	#endif
	116
	117	#define CONFIG_HOSTNAME M54451EVB
6d0f6bcf	118	#ifdef CONFIG_SYS_STMICRO_BOOT
05316f8e	119	/* ST Micro serial flash */
6d0f6bcf	120	#define CONFIG_SYS_LOAD_ADDR2 0x40010007
05316f8e TL	121	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	122	"netdev=eth0\0" \
6d0f6bcf	123	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	124	"loadaddr=0x40010000\0" \
	125	"sbfhdr=sbfhdr.bin\0" \
	126	"uboot=u-boot.bin\0" \
	127	"load=tftp ${loadaddr} ${sbfhdr};" \
6d0f6bcf	128	"tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
05316f8e TL	129	"upd=run load; run prog\0" \
	130	"prog=sf probe 0:1 10000 1;" \
	131	"sf erase 0 30000;" \
	132	"sf write ${loadaddr} 0 30000;" \
	133	"save\0" \
	134	""
	135	#else
6d0f6bcf	136	#define CONFIG_SYS_UBOOT_END 0x3FFFF
05316f8e TL	137	#define CONFIG_EXTRA_ENV_SETTINGS \
05316f8e TL	138	"netdev=eth0\0" \
6d0f6bcf	139	"inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
05316f8e TL	140	"loadaddr=40010000\0" \
	141	"u-boot=u-boot.bin\0" \
	142	"load=tftp ${loadaddr) ${u-boot}\0" \
	143	"upd=run load; run prog\0" \
6d0f6bcf JCPV	144	"prog=prot off 0 " MK_STR(CONFIG_SYS_UBOOT_END) \
6d0f6bcf JCPV	145	"; era 0 " MK_STR(CONFIG_SYS_UBOOT_END) " ;" \
05316f8e TL	146	"cp.b ${loadaddr} 0 ${filesize};" \
	147	"save\0" \
	148	""
	149	#endif
	150
	151	/* Realtime clock */
	152	#define CONFIG_MCFRTC
	153	#undef RTC_DEBUG
6d0f6bcf	154	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
05316f8e TL	155
	156	/* Timer */
	157	#define CONFIG_MCFTMR
	158	#undef CONFIG_MCFPIT
	159
	160	/* I2c */
	161	#define CONFIG_FSL_I2C
	162	#define CONFIG_HARD_I2C /* I2C with hardware support */
	163	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	164	#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
	165	#define CONFIG_SYS_I2C_SLAVE 0x7F
	166	#define CONFIG_SYS_I2C_OFFSET 0x58000
709b384b	167	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
05316f8e TL	168
05316f8e TL	169	/* DSPI and Serial Flash */
ee0a8462	170	#define CONFIG_CF_SPI
05316f8e TL	171	#define CONFIG_CF_DSPI
	172	#define CONFIG_SERIAL_FLASH
	173	#define CONFIG_HARD_SPI
6d0f6bcf	174	#define CONFIG_SYS_SBFHDR_SIZE 0x7
05316f8e TL	175	#ifdef CONFIG_CMD_SPI
	176	# define CONFIG_SPI_FLASH
	177	# define CONFIG_SPI_FLASH_STMICRO
	178
ee0a8462 TL	179	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	180	DSPI_CTAR_PCSSCK_1CLK \| \
	181	DSPI_CTAR_PASC(0) \| \
	182	DSPI_CTAR_PDT(0) \| \
	183	DSPI_CTAR_CSSCK(0) \| \
	184	DSPI_CTAR_ASC(0) \| \
	185	DSPI_CTAR_DT(1))
	186	# define CONFIG_SYS_DSPI_CTAR1 (CONFIG_SYS_DSPI_CTAR0)
	187	# define CONFIG_SYS_DSPI_CTAR2 (CONFIG_SYS_DSPI_CTAR0)
05316f8e TL	188	#endif
	189
	190	/* Input, PCI, Flexbus, and VCO */
	191	#define CONFIG_EXTRA_CLOCK
	192
709b384b	193	#define CONFIG_PRAM 2048 /* 2048 KB */
05316f8e	194
6d0f6bcf JCPV	195	#define CONFIG_SYS_PROMPT "-> "
6d0f6bcf JCPV	196	#define CONFIG_SYS_LONGHELP /* undef to save memory */
05316f8e TL	197
05316f8e TL	198	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	199	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
05316f8e	200	#else
6d0f6bcf	201	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
05316f8e	202	#endif
6d0f6bcf JCPV	203	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	204	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	205	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
05316f8e	206
6d0f6bcf	207	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
05316f8e	208
6d0f6bcf	209	#define CONFIG_SYS_HZ 1000
05316f8e	210
709b384b	211	#define CONFIG_SYS_MBAR 0xFC000000
05316f8e TL	212
	213	/*
	214	* Low Level Configuration Settings
	215	* (address mappings, register initial values, etc.)
	216	* You should know what you are doing if you make changes here.
	217	*/
	218
	219	/*-----------------------------------------------------------------------
	220	* Definitions for initial stack pointer and data area (in DPRAM)
	221	*/
6d0f6bcf JCPV	222	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
	223	#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
	224	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
	225	#define CONFIG_SYS_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
	226	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
	227	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	228	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
05316f8e TL	229
	230	/*-----------------------------------------------------------------------
	231	* Start addresses for the final memory configuration
	232	* (Set up by the startup code)
6d0f6bcf	233	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
05316f8e	234	*/
6d0f6bcf JCPV	235	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	236	#define CONFIG_SYS_SDRAM_SIZE 128 /* SDRAM size in MB */
	237	#define CONFIG_SYS_SDRAM_CFG1 0x33633F30
	238	#define CONFIG_SYS_SDRAM_CFG2 0x57670000
	239	#define CONFIG_SYS_SDRAM_CTRL 0xE20D2C00
	240	#define CONFIG_SYS_SDRAM_EMOD 0x80810000
	241	#define CONFIG_SYS_SDRAM_MODE 0x008D0000
	242	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x44
	243
	244	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	245	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
05316f8e TL	246
05316f8e TL	247	#ifdef CONFIG_CF_SBF
6d0f6bcf	248	# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
05316f8e	249	#else
6d0f6bcf	250	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
05316f8e	251	#endif
6d0f6bcf JCPV	252	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
	253	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	254	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
05316f8e TL	255
	256	/*
	257	* For booting Linux, the board info and command line data
	258	* have to be in the first 8 MB of memory, since this is
	259	* the maximum mapped by the Linux kernel during initialization ??
	260	*/
	261	/* Initial Memory map for Linux */
6d0f6bcf	262	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
05316f8e TL	263
	264	/* Configuration for environment
	265	* Environment is embedded in u-boot in the second sector of the flash
	266	*/
709b384b	267	#if defined(CONFIG_SYS_STMICRO_BOOT)
0b5099a8	268	# define CONFIG_ENV_IS_IN_SPI_FLASH 1
0e8d1586 JCPV	269	# define CONFIG_ENV_SPI_CS 1
	270	# define CONFIG_ENV_OFFSET 0x20000
	271	# define CONFIG_ENV_SIZE 0x2000
	272	# define CONFIG_ENV_SECT_SIZE 0x10000
05316f8e	273	#else
5a1aceb0	274	# define CONFIG_ENV_IS_IN_FLASH 1
709b384b TL	275	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x8000)
	276	# define CONFIG_ENV_SIZE 0x2000
	277	# define CONFIG_ENV_SECT_SIZE 0x8000
05316f8e TL	278	#endif
05316f8e TL	279	#undef CONFIG_ENV_OVERWRITE
05316f8e	280
ee0a8462 TL	281	/* FLASH organization */
ee0a8462 TL	282	#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
05316f8e	283
6d0f6bcf JCPV	284	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	285	#ifdef CONFIG_SYS_FLASH_CFI
05316f8e TL	286
05316f8e TL	287	# define CONFIG_FLASH_CFI_DRIVER 1
709b384b	288	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
6d0f6bcf JCPV	289	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	290	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	291	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
	292	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	293	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	294	# define CONFIG_SYS_FLASH_CHECKSUM
	295	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE }
05316f8e TL	296
	297	#endif
	298
	299	/*
	300	* This is setting for JFFS2 support in u-boot.
	301	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	302	*/
709b384b	303	#ifdef CONFIG_CMD_JFFS2
05316f8e TL	304	# define CONFIG_JFFS2_DEV "nor0"
05316f8e TL	305	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	306	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
05316f8e TL	307	#endif
05316f8e TL	308
709b384b	309	/* Cache Configuration */
6d0f6bcf	310	#define CONFIG_SYS_CACHELINE_SIZE 16
05316f8e	311
dd9f054e TL	312	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	313	CONFIG_SYS_INIT_RAM_END - 8)
	314	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
	315	CONFIG_SYS_INIT_RAM_END - 4)
	316	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	317	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	318	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	319	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	320	CF_ACR_EN \| CF_ACR_SM_ALL)
	321	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	322	CF_CACR_ICINVA \| CF_CACR_EUSP)
	323	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	324	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	325	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	326
05316f8e TL	327	/*-----------------------------------------------------------------------
	328	* Memory bank definitions
	329	*/
	330	/*
709b384b	331	* CS0 - NOR Flash 16MB
05316f8e TL	332	* CS1 - Available
	333	* CS2 - Available
	334	* CS3 - Available
	335	* CS4 - Available
	336	* CS5 - Available
	337	*/
	338
709b384b	339	/* Flash */
6d0f6bcf	340	#define CONFIG_SYS_CS0_BASE 0x00000000
709b384b TL	341	#define CONFIG_SYS_CS0_MASK 0x00FF0001
709b384b TL	342	#define CONFIG_SYS_CS0_CTRL 0x00004D80
05316f8e	343
6d0f6bcf	344	#define CONFIG_SYS_SPANSION_BASE CONFIG_SYS_CS0_BASE
05316f8e TL	345
05316f8e TL	346	#endif /* _M54451EVB_H */