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8ae158cd TL |
1 | /* |
2 | * Configuation settings for the Freescale MCF54455 EVB board. | |
3 | * | |
4 | * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. | |
5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | /* | |
27 | * board/config.h - configuration options, board specific | |
28 | */ | |
29 | ||
e8ee8f3a TL |
30 | #ifndef _M54455EVB_H |
31 | #define _M54455EVB_H | |
8ae158cd TL |
32 | |
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | #define CONFIG_MCF5445x /* define processor family */ | |
38 | #define CONFIG_M54455 /* define processor type */ | |
39 | #define CONFIG_M54455EVB /* M54455EVB board */ | |
40 | ||
8ae158cd TL |
41 | #define CONFIG_MCFUART |
42 | #define CFG_UART_PORT (0) | |
43 | #define CONFIG_BAUDRATE 115200 | |
44 | #define CFG_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } | |
45 | ||
46 | #undef CONFIG_WATCHDOG | |
47 | ||
48 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
49 | ||
50 | /* | |
51 | * BOOTP options | |
52 | */ | |
53 | #define CONFIG_BOOTP_BOOTFILESIZE | |
54 | #define CONFIG_BOOTP_BOOTPATH | |
55 | #define CONFIG_BOOTP_GATEWAY | |
56 | #define CONFIG_BOOTP_HOSTNAME | |
57 | ||
58 | /* Command line configuration */ | |
59 | #include <config_cmd_default.h> | |
60 | ||
61 | #define CONFIG_CMD_BOOTD | |
62 | #define CONFIG_CMD_CACHE | |
63 | #define CONFIG_CMD_DATE | |
64 | #define CONFIG_CMD_DHCP | |
65 | #define CONFIG_CMD_ELF | |
66 | #define CONFIG_CMD_EXT2 | |
67 | #define CONFIG_CMD_FAT | |
68 | #define CONFIG_CMD_FLASH | |
69 | #define CONFIG_CMD_I2C | |
70 | #define CONFIG_CMD_IDE | |
71 | #define CONFIG_CMD_JFFS2 | |
72 | #define CONFIG_CMD_MEMORY | |
73 | #define CONFIG_CMD_MISC | |
74 | #define CONFIG_CMD_MII | |
75 | #define CONFIG_CMD_NET | |
e8ee8f3a | 76 | #undef CONFIG_CMD_PCI |
8ae158cd TL |
77 | #define CONFIG_CMD_PING |
78 | #define CONFIG_CMD_REGINFO | |
a7323bba | 79 | #define CONFIG_CMD_SPI |
8ae158cd TL |
80 | |
81 | #undef CONFIG_CMD_LOADB | |
82 | #undef CONFIG_CMD_LOADS | |
83 | ||
84 | /* Network configuration */ | |
85 | #define CONFIG_MCFFEC | |
86 | #ifdef CONFIG_MCFFEC | |
0f3ba7e9 | 87 | # define CONFIG_NET_MULTI 1 |
8ae158cd | 88 | # define CONFIG_MII 1 |
0f3ba7e9 | 89 | # define CONFIG_MII_INIT 1 |
8ae158cd TL |
90 | # define CFG_DISCOVER_PHY |
91 | # define CFG_RX_ETH_BUFFER 8 | |
92 | # define CFG_FAULT_ECHO_LINK_DOWN | |
93 | ||
94 | # define CFG_FEC0_PINMUX 0 | |
95 | # define CFG_FEC1_PINMUX 0 | |
96 | # define CFG_FEC0_MIIBASE CFG_FEC0_IOBASE | |
97 | # define CFG_FEC1_MIIBASE CFG_FEC0_IOBASE | |
98 | # define MCFFEC_TOUT_LOOP 50000 | |
99 | # define CONFIG_HAS_ETH1 | |
100 | ||
101 | # define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
102 | # define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)" | |
103 | # define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 | |
104 | # define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61 | |
105 | # define CONFIG_ETHPRIME "FEC0" | |
106 | # define CONFIG_IPADDR 192.162.1.2 | |
107 | # define CONFIG_NETMASK 255.255.255.0 | |
108 | # define CONFIG_SERVERIP 192.162.1.1 | |
109 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
110 | # define CONFIG_OVERWRITE_ETHADDR_ONCE | |
111 | ||
112 | /* If CFG_DISCOVER_PHY is not defined - hardcoded */ | |
113 | # ifndef CFG_DISCOVER_PHY | |
114 | # define FECDUPLEX FULL | |
115 | # define FECSPEED _100BASET | |
116 | # else | |
117 | # ifndef CFG_FAULT_ECHO_LINK_DOWN | |
118 | # define CFG_FAULT_ECHO_LINK_DOWN | |
119 | # endif | |
120 | # endif /* CFG_DISCOVER_PHY */ | |
121 | #endif | |
122 | ||
123 | #define CONFIG_HOSTNAME M54455EVB | |
9f751551 TL |
124 | #ifdef CFG_STMICRO_BOOT |
125 | /* ST Micro serial flash */ | |
126 | #define CFG_LOAD_ADDR2 0x40010013 | |
8ae158cd TL |
127 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
128 | "netdev=eth0\0" \ | |
129 | "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ | |
9f751551 TL |
130 | "loadaddr=0x40010000\0" \ |
131 | "sbfhdr=sbfhdr.bin\0" \ | |
132 | "uboot=u-boot.bin\0" \ | |
133 | "load=tftp ${loadaddr} ${sbfhdr};" \ | |
134 | "tftp " MK_STR(CFG_LOAD_ADDR2) " ${uboot} \0" \ | |
8ae158cd | 135 | "upd=run load; run prog\0" \ |
9f751551 TL |
136 | "prog=sf probe 0:1 10000 1;" \ |
137 | "sf erase 0 30000;" \ | |
138 | "sf write ${loadaddr} 0 0x30000;" \ | |
8ae158cd TL |
139 | "save\0" \ |
140 | "" | |
9f751551 TL |
141 | #else |
142 | /* Atmel and Intel */ | |
143 | #ifdef CFG_ATMEL_BOOT | |
144 | # define CFG_UBOOT_END 0x0403FFFF | |
145 | #elif defined(CFG_INTEL_BOOT) | |
146 | # define CFG_UBOOT_END 0x3FFFF | |
147 | #endif | |
148 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
149 | "netdev=eth0\0" \ | |
150 | "inpclk=" MK_STR(CFG_INPUT_CLKSRC) "\0" \ | |
151 | "loadaddr=0x40010000\0" \ | |
152 | "uboot=u-boot.bin\0" \ | |
153 | "load=tftp ${loadaddr} ${uboot}\0" \ | |
154 | "upd=run load; run prog\0" \ | |
155 | "prog=prot off " MK_STR(CFG_FLASH_BASE) \ | |
156 | " " MK_STR(CFG_UBOOT_END) ";" \ | |
157 | "era " MK_STR(CFG_FLASH_BASE) " " \ | |
158 | MK_STR(CFG_UBOOT_END) ";" \ | |
159 | "cp.b ${loadaddr} " MK_STR(CFG_FLASH_BASE)\ | |
160 | " ${filesize}; save\0" \ | |
161 | "" | |
162 | #endif | |
8ae158cd TL |
163 | |
164 | /* ATA configuration */ | |
165 | #define CONFIG_ISO_PARTITION | |
166 | #define CONFIG_DOS_PARTITION | |
167 | #define CONFIG_IDE_RESET 1 | |
168 | #define CONFIG_IDE_PREINIT 1 | |
169 | #define CONFIG_ATAPI | |
170 | #undef CONFIG_LBA48 | |
171 | ||
172 | #define CFG_IDE_MAXBUS 1 | |
173 | #define CFG_IDE_MAXDEVICE 2 | |
174 | ||
175 | #define CFG_ATA_BASE_ADDR 0x90000000 | |
176 | #define CFG_ATA_IDE0_OFFSET 0 | |
177 | ||
178 | #define CFG_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */ | |
179 | #define CFG_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */ | |
180 | #define CFG_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */ | |
181 | #define CFG_ATA_STRIDE 4 /* Interval between registers */ | |
182 | #define _IO_BASE 0 | |
183 | ||
184 | /* Realtime clock */ | |
185 | #define CONFIG_MCFRTC | |
186 | #undef RTC_DEBUG | |
187 | #define CFG_RTC_OSCILLATOR (32 * CFG_HZ) | |
188 | ||
189 | /* Timer */ | |
190 | #define CONFIG_MCFTMR | |
191 | #undef CONFIG_MCFPIT | |
192 | ||
193 | /* I2c */ | |
194 | #define CONFIG_FSL_I2C | |
195 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
196 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
197 | #define CFG_I2C_SPEED 80000 /* I2C speed and slave address */ | |
198 | #define CFG_I2C_SLAVE 0x7F | |
199 | #define CFG_I2C_OFFSET 0x58000 | |
200 | #define CFG_IMMR CFG_MBAR | |
201 | ||
bae61eef TL |
202 | /* DSPI and Serial Flash */ |
203 | #define CONFIG_CF_DSPI | |
a7323bba | 204 | #define CONFIG_HARD_SPI |
9f751551 TL |
205 | #define CFG_SER_FLASH_BASE 0x01000000 |
206 | #define CFG_SBFHDR_SIZE 0x13 | |
a7323bba TL |
207 | #ifdef CONFIG_CMD_SPI |
208 | # define CFG_DSPI_DCTAR0 (DSPI_DCTAR_TRSZ(7) | \ | |
209 | DSPI_DCTAR_CPOL | \ | |
210 | DSPI_DCTAR_CPHA | \ | |
211 | DSPI_DCTAR_PCSSCK_1CLK | \ | |
212 | DSPI_DCTAR_PASC(0) | \ | |
213 | DSPI_DCTAR_PDT(0) | \ | |
214 | DSPI_DCTAR_CSSCK(0) | \ | |
215 | DSPI_DCTAR_ASC(0) | \ | |
216 | DSPI_DCTAR_PBR(0) | \ | |
217 | DSPI_DCTAR_DT(1) | \ | |
218 | DSPI_DCTAR_BR(1)) | |
219 | #endif | |
bae61eef | 220 | |
8ae158cd | 221 | /* PCI */ |
e8ee8f3a | 222 | #ifdef CONFIG_CMD_PCI |
8ae158cd | 223 | #define CONFIG_PCI 1 |
2e72ad06 | 224 | #define CONFIG_PCI_PNP 1 |
f33fca22 | 225 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
2e72ad06 TL |
226 | |
227 | #define CFG_PCI_CACHE_LINE_SIZE 4 | |
8ae158cd TL |
228 | |
229 | #define CFG_PCI_MEM_BUS 0xA0000000 | |
230 | #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BUS | |
231 | #define CFG_PCI_MEM_SIZE 0x10000000 | |
232 | ||
233 | #define CFG_PCI_IO_BUS 0xB1000000 | |
234 | #define CFG_PCI_IO_PHYS CFG_PCI_IO_BUS | |
235 | #define CFG_PCI_IO_SIZE 0x01000000 | |
236 | ||
237 | #define CFG_PCI_CFG_BUS 0xB0000000 | |
238 | #define CFG_PCI_CFG_PHYS CFG_PCI_CFG_BUS | |
239 | #define CFG_PCI_CFG_SIZE 0x01000000 | |
e8ee8f3a | 240 | #endif |
8ae158cd TL |
241 | |
242 | /* FPGA - Spartan 2 */ | |
243 | /* experiment | |
2e72ad06 | 244 | #define CONFIG_FPGA CFG_SPARTAN3 |
8ae158cd TL |
245 | #define CONFIG_FPGA_COUNT 1 |
246 | #define CFG_FPGA_PROG_FEEDBACK | |
247 | #define CFG_FPGA_CHECK_CTRLC | |
248 | */ | |
249 | ||
250 | /* Input, PCI, Flexbus, and VCO */ | |
251 | #define CONFIG_EXTRA_CLOCK | |
252 | ||
9f751551 | 253 | #define CONFIG_PRAM 2048 /* 2048 KB */ |
8ae158cd TL |
254 | |
255 | #define CFG_PROMPT "-> " | |
256 | #define CFG_LONGHELP /* undef to save memory */ | |
257 | ||
258 | #if defined(CONFIG_CMD_KGDB) | |
259 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
260 | #else | |
261 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
262 | #endif | |
263 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
264 | #define CFG_MAXARGS 16 /* max number of command args */ | |
265 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
266 | ||
267 | #define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x10000) | |
268 | ||
269 | #define CFG_HZ 1000 | |
270 | ||
271 | #define CFG_MBAR 0xFC000000 | |
272 | ||
273 | /* | |
274 | * Low Level Configuration Settings | |
275 | * (address mappings, register initial values, etc.) | |
276 | * You should know what you are doing if you make changes here. | |
277 | */ | |
278 | ||
279 | /*----------------------------------------------------------------------- | |
280 | * Definitions for initial stack pointer and data area (in DPRAM) | |
281 | */ | |
282 | #define CFG_INIT_RAM_ADDR 0x80000000 | |
283 | #define CFG_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */ | |
284 | #define CFG_INIT_RAM_CTRL 0x221 | |
285 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
9f751551 | 286 | #define CFG_GBL_DATA_OFFSET ((CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) - 32) |
8ae158cd | 287 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
9f751551 | 288 | #define CFG_SBFHDR_DATA_OFFSET (CFG_INIT_RAM_END - 32) |
8ae158cd TL |
289 | |
290 | /*----------------------------------------------------------------------- | |
291 | * Start addresses for the final memory configuration | |
292 | * (Set up by the startup code) | |
293 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
294 | */ | |
295 | #define CFG_SDRAM_BASE 0x40000000 | |
296 | #define CFG_SDRAM_BASE1 0x48000000 | |
297 | #define CFG_SDRAM_SIZE 256 /* SDRAM size in MB */ | |
298 | #define CFG_SDRAM_CFG1 0x65311610 | |
299 | #define CFG_SDRAM_CFG2 0x59670000 | |
300 | #define CFG_SDRAM_CTRL 0xEA0B2000 | |
301 | #define CFG_SDRAM_EMOD 0x40010000 | |
302 | #define CFG_SDRAM_MODE 0x00010033 | |
9f751551 | 303 | #define CFG_SDRAM_DRV_STRENGTH 0xAA |
8ae158cd TL |
304 | |
305 | #define CFG_MEMTEST_START CFG_SDRAM_BASE + 0x400 | |
306 | #define CFG_MEMTEST_END ((CFG_SDRAM_SIZE - 3) << 20) | |
307 | ||
9f751551 TL |
308 | #ifdef CONFIG_CF_SBF |
309 | # define CFG_MONITOR_BASE (TEXT_BASE + 0x400) | |
310 | #else | |
311 | # define CFG_MONITOR_BASE (CFG_FLASH_BASE + 0x400) | |
312 | #endif | |
8ae158cd TL |
313 | #define CFG_BOOTPARAMS_LEN 64*1024 |
314 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
315 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
316 | ||
317 | /* | |
318 | * For booting Linux, the board info and command line data | |
319 | * have to be in the first 8 MB of memory, since this is | |
320 | * the maximum mapped by the Linux kernel during initialization ?? | |
321 | */ | |
322 | /* Initial Memory map for Linux */ | |
323 | #define CFG_BOOTMAPSZ (CFG_SDRAM_BASE + (CFG_SDRAM_SIZE << 20)) | |
324 | ||
9f751551 TL |
325 | /* |
326 | * Configuration for environment | |
8ae158cd TL |
327 | * Environment is embedded in u-boot in the second sector of the flash |
328 | */ | |
9f751551 TL |
329 | #ifdef CONFIG_CF_SBF |
330 | # define CFG_ENV_IS_IN_SPI_FLASH | |
331 | # define CFG_ENV_SPI_CS 1 | |
332 | #else | |
333 | # define CFG_ENV_IS_IN_FLASH 1 | |
334 | #endif | |
335 | #undef CONFIG_ENV_OVERWRITE | |
8ae158cd TL |
336 | #undef CFG_ENV_IS_EMBEDDED |
337 | ||
338 | /*----------------------------------------------------------------------- | |
339 | * FLASH organization | |
340 | */ | |
9f751551 TL |
341 | #ifdef CFG_STMICRO_BOOT |
342 | # define CFG_FLASH_BASE CFG_SER_FLASH_BASE | |
343 | # define CFG_FLASH0_BASE CFG_SER_FLASH_BASE | |
344 | # define CFG_FLASH1_BASE CFG_CS0_BASE | |
345 | # define CFG_FLASH2_BASE CFG_CS1_BASE | |
346 | # define CFG_ENV_OFFSET 0x30000 | |
347 | # define CFG_ENV_SIZE 0x2000 | |
348 | # define CFG_ENV_SECT_SIZE 0x10000 | |
349 | #endif | |
8ae158cd | 350 | #ifdef CFG_ATMEL_BOOT |
992742a5 | 351 | # define CFG_FLASH_BASE CFG_CS0_BASE |
8ae158cd TL |
352 | # define CFG_FLASH0_BASE CFG_CS0_BASE |
353 | # define CFG_FLASH1_BASE CFG_CS1_BASE | |
e8ee8f3a TL |
354 | # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x4000) |
355 | # define CFG_ENV_SECT_SIZE 0x2000 | |
9f751551 TL |
356 | #endif |
357 | #ifdef CFG_INTEL_BOOT | |
2e72ad06 TL |
358 | # define CFG_FLASH_BASE CFG_CS0_BASE |
359 | # define CFG_FLASH0_BASE CFG_CS0_BASE | |
360 | # define CFG_FLASH1_BASE CFG_CS1_BASE | |
9f751551 TL |
361 | # define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x40000) |
362 | # define CFG_ENV_SIZE 0x2000 | |
e8ee8f3a | 363 | # define CFG_ENV_SECT_SIZE 0x20000 |
8ae158cd TL |
364 | #endif |
365 | ||
b2d022d1 | 366 | #define CFG_FLASH_CFI |
8ae158cd TL |
367 | #ifdef CFG_FLASH_CFI |
368 | ||
00b1883a | 369 | # define CONFIG_FLASH_CFI_DRIVER 1 |
8ae158cd TL |
370 | # define CFG_FLASH_SIZE 0x1000000 /* Max size that the board might have */ |
371 | # define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT | |
372 | # define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
373 | # define CFG_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
374 | # define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
375 | # define CFG_FLASH_CHECKSUM | |
376 | # define CFG_FLASH_BANKS_LIST { CFG_CS0_BASE, CFG_CS1_BASE } | |
b2d022d1 | 377 | # define CONFIG_FLASH_CFI_LEGACY |
8ae158cd | 378 | |
b2d022d1 | 379 | #ifdef CONFIG_FLASH_CFI_LEGACY |
8ae158cd TL |
380 | # define CFG_ATMEL_REGION 4 |
381 | # define CFG_ATMEL_TOTALSECT 11 | |
382 | # define CFG_ATMEL_SECT {1, 2, 1, 7} | |
383 | # define CFG_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000} | |
bae61eef | 384 | #endif |
8ae158cd TL |
385 | #endif |
386 | ||
b2d022d1 TL |
387 | #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
388 | #define CFG_FLASH_CHECKSUM | |
389 | ||
8ae158cd TL |
390 | /* |
391 | * This is setting for JFFS2 support in u-boot. | |
392 | * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. | |
393 | */ | |
9f751551 TL |
394 | #ifdef CONFIG_CMD_JFFS2 |
395 | #ifdef CF_STMICRO_BOOT | |
396 | # define CONFIG_JFFS2_DEV "nor1" | |
397 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 | |
398 | # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH2_BASE + 0x500000) | |
399 | #endif | |
8ae158cd | 400 | #ifdef CFG_ATMEL_BOOT |
e8ee8f3a | 401 | # define CONFIG_JFFS2_DEV "nor1" |
8ae158cd | 402 | # define CONFIG_JFFS2_PART_SIZE 0x01000000 |
e8ee8f3a | 403 | # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH1_BASE + 0x500000) |
9f751551 TL |
404 | #endif |
405 | #ifdef CFG_INTEL_BOOT | |
8ae158cd TL |
406 | # define CONFIG_JFFS2_DEV "nor0" |
407 | # define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000) | |
408 | # define CONFIG_JFFS2_PART_OFFSET (CFG_FLASH0_BASE + 0x500000) | |
409 | #endif | |
9f751551 | 410 | #endif |
8ae158cd TL |
411 | |
412 | /*----------------------------------------------------------------------- | |
413 | * Cache Configuration | |
414 | */ | |
415 | #define CFG_CACHELINE_SIZE 16 | |
416 | ||
417 | /*----------------------------------------------------------------------- | |
418 | * Memory bank definitions | |
419 | */ | |
420 | /* | |
421 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
422 | * CS1 - CompactFlash and registers | |
423 | * CS2 - CPLD | |
424 | * CS3 - FPGA | |
425 | * CS4 - Available | |
426 | * CS5 - Available | |
427 | */ | |
428 | ||
9f751551 | 429 | #if defined(CFG_ATMEL_BOOT) || defined(CFG_STMICRO_BOOT) |
8ae158cd | 430 | /* Atmel Flash */ |
e8ee8f3a | 431 | #define CFG_CS0_BASE 0x04000000 |
8ae158cd TL |
432 | #define CFG_CS0_MASK 0x00070001 |
433 | #define CFG_CS0_CTRL 0x00001140 | |
434 | /* Intel Flash */ | |
e8ee8f3a | 435 | #define CFG_CS1_BASE 0x00000000 |
8ae158cd | 436 | #define CFG_CS1_MASK 0x01FF0001 |
e8ee8f3a | 437 | #define CFG_CS1_CTRL 0x00000D60 |
8ae158cd TL |
438 | |
439 | #define CFG_ATMEL_BASE CFG_CS0_BASE | |
440 | #else | |
441 | /* Intel Flash */ | |
e8ee8f3a | 442 | #define CFG_CS0_BASE 0x00000000 |
8ae158cd | 443 | #define CFG_CS0_MASK 0x01FF0001 |
e8ee8f3a | 444 | #define CFG_CS0_CTRL 0x00000D60 |
8ae158cd TL |
445 | /* Atmel Flash */ |
446 | #define CFG_CS1_BASE 0x04000000 | |
447 | #define CFG_CS1_MASK 0x00070001 | |
448 | #define CFG_CS1_CTRL 0x00001140 | |
449 | ||
450 | #define CFG_ATMEL_BASE CFG_CS1_BASE | |
451 | #endif | |
452 | ||
453 | /* CPLD */ | |
454 | #define CFG_CS2_BASE 0x08000000 | |
455 | #define CFG_CS2_MASK 0x00070001 | |
456 | #define CFG_CS2_CTRL 0x003f1140 | |
457 | ||
458 | /* FPGA */ | |
459 | #define CFG_CS3_BASE 0x09000000 | |
460 | #define CFG_CS3_MASK 0x00070001 | |
461 | #define CFG_CS3_CTRL 0x00000020 | |
462 | ||
e8ee8f3a | 463 | #endif /* _M54455EVB_H */ |