[people/ms/u-boot.git] / include / configs / M54455EVB.h

/*
 * Configuation settings for the Freescale MCF54455 EVB board.
 *
 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M54455EVB_H
#define _M54455EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_M54455EVB	/* M54455EVB board */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#define LDS_BOARD_TEXT                  board/freescale/m54455evb/sbf_dram_init.o (.text*)

#undef CONFIG_WATCHDOG

#define CONFIG_TIMESTAMP	/* Print image info with timestamp */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/* Network configuration */
#define CONFIG_MCFFEC
#ifdef CONFIG_MCFFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	8
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX	0
#	define CONFIG_SYS_FEC1_PINMUX	0
#	define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_IOBASE
#	define MCFFEC_TOUT_LOOP 50000
#	define CONFIG_HAS_ETH1

#	define CONFIG_ETHPRIME		"FEC0"
#	define CONFIG_IPADDR		192.162.1.2
#	define CONFIG_NETMASK		255.255.255.0
#	define CONFIG_SERVERIP		192.162.1.1
#	define CONFIG_GATEWAYIP		192.162.1.1

/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */
#endif

#define CONFIG_HOSTNAME		M54455EVB
#ifdef CONFIG_SYS_STMICRO_BOOT
/* ST Micro serial flash */
#define	CONFIG_SYS_LOAD_ADDR2		0x40010013
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"sbfhdr=sbfhdr.bin\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${sbfhdr};"	\
	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0"	\
	"upd=run load; run prog\0"		\
	"prog=sf probe 0:1 1000000 3;"		\
	"sf erase 0 30000;"			\
	"sf write ${loadaddr} 0 0x30000;"	\
	"save\0"				\
	""
#else
/* Atmel and Intel */
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_UBOOT_END	0x0403FFFF
#elif defined(CONFIG_SYS_INTEL_BOOT)
#	define CONFIG_SYS_UBOOT_END	0x3FFFF
#endif
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0"	\
	"loadaddr=0x40010000\0"			\
	"uboot=u-boot.bin\0"			\
	"load=tftp ${loadaddr} ${uboot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" " __stringify(CONFIG_SYS_UBOOT_END) ";"		\
	"era " __stringify(CONFIG_SYS_FLASH_BASE) " "		\
	__stringify(CONFIG_SYS_UBOOT_END) ";"			\
	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE)	\
	" ${filesize}; save\0"			\
	""
#endif

/* ATA configuration */
#define CONFIG_IDE_RESET	1
#define CONFIG_IDE_PREINIT	1
#define CONFIG_ATAPI
#undef CONFIG_LBA48

#define CONFIG_SYS_IDE_MAXBUS		1
#define CONFIG_SYS_IDE_MAXDEVICE	2

#define CONFIG_SYS_ATA_BASE_ADDR	0x90000000
#define CONFIG_SYS_ATA_IDE0_OFFSET	0

#define CONFIG_SYS_ATA_DATA_OFFSET	0xA0	/* Offset for data I/O                            */
#define CONFIG_SYS_ATA_REG_OFFSET	0xA0	/* Offset for normal register accesses */
#define CONFIG_SYS_ATA_ALT_OFFSET	0xC0	/* Offset for alternate registers           */
#define CONFIG_SYS_ATA_STRIDE		4	/* Interval between registers                 */

/* Realtime clock */
#define CONFIG_MCFRTC
#undef RTC_DEBUG
#define CONFIG_SYS_RTC_OSCILLATOR	(32 * CONFIG_SYS_HZ)

/* Timer */
#define CONFIG_MCFTMR
#undef CONFIG_MCFPIT

/* I2c */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x58000
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* DSPI and Serial Flash */
#define CONFIG_CF_DSPI
#define CONFIG_HARD_SPI
#define CONFIG_SYS_SBFHDR_SIZE		0x13
#ifdef CONFIG_CMD_SPI

#	define CONFIG_SYS_DSPI_CTAR0		(DSPI_CTAR_TRSZ(7) | \
					 DSPI_CTAR_PCSSCK_1CLK | \
					 DSPI_CTAR_PASC(0) | \
					 DSPI_CTAR_PDT(0) | \
					 DSPI_CTAR_CSSCK(0) | \
					 DSPI_CTAR_ASC(0) | \
					 DSPI_CTAR_DT(1))
#endif

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	4

#define CONFIG_SYS_PCI_MEM_BUS		0xA0000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0xB1000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0xB0000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

/* FPGA - Spartan 2 */
/* experiment
#define CONFIG_FPGA_COUNT	1
#define CONFIG_SYS_FPGA_PROG_FEEDBACK
#define CONFIG_SYS_FPGA_CHECK_CTRLC
*/

/* Input, PCI, Flexbus, and VCO */
#define CONFIG_EXTRA_CLOCK

#define CONFIG_PRAM		2048	/* 2048 KB */

#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x10000)

#define CONFIG_SYS_MBAR		0xFC000000

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
#define CONFIG_SYS_INIT_RAM_SIZE		0x8000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x221
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
#define CONFIG_SYS_SBFHDR_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - 32)

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_SDRAM_BASE1		0x48000000
#define CONFIG_SYS_SDRAM_SIZE		256	/* SDRAM size in MB */
#define CONFIG_SYS_SDRAM_CFG1		0x65311610
#define CONFIG_SYS_SDRAM_CFG2		0x59670000
#define CONFIG_SYS_SDRAM_CTRL		0xEA0B2000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x00010033
#define CONFIG_SYS_SDRAM_DRV_STRENGTH	0xAA

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#ifdef CONFIG_CF_SBF
#	define CONFIG_SERIAL_BOOT
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_TEXT_BASE + 0x400)
#else
#	define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#endif
#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*
 * Configuration for environment
 * Environment is not embedded in u-boot. First time runing may have env
 * crc error warning if there is no correct environment on the flash.
 */
#ifdef CONFIG_CF_SBF
#	define CONFIG_ENV_SPI_CS		1
#endif
#undef CONFIG_ENV_OVERWRITE

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#ifdef CONFIG_SYS_STMICRO_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_OFFSET		0x30000
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x10000
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH0_BASE		CONFIG_SYS_CS0_BASE
#	define CONFIG_SYS_FLASH1_BASE		CONFIG_SYS_CS1_BASE
#	define CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x40000)
#	define CONFIG_ENV_SIZE		0x2000
#	define CONFIG_ENV_SECT_SIZE	0x20000
#endif

#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI

#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE	1
#	define CONFIG_SYS_FLASH_SIZE		0x1000000	/* Max size that the board might have */
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_8BIT
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_CHECKSUM
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#	define CONFIG_FLASH_CFI_LEGACY

#ifdef CONFIG_FLASH_CFI_LEGACY
#	define CONFIG_SYS_ATMEL_REGION		4
#	define CONFIG_SYS_ATMEL_TOTALSECT	11
#	define CONFIG_SYS_ATMEL_SECT		{1, 2, 1, 7}
#	define CONFIG_SYS_ATMEL_SECTSZ		{0x4000, 0x2000, 0x8000, 0x10000}
#endif
#endif

/*
 * This is setting for JFFS2 support in u-boot.
 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
 */
#ifdef CONFIG_CMD_JFFS2
#ifdef CF_STMICRO_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH2_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_ATMEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor1"
#	define CONFIG_JFFS2_PART_SIZE	0x01000000
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH1_BASE + 0x500000)
#endif
#ifdef CONFIG_SYS_INTEL_BOOT
#	define CONFIG_JFFS2_DEV		"nor0"
#	define CONFIG_JFFS2_PART_SIZE	(0x01000000 - 0x500000)
#	define CONFIG_JFFS2_PART_OFFSET	(CONFIG_SYS_FLASH0_BASE + 0x500000)
#endif
#endif

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE		16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_IEC | \
					 CF_CACR_ICINVA | CF_CACR_EUSP)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Memory bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - CompactFlash and registers
 * CS2 - CPLD
 * CS3 - FPGA
 * CS4 - Available
 * CS5 - Available
 */

#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
 /* Atmel Flash */
#define CONFIG_SYS_CS0_BASE		0x04000000
#define CONFIG_SYS_CS0_MASK		0x00070001
#define CONFIG_SYS_CS0_CTRL		0x00001140
/* Intel Flash */
#define CONFIG_SYS_CS1_BASE		0x00000000
#define CONFIG_SYS_CS1_MASK		0x01FF0001
#define CONFIG_SYS_CS1_CTRL		0x00000D60

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS0_BASE
#else
/* Intel Flash */
#define CONFIG_SYS_CS0_BASE		0x00000000
#define CONFIG_SYS_CS0_MASK		0x01FF0001
#define CONFIG_SYS_CS0_CTRL		0x00000D60
 /* Atmel Flash */
#define CONFIG_SYS_CS1_BASE		0x04000000
#define CONFIG_SYS_CS1_MASK		0x00070001
#define CONFIG_SYS_CS1_CTRL		0x00001140

#define CONFIG_SYS_ATMEL_BASE		CONFIG_SYS_CS1_BASE
#endif

/* CPLD */
#define CONFIG_SYS_CS2_BASE		0x08000000
#define CONFIG_SYS_CS2_MASK		0x00070001
#define CONFIG_SYS_CS2_CTRL		0x003f1140

/* FPGA */
#define CONFIG_SYS_CS3_BASE		0x09000000
#define CONFIG_SYS_CS3_MASK		0x00070001
#define CONFIG_SYS_CS3_CTRL		0x00000020

#endif				/* _M54455EVB_H */
Commit	Line	Data
8ae158cd TL	1	/*
	2	* Configuation settings for the Freescale MCF54455 EVB board.
	3	*
	4	* Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
8ae158cd TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
e8ee8f3a TL	14	#ifndef _M54455EVB_H
e8ee8f3a TL	15	#define _M54455EVB_H
8ae158cd TL	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
8ae158cd TL	21	#define CONFIG_M54455EVB /* M54455EVB board */
8ae158cd TL	22
8ae158cd	23	#define CONFIG_MCFUART
6d0f6bcf	24	#define CONFIG_SYS_UART_PORT (0)
8ae158cd	25
c74dda8b AD	26	#define LDS_BOARD_TEXT board/freescale/m54455evb/sbf_dram_init.o (.text*)
c74dda8b AD	27
8ae158cd TL	28	#undef CONFIG_WATCHDOG
	29
	30	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	31
	32	/*
	33	* BOOTP options
	34	*/
	35	#define CONFIG_BOOTP_BOOTFILESIZE
8ae158cd	36
8ae158cd TL	37	/* Network configuration */
	38	#define CONFIG_MCFFEC
	39	#ifdef CONFIG_MCFFEC
8ae158cd	40	# define CONFIG_MII 1
0f3ba7e9	41	# define CONFIG_MII_INIT 1
6d0f6bcf JCPV	42	# define CONFIG_SYS_DISCOVER_PHY
	43	# define CONFIG_SYS_RX_ETH_BUFFER 8
	44	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
	45
	46	# define CONFIG_SYS_FEC0_PINMUX 0
	47	# define CONFIG_SYS_FEC1_PINMUX 0
	48	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	49	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
8ae158cd TL	50	# define MCFFEC_TOUT_LOOP 50000
	51	# define CONFIG_HAS_ETH1
	52
8ae158cd TL	53	# define CONFIG_ETHPRIME "FEC0"
	54	# define CONFIG_IPADDR 192.162.1.2
	55	# define CONFIG_NETMASK 255.255.255.0
	56	# define CONFIG_SERVERIP 192.162.1.1
	57	# define CONFIG_GATEWAYIP 192.162.1.1
8ae158cd	58
6d0f6bcf JCPV	59	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	60	# ifndef CONFIG_SYS_DISCOVER_PHY
8ae158cd TL	61	# define FECDUPLEX FULL
	62	# define FECSPEED _100BASET
	63	# else
6d0f6bcf JCPV	64	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	65	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
8ae158cd	66	# endif
6d0f6bcf	67	# endif /* CONFIG_SYS_DISCOVER_PHY */
8ae158cd TL	68	#endif
	69
	70	#define CONFIG_HOSTNAME M54455EVB
6d0f6bcf	71	#ifdef CONFIG_SYS_STMICRO_BOOT
9f751551	72	/* ST Micro serial flash */
6d0f6bcf	73	#define CONFIG_SYS_LOAD_ADDR2 0x40010013
8ae158cd TL	74	#define CONFIG_EXTRA_ENV_SETTINGS \
8ae158cd TL	75	"netdev=eth0\0" \
5368c55d	76	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	77	"loadaddr=0x40010000\0" \
	78	"sbfhdr=sbfhdr.bin\0" \
	79	"uboot=u-boot.bin\0" \
	80	"load=tftp ${loadaddr} ${sbfhdr};" \
5368c55d	81	"tftp " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
8ae158cd	82	"upd=run load; run prog\0" \
09933fb0	83	"prog=sf probe 0:1 1000000 3;" \
9f751551 TL	84	"sf erase 0 30000;" \
9f751551 TL	85	"sf write ${loadaddr} 0 0x30000;" \
8ae158cd TL	86	"save\0" \
8ae158cd TL	87	""
9f751551 TL	88	#else
9f751551 TL	89	/* Atmel and Intel */
6d0f6bcf JCPV	90	#ifdef CONFIG_SYS_ATMEL_BOOT
	91	# define CONFIG_SYS_UBOOT_END 0x0403FFFF
	92	#elif defined(CONFIG_SYS_INTEL_BOOT)
	93	# define CONFIG_SYS_UBOOT_END 0x3FFFF
9f751551 TL	94	#endif
	95	#define CONFIG_EXTRA_ENV_SETTINGS \
	96	"netdev=eth0\0" \
5368c55d	97	"inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \
9f751551 TL	98	"loadaddr=0x40010000\0" \
	99	"uboot=u-boot.bin\0" \
	100	"load=tftp ${loadaddr} ${uboot}\0" \
	101	"upd=run load; run prog\0" \
5368c55d MV	102	"prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \
	103	" " __stringify(CONFIG_SYS_UBOOT_END) ";" \
	104	"era " __stringify(CONFIG_SYS_FLASH_BASE) " " \
	105	__stringify(CONFIG_SYS_UBOOT_END) ";" \
	106	"cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \
9f751551 TL	107	" ${filesize}; save\0" \
	108	""
	109	#endif
8ae158cd TL	110
8ae158cd TL	111	/* ATA configuration */
8ae158cd TL	112	#define CONFIG_IDE_RESET 1
	113	#define CONFIG_IDE_PREINIT 1
	114	#define CONFIG_ATAPI
	115	#undef CONFIG_LBA48
	116
6d0f6bcf JCPV	117	#define CONFIG_SYS_IDE_MAXBUS 1
6d0f6bcf JCPV	118	#define CONFIG_SYS_IDE_MAXDEVICE 2
8ae158cd	119
6d0f6bcf JCPV	120	#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
6d0f6bcf JCPV	121	#define CONFIG_SYS_ATA_IDE0_OFFSET 0
8ae158cd	122
6d0f6bcf JCPV	123	#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
	124	#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
	125	#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
	126	#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
8ae158cd TL	127
	128	/* Realtime clock */
	129	#define CONFIG_MCFRTC
	130	#undef RTC_DEBUG
6d0f6bcf	131	#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
8ae158cd TL	132
	133	/* Timer */
	134	#define CONFIG_MCFTMR
	135	#undef CONFIG_MCFPIT
	136
	137	/* I2c */
00f792e0 HS	138	#define CONFIG_SYS_I2C
	139	#define CONFIG_SYS_I2C_FSL
	140	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	141	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
6af3a0ea	142	#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000
6d0f6bcf	143	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
8ae158cd	144
bae61eef TL	145	/* DSPI and Serial Flash */
bae61eef TL	146	#define CONFIG_CF_DSPI
a7323bba	147	#define CONFIG_HARD_SPI
6d0f6bcf	148	#define CONFIG_SYS_SBFHDR_SIZE 0x13
a7323bba	149	#ifdef CONFIG_CMD_SPI
922cd751	150
ee0a8462 TL	151	# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) \| \
	152	DSPI_CTAR_PCSSCK_1CLK \| \
	153	DSPI_CTAR_PASC(0) \| \
	154	DSPI_CTAR_PDT(0) \| \
	155	DSPI_CTAR_CSSCK(0) \| \
	156	DSPI_CTAR_ASC(0) \| \
	157	DSPI_CTAR_DT(1))
a7323bba	158	#endif
bae61eef	159
8ae158cd	160	/* PCI */
e8ee8f3a	161	#ifdef CONFIG_CMD_PCI
f33fca22	162	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
2e72ad06	163
6d0f6bcf	164	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
8ae158cd	165
6d0f6bcf JCPV	166	#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
	167	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	168	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
8ae158cd	169
6d0f6bcf JCPV	170	#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
	171	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	172	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
8ae158cd	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
	175	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	176	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
e8ee8f3a	177	#endif
8ae158cd TL	178
	179	/* FPGA - Spartan 2 */
	180	/* experiment
8ae158cd	181	#define CONFIG_FPGA_COUNT 1
6d0f6bcf JCPV	182	#define CONFIG_SYS_FPGA_PROG_FEEDBACK
6d0f6bcf JCPV	183	#define CONFIG_SYS_FPGA_CHECK_CTRLC
8ae158cd TL	184	*/
	185
	186	/* Input, PCI, Flexbus, and VCO */
	187	#define CONFIG_EXTRA_CLOCK
	188
9f751551	189	#define CONFIG_PRAM 2048 /* 2048 KB */
8ae158cd	190
6d0f6bcf	191	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
8ae158cd	192
6d0f6bcf	193	#define CONFIG_SYS_MBAR 0xFC000000
8ae158cd TL	194
	195	/*
	196	* Low Level Configuration Settings
	197	* (address mappings, register initial values, etc.)
	198	* You should know what you are doing if you make changes here.
	199	*/
	200
	201	/*-----------------------------------------------------------------------
	202	* Definitions for initial stack pointer and data area (in DPRAM)
	203	*/
6d0f6bcf	204	#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
553f0982	205	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */
6d0f6bcf	206	#define CONFIG_SYS_INIT_RAM_CTRL 0x221
25ddd1fb	207	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32)
6d0f6bcf	208	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
553f0982	209	#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32)
8ae158cd TL	210
	211	/*-----------------------------------------------------------------------
	212	* Start addresses for the final memory configuration
	213	* (Set up by the startup code)
6d0f6bcf	214	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
8ae158cd	215	*/
6d0f6bcf JCPV	216	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	217	#define CONFIG_SYS_SDRAM_BASE1 0x48000000
	218	#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
	219	#define CONFIG_SYS_SDRAM_CFG1 0x65311610
	220	#define CONFIG_SYS_SDRAM_CFG2 0x59670000
	221	#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
	222	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	223	#define CONFIG_SYS_SDRAM_MODE 0x00010033
	224	#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
	225
	226	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
	227	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
8ae158cd	228
9f751551	229	#ifdef CONFIG_CF_SBF
09933fb0	230	# define CONFIG_SERIAL_BOOT
14d0a02a	231	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400)
9f751551	232	#else
6d0f6bcf	233	# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
9f751551	234	#endif
6d0f6bcf JCPV	235	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
6d0f6bcf JCPV	236	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
09933fb0 JJ	237
	238	/* Reserve 256 kB for malloc() */
	239	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
8ae158cd TL	240
	241	/*
	242	* For booting Linux, the board info and command line data
	243	* have to be in the first 8 MB of memory, since this is
	244	* the maximum mapped by the Linux kernel during initialization ??
	245	*/
	246	/* Initial Memory map for Linux */
6d0f6bcf	247	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
8ae158cd	248
9f751551 TL	249	/*
9f751551 TL	250	* Configuration for environment
09933fb0 JJ	251	* Environment is not embedded in u-boot. First time runing may have env
09933fb0 JJ	252	* crc error warning if there is no correct environment on the flash.
8ae158cd	253	*/
9f751551	254	#ifdef CONFIG_CF_SBF
0e8d1586	255	# define CONFIG_ENV_SPI_CS 1
9f751551 TL	256	#endif
9f751551 TL	257	#undef CONFIG_ENV_OVERWRITE
8ae158cd TL	258
	259	/*-----------------------------------------------------------------------
	260	* FLASH organization
	261	*/
6d0f6bcf	262	#ifdef CONFIG_SYS_STMICRO_BOOT
ee0a8462 TL	263	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
ee0a8462 TL	264	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
0e8d1586 JCPV	265	# define CONFIG_ENV_OFFSET 0x30000
	266	# define CONFIG_ENV_SIZE 0x2000
	267	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	268	#endif
6d0f6bcf JCPV	269	#ifdef CONFIG_SYS_ATMEL_BOOT
	270	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	271	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	272	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
09933fb0 JJ	273	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
	274	# define CONFIG_ENV_SIZE 0x2000
	275	# define CONFIG_ENV_SECT_SIZE 0x10000
9f751551	276	#endif
6d0f6bcf JCPV	277	#ifdef CONFIG_SYS_INTEL_BOOT
	278	# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
	279	# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
	280	# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
	281	# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
0e8d1586 JCPV	282	# define CONFIG_ENV_SIZE 0x2000
0e8d1586 JCPV	283	# define CONFIG_ENV_SECT_SIZE 0x20000
8ae158cd TL	284	#endif
8ae158cd TL	285
6d0f6bcf JCPV	286	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	287	#ifdef CONFIG_SYS_FLASH_CFI
8ae158cd	288
00b1883a	289	# define CONFIG_FLASH_CFI_DRIVER 1
bbf6bbff	290	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
6d0f6bcf JCPV	291	# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
	292	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
	293	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	294	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	295	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	296	# define CONFIG_SYS_FLASH_CHECKSUM
	297	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
b2d022d1	298	# define CONFIG_FLASH_CFI_LEGACY
8ae158cd	299
b2d022d1	300	#ifdef CONFIG_FLASH_CFI_LEGACY
6d0f6bcf JCPV	301	# define CONFIG_SYS_ATMEL_REGION 4
	302	# define CONFIG_SYS_ATMEL_TOTALSECT 11
	303	# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
	304	# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
bae61eef	305	#endif
8ae158cd TL	306	#endif
	307
	308	/*
	309	* This is setting for JFFS2 support in u-boot.
	310	* NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
	311	*/
9f751551 TL	312	#ifdef CONFIG_CMD_JFFS2
	313	#ifdef CF_STMICRO_BOOT
	314	# define CONFIG_JFFS2_DEV "nor1"
	315	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	316	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
9f751551	317	#endif
6d0f6bcf	318	#ifdef CONFIG_SYS_ATMEL_BOOT
e8ee8f3a	319	# define CONFIG_JFFS2_DEV "nor1"
8ae158cd	320	# define CONFIG_JFFS2_PART_SIZE 0x01000000
6d0f6bcf	321	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
9f751551	322	#endif
6d0f6bcf	323	#ifdef CONFIG_SYS_INTEL_BOOT
8ae158cd TL	324	# define CONFIG_JFFS2_DEV "nor0"
8ae158cd TL	325	# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
6d0f6bcf	326	# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
8ae158cd	327	#endif
9f751551	328	#endif
8ae158cd TL	329
	330	/*-----------------------------------------------------------------------
	331	* Cache Configuration
	332	*/
6d0f6bcf	333	#define CONFIG_SYS_CACHELINE_SIZE 16
8ae158cd	334
dd9f054e	335	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	336	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	337	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	338	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	339	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
	340	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	341	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	342	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	343	CF_ACR_EN \| CF_ACR_SM_ALL)
	344	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_IEC \| \
	345	CF_CACR_ICINVA \| CF_CACR_EUSP)
	346	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	347	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	348	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	349
8ae158cd TL	350	/*-----------------------------------------------------------------------
	351	* Memory bank definitions
	352	*/
	353	/*
	354	* CS0 - NOR Flash 1, 2, 4, or 8MB
	355	* CS1 - CompactFlash and registers
	356	* CS2 - CPLD
	357	* CS3 - FPGA
	358	* CS4 - Available
	359	* CS5 - Available
	360	*/
	361
6d0f6bcf	362	#if defined(CONFIG_SYS_ATMEL_BOOT) \|\| defined(CONFIG_SYS_STMICRO_BOOT)
8ae158cd	363	/* Atmel Flash */
6d0f6bcf JCPV	364	#define CONFIG_SYS_CS0_BASE 0x04000000
	365	#define CONFIG_SYS_CS0_MASK 0x00070001
	366	#define CONFIG_SYS_CS0_CTRL 0x00001140
8ae158cd	367	/* Intel Flash */
6d0f6bcf JCPV	368	#define CONFIG_SYS_CS1_BASE 0x00000000
	369	#define CONFIG_SYS_CS1_MASK 0x01FF0001
	370	#define CONFIG_SYS_CS1_CTRL 0x00000D60
8ae158cd	371
6d0f6bcf	372	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
8ae158cd TL	373	#else
8ae158cd TL	374	/* Intel Flash */
6d0f6bcf JCPV	375	#define CONFIG_SYS_CS0_BASE 0x00000000
	376	#define CONFIG_SYS_CS0_MASK 0x01FF0001
	377	#define CONFIG_SYS_CS0_CTRL 0x00000D60
8ae158cd	378	/* Atmel Flash */
6d0f6bcf JCPV	379	#define CONFIG_SYS_CS1_BASE 0x04000000
	380	#define CONFIG_SYS_CS1_MASK 0x00070001
	381	#define CONFIG_SYS_CS1_CTRL 0x00001140
8ae158cd	382
6d0f6bcf	383	#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
8ae158cd TL	384	#endif
	385
	386	/* CPLD */
6d0f6bcf JCPV	387	#define CONFIG_SYS_CS2_BASE 0x08000000
	388	#define CONFIG_SYS_CS2_MASK 0x00070001
	389	#define CONFIG_SYS_CS2_CTRL 0x003f1140
8ae158cd TL	390
8ae158cd TL	391	/* FPGA */
6d0f6bcf JCPV	392	#define CONFIG_SYS_CS3_BASE 0x09000000
	393	#define CONFIG_SYS_CS3_MASK 0x00070001
	394	#define CONFIG_SYS_CS3_CTRL 0x00000020
8ae158cd	395
e8ee8f3a	396	#endif /* _M54455EVB_H */