[people/ms/u-boot.git] / include / configs / M5475EVB.h

/*
 * Configuation settings for the Freescale MCF5475 board.
 *
 * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef _M5475EVB_H
#define _M5475EVB_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MCFUART
#define CONFIG_SYS_UART_PORT		(0)

#undef CONFIG_HW_WATCHDOG
#define CONFIG_WATCHDOG_TIMEOUT	5000	/* timeout in milliseconds, max timeout is 6.71sec */

#define CONFIG_SLTTMR

#define CONFIG_FSLDMAFEC
#ifdef CONFIG_FSLDMAFEC
#	define CONFIG_MII		1
#	define CONFIG_MII_INIT		1
#	define CONFIG_HAS_ETH1

#	define CONFIG_SYS_DMA_USE_INTSRAM	1
#	define CONFIG_SYS_DISCOVER_PHY
#	define CONFIG_SYS_RX_ETH_BUFFER	32
#	define CONFIG_SYS_TX_ETH_BUFFER	48
#	define CONFIG_SYS_FAULT_ECHO_LINK_DOWN

#	define CONFIG_SYS_FEC0_PINMUX		0
#	define CONFIG_SYS_FEC0_MIIBASE		CONFIG_SYS_FEC0_IOBASE
#	define CONFIG_SYS_FEC1_PINMUX		0
#	define CONFIG_SYS_FEC1_MIIBASE		CONFIG_SYS_FEC0_IOBASE

#	define MCFFEC_TOUT_LOOP		50000
/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
#	ifndef CONFIG_SYS_DISCOVER_PHY
#		define FECDUPLEX	FULL
#		define FECSPEED		_100BASET
#	else
#		ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#			define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
#		endif
#	endif			/* CONFIG_SYS_DISCOVER_PHY */

#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1

#endif

#ifdef CONFIG_CMD_USB
#	define CONFIG_USB_OHCI_NEW

#	define CONFIG_PCI_OHCI

#	undef CONFIG_SYS_USB_OHCI_BOARD_INIT
#	undef CONFIG_SYS_USB_OHCI_CPU_INIT
#	define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	15
#	define CONFIG_SYS_USB_OHCI_SLOT_NAME		"isp1561"
#	define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
#endif

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	80000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x00008F00
#define CONFIG_SYS_IMMR		CONFIG_SYS_MBAR

/* PCI */
#ifdef CONFIG_CMD_PCI
#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE	1

#define CONFIG_SYS_PCI_CACHE_LINE_SIZE	8

#define CONFIG_SYS_PCI_MEM_BUS		0x80000000
#define CONFIG_SYS_PCI_MEM_PHYS	CONFIG_SYS_PCI_MEM_BUS
#define CONFIG_SYS_PCI_MEM_SIZE	0x10000000

#define CONFIG_SYS_PCI_IO_BUS		0x71000000
#define CONFIG_SYS_PCI_IO_PHYS		CONFIG_SYS_PCI_IO_BUS
#define CONFIG_SYS_PCI_IO_SIZE		0x01000000

#define CONFIG_SYS_PCI_CFG_BUS		0x70000000
#define CONFIG_SYS_PCI_CFG_PHYS	CONFIG_SYS_PCI_CFG_BUS
#define CONFIG_SYS_PCI_CFG_SIZE	0x01000000
#endif

#define CONFIG_UDP_CHECKSUM

#ifdef CONFIG_MCFFEC
#	define CONFIG_IPADDR	192.162.1.2
#	define CONFIG_NETMASK	255.255.255.0
#	define CONFIG_SERVERIP	192.162.1.1
#	define CONFIG_GATEWAYIP	192.162.1.1
#endif				/* FEC_ENET */

#define CONFIG_HOSTNAME		M547xEVB
#define CONFIG_EXTRA_ENV_SETTINGS		\
	"netdev=eth0\0"				\
	"loadaddr=10000\0"			\
	"u-boot=u-boot.bin\0"			\
	"load=tftp ${loadaddr) ${u-boot}\0"	\
	"upd=run load; run prog\0"		\
	"prog=prot off bank 1;"			\
	"era ff800000 ff83ffff;"		\
	"cp.b ${loadaddr} ff800000 ${filesize};"\
	"save\0"				\
	""

#define CONFIG_PRAM		512	/* 512 KB */

#define CONFIG_SYS_LOAD_ADDR		0x00010000

#define CONFIG_SYS_CLK			CONFIG_SYS_BUSCLK
#define CONFIG_SYS_CPU_CLK		CONFIG_SYS_CLK * 2

#define CONFIG_SYS_MBAR		0xF0000000
#define CONFIG_SYS_INTSRAM		(CONFIG_SYS_MBAR + 0x10000)
#define CONFIG_SYS_INTSRAMSZ		0x8000

/*#define CONFIG_SYS_LATCH_ADDR		(CONFIG_SYS_CS1_BASE + 0x80000)*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	0xF2000000
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM_CTRL	0x21
#define CONFIG_SYS_INIT_RAM1_ADDR	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
#define CONFIG_SYS_INIT_RAM1_END	0x1000	/* End of used area in internal SRAM */
#define CONFIG_SYS_INIT_RAM1_CTRL	0x21
#define CONFIG_SYS_GBL_DATA_OFFSET	((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_SDRAM_CFG1		0x73711630
#define CONFIG_SYS_SDRAM_CFG2		0x46770000
#define CONFIG_SYS_SDRAM_CTRL		0xE10B0000
#define CONFIG_SYS_SDRAM_EMOD		0x40010000
#define CONFIG_SYS_SDRAM_MODE		0x018D0000
#define CONFIG_SYS_SDRAM_DRVSTRENGTH	0x000002AA
#ifdef CONFIG_SYS_DRAMSZ1
#	define CONFIG_SYS_SDRAM_SIZE	(CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
#else
#	define CONFIG_SYS_SDRAM_SIZE	CONFIG_SYS_DRAMSZ
#endif

#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE + 0x400
#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)

#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE + 0x400)
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor */

#define CONFIG_SYS_BOOTPARAMS_LEN	64*1024

/* Reserve 256 kB for malloc() */
#define CONFIG_SYS_MALLOC_LEN		(256 << 10)
/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization ??
 */
#define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_FLASH_CFI
#ifdef CONFIG_SYS_FLASH_CFI
#	define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
#	define CONFIG_FLASH_CFI_DRIVER	1
#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
#	define CONFIG_SYS_MAX_FLASH_SECT	137	/* max number of sectors on one chip */
#	define CONFIG_SYS_FLASH_PROTECTION	/* "Real" (hardware) sectors protection */
#	define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
#ifdef CONFIG_SYS_NOR1SZ
#	define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks */
#	define CONFIG_SYS_FLASH_SIZE		((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
#	define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
#else
#	define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks */
#	define CONFIG_SYS_FLASH_SIZE		(CONFIG_SYS_BOOTSZ << 20)
#endif
#endif

/* Configuration for environment
 * Environment is not embedded in u-boot but at offset 0x40000 on the flash.
 * First time runing may have env crc error warning if there is
 * no correct environment on the flash.
 */
#define CONFIG_ENV_OFFSET		0x40000
#define CONFIG_ENV_SECT_SIZE	0x10000

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16

#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 8)
#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
					 CONFIG_SYS_INIT_RAM_SIZE - 4)
#define CONFIG_SYS_ICACHE_INV		(CF_CACR_BCINVA + CF_CACR_ICINVA + \
					 CF_CACR_IDCM)
#define CONFIG_SYS_DCACHE_INV		(CF_CACR_DCINVA)
#define CONFIG_SYS_CACHE_ACR2		(CONFIG_SYS_SDRAM_BASE | \
					 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
					 CF_ACR_EN | CF_ACR_SM_ALL)
#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_BEC | CF_CACR_BCINVA | \
					 CF_CACR_IEC | CF_CACR_ICINVA)
#define CONFIG_SYS_CACHE_DCACR		((CONFIG_SYS_CACHE_ICACR | \
					 CF_CACR_DEC | CF_CACR_DDCM_P | \
					 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)

/*-----------------------------------------------------------------------
 * Chipselect bank definitions
 */
/*
 * CS0 - NOR Flash 1, 2, 4, or 8MB
 * CS1 - NOR Flash
 * CS2 - Available
 * CS3 - Available
 * CS4 - Available
 * CS5 - Available
 */
#define CONFIG_SYS_CS0_BASE		0xFF800000
#define CONFIG_SYS_CS0_MASK		(((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS0_CTRL		0x00101980

#ifdef CONFIG_SYS_NOR1SZ
#define CONFIG_SYS_CS1_BASE		0xE0000000
#define CONFIG_SYS_CS1_MASK		(((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
#define CONFIG_SYS_CS1_CTRL		0x00101D80
#endif

#endif				/* _M5475EVB_H */
Commit	Line	Data
57a12720 TL	1	/*
	2	* Configuation settings for the Freescale MCF5475 board.
	3	*
	4	* Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
	5	* TsiChung Liew (Tsi-Chung.Liew@freescale.com)
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
57a12720 TL	8	*/
	9
	10	/*
	11	* board/config.h - configuration options, board specific
	12	*/
	13
	14	#ifndef _M5475EVB_H
	15	#define _M5475EVB_H
	16
	17	/*
	18	* High Level Configuration Options
	19	* (easy to change)
	20	*/
57a12720	21
57a12720	22	#define CONFIG_MCFUART
6d0f6bcf	23	#define CONFIG_SYS_UART_PORT (0)
57a12720	24
1313db48	25	#undef CONFIG_HW_WATCHDOG
57a12720 TL	26	#define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */
57a12720 TL	27
57a12720 TL	28	#define CONFIG_SLTTMR
	29
	30	#define CONFIG_FSLDMAFEC
	31	#ifdef CONFIG_FSLDMAFEC
57a12720	32	# define CONFIG_MII 1
0f3ba7e9	33	# define CONFIG_MII_INIT 1
57a12720 TL	34	# define CONFIG_HAS_ETH1
57a12720 TL	35
6d0f6bcf JCPV	36	# define CONFIG_SYS_DMA_USE_INTSRAM 1
	37	# define CONFIG_SYS_DISCOVER_PHY
	38	# define CONFIG_SYS_RX_ETH_BUFFER 32
	39	# define CONFIG_SYS_TX_ETH_BUFFER 48
	40	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57a12720	41
6d0f6bcf JCPV	42	# define CONFIG_SYS_FEC0_PINMUX 0
	43	# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
	44	# define CONFIG_SYS_FEC1_PINMUX 0
	45	# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
57a12720	46
53677ef1	47	# define MCFFEC_TOUT_LOOP 50000
6d0f6bcf JCPV	48	/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
6d0f6bcf JCPV	49	# ifndef CONFIG_SYS_DISCOVER_PHY
57a12720 TL	50	# define FECDUPLEX FULL
	51	# define FECSPEED _100BASET
	52	# else
6d0f6bcf JCPV	53	# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
6d0f6bcf JCPV	54	# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
57a12720	55	# endif
6d0f6bcf	56	# endif /* CONFIG_SYS_DISCOVER_PHY */
57a12720	57
57a12720 TL	58	# define CONFIG_IPADDR 192.162.1.2
	59	# define CONFIG_NETMASK 255.255.255.0
	60	# define CONFIG_SERVERIP 192.162.1.1
	61	# define CONFIG_GATEWAYIP 192.162.1.1
57a12720 TL	62
	63	#endif
	64
	65	#ifdef CONFIG_CMD_USB
	66	# define CONFIG_USB_OHCI_NEW
57a12720	67
57a12720	68	# define CONFIG_PCI_OHCI
57a12720	69
6d0f6bcf JCPV	70	# undef CONFIG_SYS_USB_OHCI_BOARD_INIT
	71	# undef CONFIG_SYS_USB_OHCI_CPU_INIT
	72	# define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
	73	# define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561"
	74	# define CONFIG_SYS_OHCI_SWAP_REG_ACCESS
57a12720 TL	75	#endif
	76
	77	/* I2C */
00f792e0 HS	78	#define CONFIG_SYS_I2C
	79	#define CONFIG_SYS_I2C_FSL
	80	#define CONFIG_SYS_FSL_I2C_SPEED 80000
	81	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	82	#define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00
6d0f6bcf	83	#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
57a12720 TL	84
	85	/* PCI */
	86	#ifdef CONFIG_CMD_PCI
f33fca22	87	#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
57a12720	88
6d0f6bcf	89	#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8
57a12720	90
6d0f6bcf JCPV	91	#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
	92	#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
	93	#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
57a12720	94
6d0f6bcf JCPV	95	#define CONFIG_SYS_PCI_IO_BUS 0x71000000
	96	#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
	97	#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
57a12720	98
6d0f6bcf JCPV	99	#define CONFIG_SYS_PCI_CFG_BUS 0x70000000
	100	#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
	101	#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
57a12720 TL	102	#endif
57a12720 TL	103
57a12720 TL	104	#define CONFIG_UDP_CHECKSUM
	105
	106	#ifdef CONFIG_MCFFEC
57a12720 TL	107	# define CONFIG_IPADDR 192.162.1.2
	108	# define CONFIG_NETMASK 255.255.255.0
	109	# define CONFIG_SERVERIP 192.162.1.1
	110	# define CONFIG_GATEWAYIP 192.162.1.1
57a12720 TL	111	#endif /* FEC_ENET */
	112
	113	#define CONFIG_HOSTNAME M547xEVB
	114	#define CONFIG_EXTRA_ENV_SETTINGS \
	115	"netdev=eth0\0" \
	116	"loadaddr=10000\0" \
	117	"u-boot=u-boot.bin\0" \
	118	"load=tftp ${loadaddr) ${u-boot}\0" \
	119	"upd=run load; run prog\0" \
	120	"prog=prot off bank 1;" \
09933fb0	121	"era ff800000 ff83ffff;" \
57a12720 TL	122	"cp.b ${loadaddr} ff800000 ${filesize};"\
	123	"save\0" \
	124	""
	125
	126	#define CONFIG_PRAM 512 /* 512 KB */
57a12720	127
6d0f6bcf	128	#define CONFIG_SYS_LOAD_ADDR 0x00010000
57a12720	129
6d0f6bcf JCPV	130	#define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK
6d0f6bcf JCPV	131	#define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2
57a12720	132
6d0f6bcf JCPV	133	#define CONFIG_SYS_MBAR 0xF0000000
	134	#define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000)
	135	#define CONFIG_SYS_INTSRAMSZ 0x8000
57a12720	136
6d0f6bcf	137	/#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)/
57a12720 TL	138
	139	/*
	140	* Low Level Configuration Settings
	141	* (address mappings, register initial values, etc.)
	142	* You should know what you are doing if you make changes here.
	143	*/
	144	/*-----------------------------------------------------------------------
	145	* Definitions for initial stack pointer and data area (in DPRAM)
	146	*/
6d0f6bcf	147	#define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000
553f0982	148	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */
6d0f6bcf	149	#define CONFIG_SYS_INIT_RAM_CTRL 0x21
553f0982	150	#define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
6d0f6bcf JCPV	151	#define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */
6d0f6bcf JCPV	152	#define CONFIG_SYS_INIT_RAM1_CTRL 0x21
25ddd1fb	153	#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
6d0f6bcf	154	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
57a12720 TL	155
	156	/*-----------------------------------------------------------------------
	157	* Start addresses for the final memory configuration
	158	* (Set up by the startup code)
6d0f6bcf	159	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
57a12720	160	*/
6d0f6bcf JCPV	161	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	162	#define CONFIG_SYS_SDRAM_CFG1 0x73711630
	163	#define CONFIG_SYS_SDRAM_CFG2 0x46770000
	164	#define CONFIG_SYS_SDRAM_CTRL 0xE10B0000
	165	#define CONFIG_SYS_SDRAM_EMOD 0x40010000
	166	#define CONFIG_SYS_SDRAM_MODE 0x018D0000
	167	#define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA
	168	#ifdef CONFIG_SYS_DRAMSZ1
	169	# define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1)
57a12720	170	#else
6d0f6bcf	171	# define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ
57a12720 TL	172	#endif
57a12720 TL	173
6d0f6bcf JCPV	174	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
6d0f6bcf JCPV	175	#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
57a12720	176
6d0f6bcf JCPV	177	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
6d0f6bcf JCPV	178	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
57a12720	179
6d0f6bcf	180	#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
57a12720	181
09933fb0 JJ	182	/* Reserve 256 kB for malloc() */
09933fb0 JJ	183	#define CONFIG_SYS_MALLOC_LEN (256 << 10)
57a12720 TL	184	/*
	185	* For booting Linux, the board info and command line data
	186	* have to be in the first 8 MB of memory, since this is
	187	* the maximum mapped by the Linux kernel during initialization ??
	188	*/
6d0f6bcf	189	#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
57a12720 TL	190
	191	/*-----------------------------------------------------------------------
	192	* FLASH organization
	193	*/
6d0f6bcf JCPV	194	#define CONFIG_SYS_FLASH_CFI
	195	#ifdef CONFIG_SYS_FLASH_CFI
	196	# define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE)
00b1883a	197	# define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	198	# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
	199	# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
	200	# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
	201	# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
	202	#ifdef CONFIG_SYS_NOR1SZ
	203	# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
	204	# define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20)
	205	# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
57a12720	206	#else
6d0f6bcf JCPV	207	# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	208	# define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20)
57a12720 TL	209	#endif
	210	#endif
	211
	212	/* Configuration for environment
09933fb0 JJ	213	* Environment is not embedded in u-boot but at offset 0x40000 on the flash.
	214	* First time runing may have env crc error warning if there is
	215	* no correct environment on the flash.
57a12720	216	*/
09933fb0 JJ	217	#define CONFIG_ENV_OFFSET 0x40000
09933fb0 JJ	218	#define CONFIG_ENV_SECT_SIZE 0x10000
57a12720 TL	219
	220	/*-----------------------------------------------------------------------
	221	* Cache Configuration
	222	*/
6d0f6bcf	223	#define CONFIG_SYS_CACHELINE_SIZE 16
57a12720	224
dd9f054e	225	#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	226	CONFIG_SYS_INIT_RAM_SIZE - 8)
dd9f054e	227	#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
553f0982	228	CONFIG_SYS_INIT_RAM_SIZE - 4)
dd9f054e TL	229	#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \
	230	CF_CACR_IDCM)
	231	#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
	232	#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE \| \
	233	CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) \| \
	234	CF_ACR_EN \| CF_ACR_SM_ALL)
	235	#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC \| CF_CACR_BCINVA \| \
	236	CF_CACR_IEC \| CF_CACR_ICINVA)
	237	#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR \| \
	238	CF_CACR_DEC \| CF_CACR_DDCM_P \| \
	239	CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
	240
57a12720 TL	241	/*-----------------------------------------------------------------------
	242	* Chipselect bank definitions
	243	*/
	244	/*
	245	* CS0 - NOR Flash 1, 2, 4, or 8MB
	246	* CS1 - NOR Flash
	247	* CS2 - Available
	248	* CS3 - Available
	249	* CS4 - Available
	250	* CS5 - Available
	251	*/
6d0f6bcf JCPV	252	#define CONFIG_SYS_CS0_BASE 0xFF800000
	253	#define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001)
	254	#define CONFIG_SYS_CS0_CTRL 0x00101980
	255
	256	#ifdef CONFIG_SYS_NOR1SZ
	257	#define CONFIG_SYS_CS1_BASE 0xE0000000
	258	#define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001)
	259	#define CONFIG_SYS_CS1_CTRL 0x00101D80
57a12720 TL	260	#endif
	261
	262	#endif /* _M5475EVB_H */