projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 57a12720 TL |
1 | /* |
| 2 | * Configuation settings for the Freescale MCF5475 board. | |
| 3 | * | |
| 4 | * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. | |
| 5 | * TsiChung Liew (Tsi-Chung.Liew@freescale.com) | |
| 6 | * | |
| 3765b3e7 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
| 57a12720 TL |
8 | */ |
| 9 | ||
| 10 | /* | |
| 11 | * board/config.h - configuration options, board specific | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef _M5475EVB_H | |
| 15 | #define _M5475EVB_H | |
| 16 | ||
| 17 | /* | |
| 18 | * High Level Configuration Options | |
| 19 | * (easy to change) | |
| 20 | */ | |
| 57a12720 | 21 | |
| 57a12720 | 22 | #define CONFIG_MCFUART |
| 6d0f6bcf | 23 | #define CONFIG_SYS_UART_PORT (0) |
| 57a12720 | 24 | #define CONFIG_BAUDRATE 115200 |
| 57a12720 | 25 | |
| 1313db48 | 26 | #undef CONFIG_HW_WATCHDOG |
| 57a12720 TL |
27 | #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ |
| 28 | ||
| 29 | /* Command line configuration */ | |
| 57a12720 | 30 | #undef CONFIG_CMD_DATE |
| 57a12720 | 31 | #define CONFIG_CMD_PCI |
| 57a12720 | 32 | #define CONFIG_CMD_REGINFO |
| 57a12720 TL |
33 | |
| 34 | #define CONFIG_SLTTMR | |
| 35 | ||
| 36 | #define CONFIG_FSLDMAFEC | |
| 37 | #ifdef CONFIG_FSLDMAFEC | |
| 57a12720 | 38 | # define CONFIG_MII 1 |
| 0f3ba7e9 | 39 | # define CONFIG_MII_INIT 1 |
| 57a12720 TL |
40 | # define CONFIG_HAS_ETH1 |
| 41 | ||
| 6d0f6bcf JCPV |
42 | # define CONFIG_SYS_DMA_USE_INTSRAM 1 |
| 43 | # define CONFIG_SYS_DISCOVER_PHY | |
| 44 | # define CONFIG_SYS_RX_ETH_BUFFER 32 | |
| 45 | # define CONFIG_SYS_TX_ETH_BUFFER 48 | |
| 46 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
| 57a12720 | 47 | |
| 6d0f6bcf JCPV |
48 | # define CONFIG_SYS_FEC0_PINMUX 0 |
| 49 | # define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
| 50 | # define CONFIG_SYS_FEC1_PINMUX 0 | |
| 51 | # define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE | |
| 57a12720 | 52 | |
| 53677ef1 | 53 | # define MCFFEC_TOUT_LOOP 50000 |
| 6d0f6bcf JCPV |
54 | /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */ |
| 55 | # ifndef CONFIG_SYS_DISCOVER_PHY | |
| 57a12720 TL |
56 | # define FECDUPLEX FULL |
| 57 | # define FECSPEED _100BASET | |
| 58 | # else | |
| 6d0f6bcf JCPV |
59 | # ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN |
| 60 | # define CONFIG_SYS_FAULT_ECHO_LINK_DOWN | |
| 57a12720 | 61 | # endif |
| 6d0f6bcf | 62 | # endif /* CONFIG_SYS_DISCOVER_PHY */ |
| 57a12720 | 63 | |
| 57a12720 TL |
64 | # define CONFIG_IPADDR 192.162.1.2 |
| 65 | # define CONFIG_NETMASK 255.255.255.0 | |
| 66 | # define CONFIG_SERVERIP 192.162.1.1 | |
| 67 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
| 57a12720 TL |
68 | |
| 69 | #endif | |
| 70 | ||
| 71 | #ifdef CONFIG_CMD_USB | |
| 72 | # define CONFIG_USB_OHCI_NEW | |
| 57a12720 TL |
73 | |
| 74 | # ifndef CONFIG_CMD_PCI | |
| 75 | # define CONFIG_CMD_PCI | |
| 76 | # endif | |
| 77 | # define CONFIG_PCI_OHCI | |
| 78 | # define CONFIG_DOS_PARTITION | |
| 79 | ||
| 6d0f6bcf JCPV |
80 | # undef CONFIG_SYS_USB_OHCI_BOARD_INIT |
| 81 | # undef CONFIG_SYS_USB_OHCI_CPU_INIT | |
| 82 | # define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 83 | # define CONFIG_SYS_USB_OHCI_SLOT_NAME "isp1561" | |
| 84 | # define CONFIG_SYS_OHCI_SWAP_REG_ACCESS | |
| 57a12720 TL |
85 | #endif |
| 86 | ||
| 87 | /* I2C */ | |
| 00f792e0 HS |
88 | #define CONFIG_SYS_I2C |
| 89 | #define CONFIG_SYS_I2C_FSL | |
| 90 | #define CONFIG_SYS_FSL_I2C_SPEED 80000 | |
| 91 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
| 92 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x00008F00 | |
| 6d0f6bcf | 93 | #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR |
| 57a12720 TL |
94 | |
| 95 | /* PCI */ | |
| 96 | #ifdef CONFIG_CMD_PCI | |
| 97 | #define CONFIG_PCI 1 | |
| 98 | #define CONFIG_PCI_PNP 1 | |
| f33fca22 | 99 | #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 |
| 57a12720 | 100 | |
| 6d0f6bcf | 101 | #define CONFIG_SYS_PCI_CACHE_LINE_SIZE 8 |
| 57a12720 | 102 | |
| 6d0f6bcf JCPV |
103 | #define CONFIG_SYS_PCI_MEM_BUS 0x80000000 |
| 104 | #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS | |
| 105 | #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 | |
| 57a12720 | 106 | |
| 6d0f6bcf JCPV |
107 | #define CONFIG_SYS_PCI_IO_BUS 0x71000000 |
| 108 | #define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS | |
| 109 | #define CONFIG_SYS_PCI_IO_SIZE 0x01000000 | |
| 57a12720 | 110 | |
| 6d0f6bcf JCPV |
111 | #define CONFIG_SYS_PCI_CFG_BUS 0x70000000 |
| 112 | #define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS | |
| 113 | #define CONFIG_SYS_PCI_CFG_SIZE 0x01000000 | |
| 57a12720 TL |
114 | #endif |
| 115 | ||
| 57a12720 TL |
116 | #define CONFIG_UDP_CHECKSUM |
| 117 | ||
| 118 | #ifdef CONFIG_MCFFEC | |
| 57a12720 TL |
119 | # define CONFIG_IPADDR 192.162.1.2 |
| 120 | # define CONFIG_NETMASK 255.255.255.0 | |
| 121 | # define CONFIG_SERVERIP 192.162.1.1 | |
| 122 | # define CONFIG_GATEWAYIP 192.162.1.1 | |
| 57a12720 TL |
123 | #endif /* FEC_ENET */ |
| 124 | ||
| 125 | #define CONFIG_HOSTNAME M547xEVB | |
| 126 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 127 | "netdev=eth0\0" \ | |
| 128 | "loadaddr=10000\0" \ | |
| 129 | "u-boot=u-boot.bin\0" \ | |
| 130 | "load=tftp ${loadaddr) ${u-boot}\0" \ | |
| 131 | "upd=run load; run prog\0" \ | |
| 132 | "prog=prot off bank 1;" \ | |
| 09933fb0 | 133 | "era ff800000 ff83ffff;" \ |
| 57a12720 TL |
134 | "cp.b ${loadaddr} ff800000 ${filesize};"\ |
| 135 | "save\0" \ | |
| 136 | "" | |
| 137 | ||
| 138 | #define CONFIG_PRAM 512 /* 512 KB */ | |
| 6d0f6bcf | 139 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 57a12720 TL |
140 | |
| 141 | #ifdef CONFIG_CMD_KGDB | |
| 6d0f6bcf | 142 | # define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 57a12720 | 143 | #else |
| 6d0f6bcf | 144 | # define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 57a12720 TL |
145 | #endif |
| 146 | ||
| 6d0f6bcf JCPV |
147 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 148 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 149 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 150 | #define CONFIG_SYS_LOAD_ADDR 0x00010000 | |
| 57a12720 | 151 | |
| 6d0f6bcf JCPV |
152 | #define CONFIG_SYS_CLK CONFIG_SYS_BUSCLK |
| 153 | #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 | |
| 57a12720 | 154 | |
| 6d0f6bcf JCPV |
155 | #define CONFIG_SYS_MBAR 0xF0000000 |
| 156 | #define CONFIG_SYS_INTSRAM (CONFIG_SYS_MBAR + 0x10000) | |
| 157 | #define CONFIG_SYS_INTSRAMSZ 0x8000 | |
| 57a12720 | 158 | |
| 6d0f6bcf | 159 | /*#define CONFIG_SYS_LATCH_ADDR (CONFIG_SYS_CS1_BASE + 0x80000)*/ |
| 57a12720 TL |
160 | |
| 161 | /* | |
| 162 | * Low Level Configuration Settings | |
| 163 | * (address mappings, register initial values, etc.) | |
| 164 | * You should know what you are doing if you make changes here. | |
| 165 | */ | |
| 166 | /*----------------------------------------------------------------------- | |
| 167 | * Definitions for initial stack pointer and data area (in DPRAM) | |
| 168 | */ | |
| 6d0f6bcf | 169 | #define CONFIG_SYS_INIT_RAM_ADDR 0xF2000000 |
| 553f0982 | 170 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in internal SRAM */ |
| 6d0f6bcf | 171 | #define CONFIG_SYS_INIT_RAM_CTRL 0x21 |
| 553f0982 | 172 | #define CONFIG_SYS_INIT_RAM1_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE) |
| 6d0f6bcf JCPV |
173 | #define CONFIG_SYS_INIT_RAM1_END 0x1000 /* End of used area in internal SRAM */ |
| 174 | #define CONFIG_SYS_INIT_RAM1_CTRL 0x21 | |
| 25ddd1fb | 175 | #define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10) |
| 6d0f6bcf | 176 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 57a12720 TL |
177 | |
| 178 | /*----------------------------------------------------------------------- | |
| 179 | * Start addresses for the final memory configuration | |
| 180 | * (Set up by the startup code) | |
| 6d0f6bcf | 181 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
| 57a12720 | 182 | */ |
| 6d0f6bcf JCPV |
183 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
| 184 | #define CONFIG_SYS_SDRAM_CFG1 0x73711630 | |
| 185 | #define CONFIG_SYS_SDRAM_CFG2 0x46770000 | |
| 186 | #define CONFIG_SYS_SDRAM_CTRL 0xE10B0000 | |
| 187 | #define CONFIG_SYS_SDRAM_EMOD 0x40010000 | |
| 188 | #define CONFIG_SYS_SDRAM_MODE 0x018D0000 | |
| 189 | #define CONFIG_SYS_SDRAM_DRVSTRENGTH 0x000002AA | |
| 190 | #ifdef CONFIG_SYS_DRAMSZ1 | |
| 191 | # define CONFIG_SYS_SDRAM_SIZE (CONFIG_SYS_DRAMSZ + CONFIG_SYS_DRAMSZ1) | |
| 57a12720 | 192 | #else |
| 6d0f6bcf | 193 | # define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_DRAMSZ |
| 57a12720 TL |
194 | #endif |
| 195 | ||
| 6d0f6bcf JCPV |
196 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 |
| 197 | #define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) | |
| 57a12720 | 198 | |
| 6d0f6bcf JCPV |
199 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) |
| 200 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
| 57a12720 | 201 | |
| 6d0f6bcf | 202 | #define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 |
| 57a12720 | 203 | |
| 09933fb0 JJ |
204 | /* Reserve 256 kB for malloc() */ |
| 205 | #define CONFIG_SYS_MALLOC_LEN (256 << 10) | |
| 57a12720 TL |
206 | /* |
| 207 | * For booting Linux, the board info and command line data | |
| 208 | * have to be in the first 8 MB of memory, since this is | |
| 209 | * the maximum mapped by the Linux kernel during initialization ?? | |
| 210 | */ | |
| 6d0f6bcf | 211 | #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) |
| 57a12720 TL |
212 | |
| 213 | /*----------------------------------------------------------------------- | |
| 214 | * FLASH organization | |
| 215 | */ | |
| 6d0f6bcf JCPV |
216 | #define CONFIG_SYS_FLASH_CFI |
| 217 | #ifdef CONFIG_SYS_FLASH_CFI | |
| 218 | # define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) | |
| 00b1883a | 219 | # define CONFIG_FLASH_CFI_DRIVER 1 |
| 6d0f6bcf JCPV |
220 | # define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
| 221 | # define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ | |
| 222 | # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ | |
| 223 | # define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
| 224 | #ifdef CONFIG_SYS_NOR1SZ | |
| 225 | # define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
| 226 | # define CONFIG_SYS_FLASH_SIZE ((CONFIG_SYS_NOR1SZ + CONFIG_SYS_BOOTSZ) << 20) | |
| 227 | # define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE } | |
| 57a12720 | 228 | #else |
| 6d0f6bcf JCPV |
229 | # define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
| 230 | # define CONFIG_SYS_FLASH_SIZE (CONFIG_SYS_BOOTSZ << 20) | |
| 57a12720 TL |
231 | #endif |
| 232 | #endif | |
| 233 | ||
| 234 | /* Configuration for environment | |
| 09933fb0 JJ |
235 | * Environment is not embedded in u-boot but at offset 0x40000 on the flash. |
| 236 | * First time runing may have env crc error warning if there is | |
| 237 | * no correct environment on the flash. | |
| 57a12720 | 238 | */ |
| 09933fb0 JJ |
239 | #define CONFIG_ENV_OFFSET 0x40000 |
| 240 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
| 5a1aceb0 | 241 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 57a12720 TL |
242 | |
| 243 | /*----------------------------------------------------------------------- | |
| 244 | * Cache Configuration | |
| 245 | */ | |
| 6d0f6bcf | 246 | #define CONFIG_SYS_CACHELINE_SIZE 16 |
| 57a12720 | 247 | |
| dd9f054e | 248 | #define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 553f0982 | 249 | CONFIG_SYS_INIT_RAM_SIZE - 8) |
| dd9f054e | 250 | #define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ |
| 553f0982 | 251 | CONFIG_SYS_INIT_RAM_SIZE - 4) |
| dd9f054e TL |
252 | #define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA + \ |
| 253 | CF_CACR_IDCM) | |
| 254 | #define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA) | |
| 255 | #define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \ | |
| 256 | CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ | |
| 257 | CF_ACR_EN | CF_ACR_SM_ALL) | |
| 258 | #define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_BCINVA | \ | |
| 259 | CF_CACR_IEC | CF_CACR_ICINVA) | |
| 260 | #define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \ | |
| 261 | CF_CACR_DEC | CF_CACR_DDCM_P | \ | |
| 262 | CF_CACR_DCINVA) & ~CF_CACR_ICINVA) | |
| 263 | ||
| 57a12720 TL |
264 | /*----------------------------------------------------------------------- |
| 265 | * Chipselect bank definitions | |
| 266 | */ | |
| 267 | /* | |
| 268 | * CS0 - NOR Flash 1, 2, 4, or 8MB | |
| 269 | * CS1 - NOR Flash | |
| 270 | * CS2 - Available | |
| 271 | * CS3 - Available | |
| 272 | * CS4 - Available | |
| 273 | * CS5 - Available | |
| 274 | */ | |
| 6d0f6bcf JCPV |
275 | #define CONFIG_SYS_CS0_BASE 0xFF800000 |
| 276 | #define CONFIG_SYS_CS0_MASK (((CONFIG_SYS_BOOTSZ << 20) - 1) & 0xFFFF0001) | |
| 277 | #define CONFIG_SYS_CS0_CTRL 0x00101980 | |
| 278 | ||
| 279 | #ifdef CONFIG_SYS_NOR1SZ | |
| 280 | #define CONFIG_SYS_CS1_BASE 0xE0000000 | |
| 281 | #define CONFIG_SYS_CS1_MASK (((CONFIG_SYS_NOR1SZ << 20) - 1) & 0xFFFF0001) | |
| 282 | #define CONFIG_SYS_CS1_CTRL 0x00101D80 | |
| 57a12720 TL |
283 | #endif |
| 284 | ||
| 285 | #endif /* _M5475EVB_H */ |