[people/ms/u-boot.git] / include / configs / MHPC.h

/*
 * (C) Copyright 2001
 * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
 *
 * (C) Copyright 2001
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * Configuation settings for the miniHiPerCam.
 *
 * -----------------------------------------------------------------
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_MHPC		1	/* on a miniHiPerCam		*/
#define CONFIG_BOARD_EARLY_INIT_F 1	/* do special hardware init.	*/
#define CONFIG_MISC_INIT_R	1

#define CONFIG_8xx_GCLK_FREQ	MPC8XX_SPEED
#undef	CONFIG_8xx_CONS_SMC1
#define CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		9600
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/

#define CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ETHADDR		00:00:5b:ee:de:ad

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND	\
	"bootp;"								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

#undef	CONFIG_UCODE_PATCH

/* enable I2C and select the hardware/software driver */
#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
#define CONFIG_SOFT_I2C		1	/* I2C bit-banged		*/
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL		0x00000020	/* PB 26 */
#define PB_SDA		0x00000010	/* PB 27 */

#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
			else	immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY	udelay(5)	/* 1/4 I2C clock duration */

#define CFG_I2C_SPEED			50000
#define CFG_I2C_SLAVE			0xFE
#define CFG_I2C_EEPROM_ADDR		0x50	/* EEPROM X24C04		*/
#define CFG_I2C_EEPROM_ADDR_LEN		1	/* bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"	*/
#define CFG_I2C_EEPROM_ADDR_OVERFLOW	0x07
#define CFG_EEPROM_PAGE_WRITE_BITS	3
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10

#define LCD_VIDEO_ADDR		(SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
#define LCD_VIDEO_SIZE		SDRAM_RES_SIZE	/* 2MB */
#define LCD_VIDEO_COLS		640
#define LCD_VIDEO_ROWS		480
#define LCD_VIDEO_FG		255
#define LCD_VIDEO_BG		0

#undef	CONFIG_VIDEO				/* test only ! s.a devices.c and 8xx */
#define CONFIG_CFB_CONSOLE			/* framebuffer console with std input */
#define CONFIG_VIDEO_LOGO

#define VIDEO_KBD_INIT_FCT	0		/* no KBD dev on MHPC - use serial */
#define VIDEO_TSTC_FCT		serial_tstc
#define VIDEO_GETC_FCT		serial_getc

#define CONFIG_BR0_WORKAROUND	1


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_ELF
#define CONFIG_CMD_I2C
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_REGINFO


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE


/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define CFG_LOAD_ADDR		0x300000	/* default load address */

#define CFG_HZ			1000		/* decrementer freq: 1 ms ticks */

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Physical memory map
 */
#define CFG_IMMR		0xFFF00000 /* Internal Memory Mapped Register*/

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xfe000000

#define CFG_MONITOR_LEN		0x40000		/* Reserve 256 kB for Monitor	*/
#undef	CFG_MONITOR_BASE		    /* to run U-Boot from RAM */
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * JFFS2 partitions
 *
 */
/* No command line, one static partition, whole device */
#undef CONFIG_JFFS2_CMDLINE
#define CONFIG_JFFS2_DEV		"nor0"
#define CONFIG_JFFS2_PART_SIZE		0xFFFFFFFF
#define CONFIG_JFFS2_PART_OFFSET	0x00000000

/* mtdparts command line support */
/* Note: fake mtd_id used, no linux mtd map file */
/*
#define CONFIG_JFFS2_CMDLINE
#define MTDIDS_DEFAULT		"nor0=mhpc-0"
#define MTDPARTS_DEFAULT	"mtdparts=mhpc-0:-(jffs2)"
*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map- for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	64	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
#define CONFIG_ENV_IS_IN_FLASH	1
#define CFG_ENV_OFFSET		CFG_MONITOR_LEN /* Offset of Environment */
#define CFG_ENV_SIZE		0x20000 /* Total Size of Environment	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CFG_SIUMCR	(SIUMCR_SEME)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF | PISCR_PTE)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		12-18
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit - leave PLL multiplication factor unchanged !
 */
#define MPC8XX_SPEED	50000000L
#define MPC8XX_XIN	5000000L      /* ref clk */
#define MPC8XX_FACT	(MPC8XX_SPEED/MPC8XX_XIN)
#define CFG_PLPRCR	(((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
			PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */

#define SCCR_MASK	(SCCR_RTDIV | SCCR_RTSEL)     /* SCCR_EBDF11 */
#define CFG_SCCR	(SCCR_TBS | SCCR_DFLCD001)


/*-----------------------------------------------------------------------
 * MAMR settings for SDRAM	- 16-14
 * => 0xC080200F
 *-----------------------------------------------------------------------
 * periodic timer for refresh
 */
#define CFG_MAMR_PTA	0xC0
#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)

/*
 * BR0 and OR0 (FLASH) used to re-map FLASH
 */

/* allow for max 8 MB of Flash */
#define FLASH_BASE		0xFE000000	/* FLASH bank #0*/
#define FLASH_BASE0_PRELIM	0xFE000000	/* FLASH bank #0*/
#define CFG_REMAP_OR_AM		0xFF800000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */

#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )

/*
 * BR1 and OR1 (SDRAM)
 */
#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define SDRAM_MAX_SIZE		0x01000000	/* max 16 MB		*/
#define SDRAM_RES_SIZE		0x00200000	/* 2 MB for framebuffer */

/* SDRAM timing: drive GPL5 high on first cycle */
#define CFG_OR_TIMING_SDRAM	(OR_G5LS)

#define CFG_OR1_PRELIM	((~(SDRAM_MAX_SIZE)+1)| CFG_OR_TIMING_SDRAM )
#define CFG_BR1_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

/*
 * BR2/OR2 - DIMM
 */
#define CFG_OR2		(OR_ACS_DIV4)
#define CFG_BR2		(BR_MS_UPMA)

/*
 * BR3/OR3 - DIMM
 */
#define CFG_OR3		(OR_ACS_DIV4)
#define CFG_BR3		(BR_MS_UPMA)

/*
 * BR4/OR4
 */
#define CFG_OR4		0
#define CFG_BR4		0

/*
 * BR5/OR5
 */
#define CFG_OR5		0
#define CFG_BR5		0

/*
 * BR6/OR6
 */
#define CFG_OR6		0
#define CFG_BR6		0

/*
 * BR7/OR7
 */
#define CFG_OR7		0
#define CFG_BR7		0


/*-----------------------------------------------------------------------
 * Debug Entry Mode
 *-----------------------------------------------------------------------
 *
 */
#define CFG_DER 0

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
e2211743 WD	1	/*
	2	* (C) Copyright 2001
	3	* Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
	4	*
	5	* (C) Copyright 2001
	6	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	7	*
	8	* Configuation settings for the miniHiPerCam.
	9	*
	10	* -----------------------------------------------------------------
	11	* See file CREDITS for list of people who contributed to this
	12	* project.
	13	*
	14	* This program is free software; you can redistribute it and/or
	15	* modify it under the terms of the GNU General Public License as
	16	* published by the Free Software Foundation; either version 2 of
	17	* the License, or (at your option) any later version.
	18	*
	19	* This program is distributed in the hope that it will be useful,
	20	* but WITHOUT ANY WARRANTY; without even the implied warranty of
c837dcb1	21	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
e2211743 WD	22	* GNU General Public License for more details.
	23	*
	24	* You should have received a copy of the GNU General Public License
	25	* along with this program; if not, write to the Free Software
	26	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	27	* MA 02111-1307 USA
	28	*/
	29
	30	/*
	31	* board/config.h - configuration options, board specific
	32	*/
	33
	34	#ifndef __CONFIG_H
	35	#define __CONFIG_H
	36
	37	/*
	38	* High Level Configuration Options
	39	* (easy to change)
	40	*/
	41	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
c837dcb1 WD	42	#define CONFIG_MHPC 1 /* on a miniHiPerCam */
	43	#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
	44	#define CONFIG_MISC_INIT_R 1
e2211743 WD	45
	46	#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
	47	#undef CONFIG_8xx_CONS_SMC1
c837dcb1	48	#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
e2211743 WD	49	#undef CONFIG_8xx_CONS_NONE
	50	#define CONFIG_BAUDRATE 9600
	51	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	52
c837dcb1	53	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
e2211743	54
c837dcb1 WD	55	#define CONFIG_ENV_OVERWRITE 1
c837dcb1 WD	56	#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
e2211743	57
c837dcb1	58	#undef CONFIG_BOOTARGS
e2211743 WD	59	#define CONFIG_BOOTCOMMAND \
e2211743 WD	60	"bootp;" \
fe126d8b WD	61	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
fe126d8b WD	62	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
e2211743 WD	63	"bootm"
	64
	65	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	66	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	67
	68	#undef CONFIG_WATCHDOG /* watchdog disabled */
c837dcb1	69	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
e2211743	70
c837dcb1	71	#undef CONFIG_UCODE_PATCH
e2211743 WD	72
e2211743 WD	73	/* enable I2C and select the hardware/software driver */
c837dcb1	74	#undef CONFIG_HARD_I2C /* I2C with hardware support */
e2211743 WD	75	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	76	/*
	77	* Software (bit-bang) I2C driver configuration
	78	*/
	79	#define PB_SCL 0x00000020 /* PB 26 */
	80	#define PB_SDA 0x00000010 /* PB 27 */
	81
	82	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	83	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	84	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	85	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	86	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
c837dcb1	87	else immr->im_cpm.cp_pbdat &= ~PB_SDA
e2211743	88	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
c837dcb1	89	else immr->im_cpm.cp_pbdat &= ~PB_SCL
e2211743 WD	90	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
e2211743 WD	91
c837dcb1 WD	92	#define CFG_I2C_SPEED 50000
	93	#define CFG_I2C_SLAVE 0xFE
	94	#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
	95	#define CFG_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
	96	/* mask of address bits that overflow into the "EEPROM chip address" */
	97	#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
	98	#define CFG_EEPROM_PAGE_WRITE_BITS 3
	99	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
	100
	101	#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
	102	#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
	103	#define LCD_VIDEO_COLS 640
	104	#define LCD_VIDEO_ROWS 480
	105	#define LCD_VIDEO_FG 255
	106	#define LCD_VIDEO_BG 0
	107
	108	#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
	109	#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
e2211743 WD	110	#define CONFIG_VIDEO_LOGO
e2211743 WD	111
c837dcb1 WD	112	#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
	113	#define VIDEO_TSTC_FCT serial_tstc
	114	#define VIDEO_GETC_FCT serial_getc
e2211743	115
c837dcb1	116	#define CONFIG_BR0_WORKAROUND 1
e2211743	117
e2211743	118
8353e139 JL	119	/*
	120	* Command line configuration.
	121	*/
	122	#include <config_cmd_default.h>
e2211743	123
8353e139 JL	124	#define CONFIG_CMD_DATE
	125	#define CONFIG_CMD_EEPROM
	126	#define CONFIG_CMD_ELF
	127	#define CONFIG_CMD_I2C
	128	#define CONFIG_CMD_JFFS2
	129	#define CONFIG_CMD_REGINFO
	130
	131
7be044e4 JL	132	/*
	133	* BOOTP options
	134	*/
	135	#define CONFIG_BOOTP_SUBNETMASK
	136	#define CONFIG_BOOTP_GATEWAY
	137	#define CONFIG_BOOTP_HOSTNAME
	138	#define CONFIG_BOOTP_BOOTPATH
	139	#define CONFIG_BOOTP_BOOTFILESIZE
	140
e2211743 WD	141
	142	/*
	143	* Miscellaneous configurable options
	144	*/
c837dcb1 WD	145	#define CFG_LONGHELP /* undef to save memory */
c837dcb1 WD	146	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
8353e139	147	#if defined(CONFIG_CMD_KGDB)
c837dcb1	148	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
e2211743	149	#else
c837dcb1	150	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
e2211743	151	#endif
c837dcb1 WD	152	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
c837dcb1 WD	153	#define CFG_MAXARGS 16 /* max number of command args */
e2211743 WD	154	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	155
	156	#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
	157	#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
	158
c837dcb1	159	#define CFG_LOAD_ADDR 0x300000 /* default load address */
e2211743	160
c837dcb1	161	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
e2211743 WD	162
	163	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	164
	165	/*
	166	* Low Level Configuration Settings
	167	* (address mappings, register initial values, etc.)
	168	* You should know what you are doing if you make changes here.
	169	*/
	170
	171	/*-----------------------------------------------------------------------
	172	* Physical memory map
	173	*/
	174	#define CFG_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
	175
	176	/*-----------------------------------------------------------------------
	177	* Definitions for initial stack pointer and data area (in DPRAM)
	178	*/
	179	#define CFG_INIT_RAM_ADDR CFG_IMMR
c837dcb1 WD	180	#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	181	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	182	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	183	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
e2211743 WD	184
	185	/*-----------------------------------------------------------------------
	186	* Start addresses for the final memory configuration
	187	* (Set up by the startup code)
	188	* Please note that CFG_SDRAM_BASE _must_ start at 0
	189	*/
c837dcb1	190	#define CFG_SDRAM_BASE 0x00000000
e2211743 WD	191	#define CFG_FLASH_BASE 0xfe000000
e2211743 WD	192
c837dcb1 WD	193	#define CFG_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
c837dcb1 WD	194	#undef CFG_MONITOR_BASE /* to run U-Boot from RAM */
e2211743	195	#define CFG_MONITOR_BASE CFG_FLASH_BASE
c837dcb1	196	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
e2211743	197
700a0c64 WD	198	/*
	199	* JFFS2 partitions
	200	*
	201	*/
	202	/* No command line, one static partition, whole device */
	203	#undef CONFIG_JFFS2_CMDLINE
	204	#define CONFIG_JFFS2_DEV "nor0"
	205	#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
	206	#define CONFIG_JFFS2_PART_OFFSET 0x00000000
	207
	208	/* mtdparts command line support */
	209	/* Note: fake mtd_id used, no linux mtd map file */
	210	/*
	211	#define CONFIG_JFFS2_CMDLINE
	212	#define MTDIDS_DEFAULT "nor0=mhpc-0"
	213	#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
	214	*/
e2211743 WD	215
	216	/*
	217	* For booting Linux, the board info and command line data
	218	* have to be in the first 8 MB of memory, since this is
	219	* the maximum mapped by the Linux kernel during initialization.
	220	*/
c837dcb1	221	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
e2211743 WD	222
	223	/*-----------------------------------------------------------------------
	224	* FLASH organization
	225	*/
	226	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	227	#define CFG_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
	228
	229	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	230	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
5a1aceb0	231	#define CONFIG_ENV_IS_IN_FLASH 1
c837dcb1 WD	232	#define CFG_ENV_OFFSET CFG_MONITOR_LEN /* Offset of Environment */
c837dcb1 WD	233	#define CFG_ENV_SIZE 0x20000 /* Total Size of Environment */
e2211743 WD	234
	235	/*-----------------------------------------------------------------------
	236	* Cache Configuration
	237	*/
	238	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
8353e139	239	#if defined(CONFIG_CMD_KGDB)
e2211743 WD	240	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	241	#endif
	242
	243	/*-----------------------------------------------------------------------
	244	* SYPCR - System Protection Control 11-9
	245	* SYPCR can only be written once after reset!
	246	*-----------------------------------------------------------------------
	247	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	248	*/
	249	#if defined(CONFIG_WATCHDOG)
	250	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	251	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	252	#else
	253	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
8bde7f77	254	SYPCR_SWP)
e2211743 WD	255	#endif
	256
	257	/*-----------------------------------------------------------------------
	258	* SIUMCR - SIU Module Configuration 11-6
	259	*-----------------------------------------------------------------------
	260	* PCMCIA config., multi-function pin tri-state
	261	*/
	262	#define CFG_SIUMCR (SIUMCR_SEME)
	263
	264	/*-----------------------------------------------------------------------
	265	* TBSCR - Time Base Status and Control 11-26
	266	*-----------------------------------------------------------------------
	267	* Clear Reference Interrupt Status, Timebase freezing enabled
	268	*/
	269	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
	270
	271	/*-----------------------------------------------------------------------
	272	* PISCR - Periodic Interrupt Status and Control 11-31
	273	*-----------------------------------------------------------------------
	274	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	275	*/
	276	#define CFG_PISCR (PISCR_PS \| PISCR_PITF \| PISCR_PTE)
	277
	278	/*-----------------------------------------------------------------------
	279	* RTCSC - Real-Time Clock Status and Control Register 12-18
	280	*-----------------------------------------------------------------------
	281	*/
	282	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
	283
	284	/*-----------------------------------------------------------------------
	285	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	286	*-----------------------------------------------------------------------
	287	* Reset PLL lock status sticky bit, timer expired status bit and timer
	288	* interrupt status bit - leave PLL multiplication factor unchanged !
	289	*/
	290	#define MPC8XX_SPEED 50000000L
c837dcb1	291	#define MPC8XX_XIN 5000000L /* ref clk */
e2211743 WD	292	#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
e2211743 WD	293	#define CFG_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) \| \
8bde7f77	294	PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
e2211743 WD	295
	296	/*-----------------------------------------------------------------------
	297	* SCCR - System Clock and reset Control Register 15-27
	298	*-----------------------------------------------------------------------
	299	* Set clock output, timebase and RTC source and divider,
	300	* power management and some other internal clocks
	301	*/
	302
	303	#define SCCR_MASK (SCCR_RTDIV \| SCCR_RTSEL) /* SCCR_EBDF11 */
	304	#define CFG_SCCR (SCCR_TBS \| SCCR_DFLCD001)
	305
	306
	307	/*-----------------------------------------------------------------------
	308	* MAMR settings for SDRAM - 16-14
	309	* => 0xC080200F
	310	*-----------------------------------------------------------------------
	311	* periodic timer for refresh
	312	*/
	313	#define CFG_MAMR_PTA 0xC0
	314	#define CFG_MAMR ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| MAMR_G0CLA_A11 \| MAMR_TLFA_MSK)
	315
	316	/*
	317	* BR0 and OR0 (FLASH) used to re-map FLASH
	318	*/
	319
	320	/* allow for max 8 MB of Flash */
	321	#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
	322	#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
	323	#define CFG_REMAP_OR_AM 0xFF800000 /* OR addr mask */
	324	#define CFG_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
	325
	326	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_BI \| OR_SCY_8_CLK) /* (OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| OR_SCY_6_CLK)*/
	327
	328	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
	329	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
	330	#define CFG_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) \| BR_PS_16 \| BR_MS_GPCM \| BR_V )
	331
	332	/*
	333	* BR1 and OR1 (SDRAM)
	334	*/
	335	#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
c837dcb1 WD	336	#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
c837dcb1 WD	337	#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
e2211743 WD	338
	339	/* SDRAM timing: drive GPL5 high on first cycle */
	340	#define CFG_OR_TIMING_SDRAM (OR_G5LS)
	341
	342	#define CFG_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)\| CFG_OR_TIMING_SDRAM )
	343	#define CFG_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
	344
	345	/*
	346	* BR2/OR2 - DIMM
	347	*/
	348	#define CFG_OR2 (OR_ACS_DIV4)
	349	#define CFG_BR2 (BR_MS_UPMA)
	350
	351	/*
	352	* BR3/OR3 - DIMM
	353	*/
	354	#define CFG_OR3 (OR_ACS_DIV4)
	355	#define CFG_BR3 (BR_MS_UPMA)
	356
	357	/*
	358	* BR4/OR4
	359	*/
	360	#define CFG_OR4 0
	361	#define CFG_BR4 0
	362
	363	/*
	364	* BR5/OR5
	365	*/
	366	#define CFG_OR5 0
	367	#define CFG_BR5 0
	368
	369	/*
	370	* BR6/OR6
	371	*/
	372	#define CFG_OR6 0
	373	#define CFG_BR6 0
	374
	375	/*
	376	* BR7/OR7
	377	*/
	378	#define CFG_OR7 0
	379	#define CFG_BR7 0
	380
	381
	382	/*-----------------------------------------------------------------------
	383	* Debug Entry Mode
	384	*-----------------------------------------------------------------------
	385	*
	386	*/
c837dcb1	387	#define CFG_DER 0
e2211743 WD	388
	389	/*
	390	* Internal Definitions
	391	*
	392	* Boot Flags
	393	*/
c837dcb1	394	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
e2211743 WD	395	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	396
	397	#endif /* __CONFIG_H */