[people/ms/u-boot.git] / include / configs / MIP405.h

/*
 * (C) Copyright 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/***********************************************************
 * High Level Configuration Options
 * (easy to change)
 ***********************************************************/
#define CONFIG_405GP		1	/* This is a PPC405 CPU		*/
#define CONFIG_4xx		1	/* ...member of PPC4xx family	*/
#define CONFIG_MIP405		1	/* ...on a MIP405 board		*/
/***********************************************************
 * Note that it may also be a MIP405T board which is a subset of the
 * MIP405
 ***********************************************************/
/***********************************************************
 * WARNING:
 * CONFIG_BOOT_PCI is only used for first boot-up and should
 * NOT be enabled for production bootloader
 ***********************************************************/
/*#define        CONFIG_BOOT_PCI         1*/       
/***********************************************************
 * Clock
 ***********************************************************/
#define CONFIG_SYS_CLK_FREQ	33000000 /* external frequency to pll   */

/***********************************************************
 * Command definitions
 ***********************************************************/
#define MIP405_COMMON_CMDS \
		       (CONFIG_CMD_DFL	| \
			CFG_CMD_IDE	| \
			CFG_CMD_DHCP	| \
			CFG_CMD_CACHE	| \
			CFG_CMD_PCI	| \
			CFG_CMD_IRQ	| \
			CFG_CMD_ECHO	| \
			CFG_CMD_EEPROM	| \
			CFG_CMD_I2C	| \
			CFG_CMD_REGINFO | \
			CFG_CMD_DATE	| \
			CFG_CMD_ELF	| \
			CFG_CMD_MII	| \
			CFG_CMD_SAVES	| \
			CFG_CMD_BSP	)

#if defined(CONFIG_MIP405T)
#define CONFIG_COMMANDS		\
			MIP405_COMMON_CMDS
#else
#define CONFIG_COMMANDS		\
			(MIP405_COMMON_CMDS | \
			CFG_CMD_USB	| \
			CFG_CMD_DOC	)

#endif

/* this must be included AFTER the definition of CONFIG_COMMANDS  (if any) */
#include <cmd_confdefs.h>

#define	 CFG_HUSH_PARSER
#define	 CFG_PROMPT_HUSH_PS2 "> "
/**************************************************************
 * I2C Stuff:
 * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
 * 0x53.
 * The Atmel EEPROM uses 16Bit addressing.
 ***************************************************************/

#define CONFIG_HARD_I2C			/* I2c with hardware support */
#define CFG_I2C_SPEED		50000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F

#define CFG_I2C_EEPROM_ADDR	0x53	/* EEPROM 24C128/256		*/
#define CFG_I2C_EEPROM_ADDR_LEN	2	/* Bytes of address		*/
/* mask of address bits that overflow into the "EEPROM chip address"    */
#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
#define CFG_EEPROM_PAGE_WRITE_BITS 6	/* The Atmel 24C128/256 has	*/
					/* 64 byte page write mode using*/
					/* last	6 bits of the address	*/
#define CFG_EEPROM_PAGE_WRITE_ENABLE	/* enable Page write */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */


#define CFG_ENV_IS_IN_EEPROM	1	/* use EEPROM for environment vars */
#define CFG_ENV_OFFSET		0x00000	/* environment starts at the beginning of the EEPROM */
#define CFG_ENV_SIZE		0x00800	/* 2k bytes may be used for env vars */

/***************************************************************
 * Definitions for Serial Presence Detect EEPROM address
 * (to get SDRAM settings)
 ***************************************************************/
/*#define SDRAM_EEPROM_WRITE_ADDRESS	0xA0
#define SDRAM_EEPROM_READ_ADDRESS 	0xA1
*/
/**************************************************************
 * Environment definitions
 **************************************************************/
#define CONFIG_BAUDRATE		9600	/* STD Baudrate */
#define CONFIG_BOOTDELAY	5
/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
#define CONFIG_BOOT_RETRY_TIME	-10	/* feature is avaiable but not enabled */
#define CONFIG_ZERO_BOOTDELAY_CHECK  	/* check console even if bootdelay = 0 */

#define CONFIG_BOOTCOMMAND	"diskboot 400000 0:1; bootm" /* autoboot command		*/
#define CONFIG_BOOTARGS		"console=ttyS0,9600 root=/dev/hda5" /* boot arguments */

#define CONFIG_IPADDR		10.0.0.100
#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_PREBOOT
/***************************************************************
 * defines if the console is stored in the environment
 ***************************************************************/
#define CFG_CONSOLE_IS_IN_ENV	/* stdin, stdout and stderr are in evironment */
/***************************************************************
 * defines if an overwrite_console function exists
 *************************************************************/
#define CFG_CONSOLE_OVERWRITE_ROUTINE
#define CFG_CONSOLE_INFO_QUIET
/***************************************************************
 * defines if the overwrite_console should be stored in the
 * environment
 **************************************************************/
#undef CFG_CONSOLE_ENV_OVERWRITE

/**************************************************************
 * loads config
 *************************************************************/
#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define CONFIG_MISC_INIT_R
/***********************************************************
 * Miscellaneous configurable options
 **********************************************************/
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0C00000	/* 1 ... 12 MB in DRAM	*/

#undef	CFG_EXT_SERIAL_CLOCK	       /* no external serial clock used */
#define CFG_BASE_BAUD       916667

/* The following table includes the supported baudrates */
#define CFG_BAUDRATE_TABLE	\
	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
	 57600, 115200, 230400, 460800, 921600 }

#define CFG_LOAD_ADDR	0x400000	/* default load address */
#define CFG_EXTBDINFO	1		/* To use extended board_into (bd_t) */

#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
#define PCI_HOST_FORCE  1               /* configure as pci host        */
#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */

#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_HOST PCI_HOST_FORCE	/* configure as pci-host	*/
#define CONFIG_PCI_PNP			/* pci plug-and-play		*/
					/* resource configuration	*/
#define CFG_PCI_SUBSYS_VENDORID 0x0000	/* PCI Vendor ID: to-do!!!	*/
#define CFG_PCI_SUBSYS_DEVICEID 0x0000	/* PCI Device ID: to-do!!!	*/
#define CFG_PCI_PTM1LA	0x00000000	/* point to sdram		*/
#define CFG_PCI_PTM1MS	0x80000001	/* 2GB, enable hard-wired to 1	*/
#define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
#define CFG_PCI_PTM2LA	0x00000000	/* disabled			*/
#define CFG_PCI_PTM2MS	0x00000000	/* disabled			*/
#define CFG_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0xFFF80000
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define CFG_MONITOR_LEN		(512 * 1024)	/* Reserve 512 kB for Monitor	*/
#define CFG_MALLOC_LEN		(128 * 1024)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_DCACHE_SIZE		0x4000	/* For IBM 405GPr CPUs			*/
#define CFG_CACHELINE_SIZE	32	/* ...			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
#endif

/*
 * Init Memory Controller:
 */

#define FLASH_BASE0_PRELIM	0xFFC00000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0		/* FLASH bank #1	*/

#define CONFIG_BOARD_PRE_INIT

/* Peripheral Bus Mapping */
#define PER_PLD_ADDR		0xF4000000 /* smallest window is 1MByte 0x10 0000*/
#define PER_UART0_ADDR		0xF4100000 /* smallest window is 1MByte 0x10 0000*/
#define PER_UART1_ADDR		0xF4200000 /* smallest window is 1MByte 0x10 0000*/

#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
#define CONFIG_PORT_ADDR 	PER_PLD_ADDR + 5


/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in On Chip SRAM)
 */
#define CFG_TEMP_STACK_OCM      1
#define CFG_OCM_DATA_ADDR	0xF0000000
#define CFG_OCM_DATA_SIZE	0x1000
#define CFG_INIT_RAM_ADDR	CFG_OCM_DATA_ADDR 	/* inside of On Chip SRAM    */
#define CFG_INIT_RAM_END	CFG_OCM_DATA_SIZE	/* End of On Chip SRAM	       */
#define CFG_GBL_DATA_SIZE	64		/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/


/***********************************************************************
 * External peripheral base address
 ***********************************************************************/
#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000

/***********************************************************************
 * Last Stage Init
 ***********************************************************************/
#define CONFIG_LAST_STAGE_INIT
/************************************************************
 * Ethernet Stuff
 ***********************************************************/
#define CONFIG_MII		1	/* MII PHY management		*/
#define CONFIG_PHY_ADDR		1	/* PHY address			*/

/************************************************************
 * RTC
 ***********************************************************/
#define CONFIG_RTC_MC146818
#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/************************************************************
 * IDE/ATA stuff
 ************************************************************/
#if defined(CONFIG_MIP405T)
#define CFG_IDE_MAXBUS		1   /* MIP405T has only one IDE bus	*/
#else
#define CFG_IDE_MAXBUS		2   /* max. 2 IDE busses	*/
#endif

#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */

#define CFG_ATA_BASE_ADDR	CFG_ISA_IO_BASE_ADDRESS /* base address */
#define CFG_ATA_IDE0_OFFSET	0x01F0		/* ide0 offste */
#define CFG_ATA_IDE1_OFFSET	0x0170		/* ide1 offset */
#define CFG_ATA_DATA_OFFSET	0		/* data reg offset	*/
#define CFG_ATA_REG_OFFSET 	0		/* reg offset */
#define CFG_ATA_ALT_OFFSET	0x200		/* alternate register offset */

#undef	CONFIG_IDE_8xx_DIRECT      /* no pcmcia interface required */
#undef	CONFIG_IDE_LED	       /* no led for ide supported     */
#define CONFIG_IDE_RESET       /* reset for ide supported...	*/
#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */

/************************************************************
 * ATAPI support (experimental)
 ************************************************************/
#define CONFIG_ATAPI			/* enable ATAPI Support */

/************************************************************
 * SCSI support (experimental) only SYM53C8xx supported
 ************************************************************/
#undef CONFIG_SCSI_SYM53C8XX

#ifdef CONFIG_SCSI_SYM53C8XX
#define CFG_SCSI_MAX_LUN	8 /* number of supported LUNs */
#define CFG_SCSI_MAX_SCSI_ID	7 /* maximum SCSI ID (0..6) */
#define CFG_SCSI_MAX_DEVICE	CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
#define CFG_SCSI_SPIN_UP_TIME	2
#endif /* CONFIG_SCSI_SYM53C8XX */
/************************************************************
 * DISK Partition support
 ************************************************************/
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION
#define CONFIG_ISO_PARTITION /* Experimental */

/************************************************************
 * Disk-On-Chip configuration
 ************************************************************/
#define CFG_MAX_DOC_DEVICE	1	/* Max number of DOC devices		*/
#define CFG_DOC_SHORT_TIMEOUT
#define CFG_DOC_SUPPORT_2000
#define CFG_DOC_SUPPORT_MILLENNIUM
/************************************************************
 * Keyboard support
 ************************************************************/
#undef CONFIG_ISA_KEYBOARD

/************************************************************
 * Video support
 ************************************************************/
#define CONFIG_VIDEO			/*To enable video controller support */
#define CONFIG_VIDEO_CT69000
#define CONFIG_CFB_CONSOLE
#define CONFIG_VIDEO_LOGO
#define CONFIG_CONSOLE_EXTRA_INFO
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_SW_CURSOR
#undef CONFIG_VIDEO_ONBOARD
/************************************************************
 * USB support EXPERIMENTAL
 ************************************************************/
#if !defined(CONFIG_MIP405T)
#define CONFIG_USB_UHCI
#define CONFIG_USB_KEYBOARD
#define CONFIG_USB_STORAGE

/* Enable needed helper functions */
#define CFG_DEVICE_DEREGISTER		/* needs device_deregister */
#endif
/************************************************************
 * Debug support
 ************************************************************/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/************************************************************
 * Ident
 ************************************************************/

#define VERSION_TAG "released"
#if !defined(CONFIG_MIP405T)
#define CONFIG_ISO_STRING "MEV-10072-001"
#else
#define CONFIG_ISO_STRING "MEV-10082-001"
#endif

#if !defined(CONFIG_BOOT_PCI)
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
#else
#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
#endif


#endif	/* __CONFIG_H */
Commit	Line	Data
7d393aed WD	1	/*
	2	* (C) Copyright 2001, 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific
	26	*/
	27
	28	#ifndef __CONFIG_H
	29	#define __CONFIG_H
	30
	31	/***********************************************************
	32	* High Level Configuration Options
	33	* (easy to change)
	34	***********************************************************/
	35	#define CONFIG_405GP 1 /* This is a PPC405 CPU */
	36	#define CONFIG_4xx 1 /* ...member of PPC4xx family */
	37	#define CONFIG_MIP405 1 /* ...on a MIP405 board */
f3e0de60 WD	38	/***********************************************************
	39	* Note that it may also be a MIP405T board which is a subset of the
	40	* MIP405
	41	***********************************************************/
	42	/***********************************************************
	43	* WARNING:
	44	* CONFIG_BOOT_PCI is only used for first boot-up and should
	45	* NOT be enabled for production bootloader
	46	***********************************************************/
	47	/#define CONFIG_BOOT_PCI 1/
7d393aed WD	48	/***********************************************************
	49	* Clock
	50	***********************************************************/
	51	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	52
	53	/***********************************************************
	54	* Command definitions
	55	***********************************************************/
f3e0de60	56	#define MIP405_COMMON_CMDS \
7d393aed WD	57	(CONFIG_CMD_DFL \| \
	58	CFG_CMD_IDE \| \
	59	CFG_CMD_DHCP \| \
	60	CFG_CMD_CACHE \| \
	61	CFG_CMD_PCI \| \
	62	CFG_CMD_IRQ \| \
	63	CFG_CMD_ECHO \| \
	64	CFG_CMD_EEPROM \| \
	65	CFG_CMD_I2C \| \
	66	CFG_CMD_REGINFO \| \
	67	CFG_CMD_DATE \| \
	68	CFG_CMD_ELF \| \
7d393aed	69	CFG_CMD_MII \| \
7d393aed WD	70	CFG_CMD_SAVES \| \
	71	CFG_CMD_BSP )
	72
f3e0de60 WD	73	#if defined(CONFIG_MIP405T)
	74	#define CONFIG_COMMANDS \
	75	MIP405_COMMON_CMDS
	76	#else
	77	#define CONFIG_COMMANDS \
	78	(MIP405_COMMON_CMDS \| \
	79	CFG_CMD_USB \| \
	80	CFG_CMD_DOC )
	81
	82	#endif
	83
7d393aed WD	84	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	85	#include <cmd_confdefs.h>
	86
	87	#define CFG_HUSH_PARSER
	88	#define CFG_PROMPT_HUSH_PS2 "> "
	89	/**************************************************************
	90	* I2C Stuff:
	91	* the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address
	92	* 0x53.
	93	* The Atmel EEPROM uses 16Bit addressing.
	94	***************************************************************/
	95
	96	#define CONFIG_HARD_I2C /* I2c with hardware support */
	97	#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */
	98	#define CFG_I2C_SLAVE 0x7F
	99
	100	#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */
	101	#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
	102	/* mask of address bits that overflow into the "EEPROM chip address" */
	103	#undef CFG_I2C_EEPROM_ADDR_OVERFLOW
	104	#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */
	105	/* 64 byte page write mode using*/
	106	/* last 6 bits of the address */
	107	#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */
	108	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
	109
	110
	111	#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */
	112	#define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */
	113	#define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */
	114
	115	/***************************************************************
	116	* Definitions for Serial Presence Detect EEPROM address
	117	* (to get SDRAM settings)
	118	***************************************************************/
f3e0de60	119	/*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0
7d393aed	120	#define SDRAM_EEPROM_READ_ADDRESS 0xA1
f3e0de60	121	*/
7d393aed WD	122	/**************************************************************
	123	* Environment definitions
	124	**************************************************************/
	125	#define CONFIG_BAUDRATE 9600 /* STD Baudrate */
	126	#define CONFIG_BOOTDELAY 5
	127	/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */
	128	#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */
	129	#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */
	130
3e38691e	131	#define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */
7d393aed WD	132	#define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */
	133
	134	#define CONFIG_IPADDR 10.0.0.100
	135	#define CONFIG_SERVERIP 10.0.0.1
	136	#define CONFIG_PREBOOT
	137	/***************************************************************
	138	* defines if the console is stored in the environment
	139	***************************************************************/
	140	#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */
	141	/***************************************************************
	142	* defines if an overwrite_console function exists
	143	*************************************************************/
	144	#define CFG_CONSOLE_OVERWRITE_ROUTINE
	145	#define CFG_CONSOLE_INFO_QUIET
	146	/***************************************************************
	147	* defines if the overwrite_console should be stored in the
	148	* environment
	149	**************************************************************/
	150	#undef CFG_CONSOLE_ENV_OVERWRITE
	151
	152	/**************************************************************
	153	* loads config
	154	*************************************************************/
	155	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	156	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	157
	158	#define CONFIG_MISC_INIT_R
	159	/***********************************************************
	160	* Miscellaneous configurable options
	161	**********************************************************/
	162	#define CFG_LONGHELP /* undef to save memory */
	163	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	164	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	165	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	166	#else
	167	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	168	#endif
	169	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	170	#define CFG_MAXARGS 16 /* max number of command args */
	171	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	172
	173	#define CFG_MEMTEST_START 0x0100000 /* memtest works on */
	174	#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */
	175
	176	#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
	177	#define CFG_BASE_BAUD 916667
	178
	179	/* The following table includes the supported baudrates */
	180	#define CFG_BAUDRATE_TABLE \
	181	{ 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
	182	57600, 115200, 230400, 460800, 921600 }
	183
3e38691e	184	#define CFG_LOAD_ADDR 0x400000 /* default load address */
7d393aed WD	185	#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
	186
	187	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	188
	189	/*-----------------------------------------------------------------------
	190	* PCI stuff
	191	*-----------------------------------------------------------------------
	192	*/
	193	#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
	194	#define PCI_HOST_FORCE 1 /* configure as pci host */
	195	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	196
	197	#define CONFIG_PCI /* include pci support */
	198	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */
	199	#define CONFIG_PCI_PNP /* pci plug-and-play */
	200	/* resource configuration */
	201	#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
	202	#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
	203	#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
	204	#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	205	#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	206	#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
	207	#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
	208	#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
	209
	210	/*-----------------------------------------------------------------------
	211	* Start addresses for the final memory configuration
	212	* (Set up by the startup code)
	213	* Please note that CFG_SDRAM_BASE _must_ start at 0
	214	*/
	215	#define CFG_SDRAM_BASE 0x00000000
	216	#define CFG_FLASH_BASE 0xFFF80000
	217	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	218	#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */
	219	#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
	220
	221	/*
	222	* For booting Linux, the board info and command line data
	223	* have to be in the first 8 MB of memory, since this is
	224	* the maximum mapped by the Linux kernel during initialization.
	225	*/
	226	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	227	/*-----------------------------------------------------------------------
	228	* FLASH organization
	229	*/
	230	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	231	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	232
	233	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	234	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
	235
	236	/*-----------------------------------------------------------------------
	237	* Cache Configuration
	238	*/
33149b88	239	#define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */
7d393aed WD	240	#define CFG_CACHELINE_SIZE 32 /* ... */
	241	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	242	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	243	#endif
	244
	245	/*
	246	* Init Memory Controller:
	247	*/
	248
	249	#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
	250	#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */
	251
	252	#define CONFIG_BOARD_PRE_INIT
	253
	254	/* Peripheral Bus Mapping */
	255	#define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/
	256	#define PER_UART0_ADDR 0xF4100000 /* smallest window is 1MByte 0x10 0000*/
	257	#define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/
	258
	259	#define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000
	260	#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5
	261
	262
	263
	264	/*-----------------------------------------------------------------------
	265	* Definitions for initial stack pointer and data area (in On Chip SRAM)
	266	*/
	267	#define CFG_TEMP_STACK_OCM 1
	268	#define CFG_OCM_DATA_ADDR 0xF0000000
	269	#define CFG_OCM_DATA_SIZE 0x1000
	270	#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */
	271	#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */
	272	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	273	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	274	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	275
	276	/*
	277	* Internal Definitions
	278	*
	279	* Boot Flags
	280	*/
	281	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	282	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	283
	284
	285	/***********************************************************************
	286	* External peripheral base address
	287	***********************************************************************/
	288	#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
	289
	290	/***********************************************************************
	291	* Last Stage Init
	292	***********************************************************************/
	293	#define CONFIG_LAST_STAGE_INIT
	294	/************************************************************
	295	* Ethernet Stuff
	296	***********************************************************/
	297	#define CONFIG_MII 1 /* MII PHY management */
	298	#define CONFIG_PHY_ADDR 1 /* PHY address */
	299
	300	/************************************************************
	301	* RTC
	302	***********************************************************/
	303	#define CONFIG_RTC_MC146818
304	#undef CONFIG_WATCHDOG /* watchdog disabled */
305
306	/************************************************************
307	* IDE/ATA stuff
308	************************************************************/
f3e0de60 WD	309	#if defined(CONFIG_MIP405T)
	310	#define CFG_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */
	311	#else
7d393aed	312	#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
f3e0de60 WD	313	#endif
f3e0de60 WD	314
7d393aed WD	315	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS2) / max. 2 drives per IDE bus */
	316
	317	#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */
	318	#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */
	319	#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */
	320	#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */
	321	#define CFG_ATA_REG_OFFSET 0 /* reg offset */
	322	#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */
	323
	324	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	325	#undef CONFIG_IDE_LED /* no led for ide supported */
	326	#define CONFIG_IDE_RESET /* reset for ide supported... */
	327	#define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */
	328
	329	/************************************************************
	330	* ATAPI support (experimental)
	331	************************************************************/
	332	#define CONFIG_ATAPI /* enable ATAPI Support */
	333
	334	/************************************************************
	335	* SCSI support (experimental) only SYM53C8xx supported
	336	************************************************************/
	337	#undef CONFIG_SCSI_SYM53C8XX
	338
	339	#ifdef CONFIG_SCSI_SYM53C8XX
	340	#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */
	341	#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */
	342	#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */
	343	#define CFG_SCSI_SPIN_UP_TIME 2
	344	#endif /* CONFIG_SCSI_SYM53C8XX */
	345	/************************************************************
	346	* DISK Partition support
	347	************************************************************/
	348	#define CONFIG_DOS_PARTITION
	349	#define CONFIG_MAC_PARTITION
	350	#define CONFIG_ISO_PARTITION /* Experimental */
	351
	352	/************************************************************
	353	* Disk-On-Chip configuration
	354	************************************************************/
	355	#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
	356	#define CFG_DOC_SHORT_TIMEOUT
	357	#define CFG_DOC_SUPPORT_2000
	358	#define CFG_DOC_SUPPORT_MILLENNIUM
	359	/************************************************************
	360	* Keyboard support
	361	************************************************************/
	362	#undef CONFIG_ISA_KEYBOARD
	363
	364	/************************************************************
	365	* Video support
	366	************************************************************/
	367	#define CONFIG_VIDEO /To enable video controller support /
	368	#define CONFIG_VIDEO_CT69000
	369	#define CONFIG_CFB_CONSOLE
	370	#define CONFIG_VIDEO_LOGO
	371	#define CONFIG_CONSOLE_EXTRA_INFO
	372	#define CONFIG_VGA_AS_SINGLE_DEVICE
	373	#define CONFIG_VIDEO_SW_CURSOR
	374	#undef CONFIG_VIDEO_ONBOARD
	375	/************************************************************
	376	* USB support EXPERIMENTAL
	377	************************************************************/
f3e0de60	378	#if !defined(CONFIG_MIP405T)
7d393aed WD	379	#define CONFIG_USB_UHCI
	380	#define CONFIG_USB_KEYBOARD
	381	#define CONFIG_USB_STORAGE
	382
	383	/* Enable needed helper functions */
	384	#define CFG_DEVICE_DEREGISTER /* needs device_deregister */
f3e0de60	385	#endif
7d393aed WD	386	/************************************************************
	387	* Debug support
	388	************************************************************/
	389	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	390	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	391	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	392	#endif
	393
	394	/************************************************************
	395	* Ident
	396	************************************************************/
f3e0de60	397
7d393aed	398	#define VERSION_TAG "released"
f3e0de60 WD	399	#if !defined(CONFIG_MIP405T)
	400	#define CONFIG_ISO_STRING "MEV-10072-001"
	401	#else
	402	#define CONFIG_ISO_STRING "MEV-10082-001"
	403	#endif
	404
	405	#if !defined(CONFIG_BOOT_PCI)
	406	#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, " CONFIG_ISO_STRING " " VERSION_TAG
	407	#else
	408	#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, PCI_BOOT Version"
	409	#endif
7d393aed WD	410
	411
	412	#endif /* __CONFIG_H */