[people/ms/u-boot.git] / include / configs / MPC8308RDB.h

/*
 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
 *
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1 /* E300 family */
#define CONFIG_MPC83xx		1 /* MPC83xx family */
#define CONFIG_MPC8308		1 /* MPC8308 CPU specific */
#define CONFIG_MPC8308RDB	1 /* MPC8308RDB board specific */

#define CONFIG_MISC_INIT_R

/*
 * On-board devices
 *
 * TSEC1 is SoC TSEC
 * TSEC2 is VSC switch
 */
#define CONFIG_TSEC1
#define CONFIG_VSC7385_ENET

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN	33333333 /* in Hz */
#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN

/*
 * Hardware Reset Configuration Word
 * if CLKIN is 66.66MHz, then
 * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
 * We choose the A type silicon as default, so the core is 400Mhz.
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_SVCOD_DIV_2 |\
	HRCWL_CSB_TO_CLKIN_4X1 |\
	HRCWL_CORE_TO_CSB_3X1)
/*
 * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
 * in 8308's HRCWH according to the manual, but original Freescale's
 * code has them and I've expirienced some problems using the board
 * with BDI3000 attached when I've tried to set these bits to zero
 * (UART doesn't work after the 'reset run' command).
 */
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_RL_EXT_LEGACY |\
	HRCWH_TSEC1M_IN_RGMII |\
	HRCWH_TSEC2M_IN_RGMII |\
	HRCWH_BIG_ENDIAN)

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRH (\
	SICRH_ESDHC_A_SD |\
	SICRH_ESDHC_B_SD |\
	SICRH_ESDHC_C_SD |\
	SICRH_GPIO_A_TSEC2 |\
	SICRH_GPIO_B_TSEC2_GTX_CLK125 |\
	SICRH_IEEE1588_A_GPIO |\
	SICRH_USB |\
	SICRH_GTM_GPIO |\
	SICRH_IEEE1588_B_GPIO |\
	SICRH_ETSEC2_CRS |\
	SICRH_GPIOSEL_1 |\
	SICRH_TMROBI_V3P3 |\
	SICRH_TSOBI1_V2P5 |\
	SICRH_TSOBI2_V2P5)	/* 0x01b7d103 */
#define CONFIG_SYS_SICRL (\
	SICRL_SPI_PF0 |\
	SICRL_UART_PF0 |\
	SICRL_IRQ_PF0 |\
	SICRL_I2C2_PF0 |\
	SICRL_ETSEC1_GTX_CLK125)	/* 0x00000040 */

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * SERDES
 */
#define CONFIG_FSL_SERDES
#define CONFIG_FSL_SERDES1	0xe3000

/*
 * Arbiter Setup
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3 /* Arbiter pipeline depth is 4 */
#define CONFIG_SYS_ACR_RPTCNT	3 /* Arbiter repeat count is 4 */
#define CONFIG_SYS_SPCR_TSECEP	3 /* eTSEC emergency priority is highest */

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE		0x00000000 /* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
#define CONFIG_SYS_DDRCDR_VALUE	(DDRCDR_EN \
				| DDRCDR_PZ_LOZ \
				| DDRCDR_NZ_LOZ \
				| DDRCDR_ODT \
				| DDRCDR_Q_DRN)
				/* 0x7b880001 */
/*
 * Manually set up DDR parameters
 * consist of two chips HY5PS12621BFP-C4 from HYNIX
 */

#define CONFIG_SYS_DDR_SIZE		128 /* MB */

#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| 0x00010000  /* ODT_WR to CSn */ \
				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
				/* 0x80010102 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (6 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x27256222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (4 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x121048c5 */
#define CONFIG_SYS_DDR_INTERVAL	((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03600100 */
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_32_BE)
				/* 0x43080000 */

#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE		((0x0448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2		0x00000000

/*
 * Memory test
 */
#define CONFIG_SYS_MEMTEST_START	0x00001000 /* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x07f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE /* start of monitor */

#define CONFIG_SYS_MONITOR_LEN	(384 * 1024) /* Reserve 384 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(512 * 1024) /* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_END		0x1000 /* End of used area in RAM */
#define CONFIG_SYS_GBL_DATA_SIZE	0x100 /* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00040000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT

#define CONFIG_SYS_FLASH_BASE		0xFE000000 /* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		8 /* FLASH size is 8M */
#define CONFIG_SYS_FLASH_PROTECTION	1 /* Use h/w Flash protection. */

/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_8MB)

#define CONFIG_SYS_BR0_PRELIM	(\
		CONFIG_SYS_FLASH_BASE	/* Flash Base address */	|\
		(2 << BR_PS_SHIFT)	/* 16 bit port size */		|\
		BR_V)			/* valid */
#define CONFIG_SYS_OR0_PRELIM	((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
				| OR_UPM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX \
				| OR_GPCM_EHTR \
				| OR_GPCM_EAD)

#define CONFIG_SYS_MAX_FLASH_BANKS	1 /* number of banks */
/* 127 64KB sectors and 8 8KB top sectors per device */
#define CONFIG_SYS_MAX_FLASH_SECT	135

#define CONFIG_SYS_FLASH_ERASE_TOUT	60000 /* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500 /* Flash Write Timeout (ms) */

/*
 * NAND Flash on the Local Bus
 */
#define CONFIG_SYS_NAND_BASE		0xE0600000	/* 0xE0600000 */
#define CONFIG_SYS_BR1_PRELIM	( CONFIG_SYS_NAND_BASE \
				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
				| BR_PS_8		/* Port Size = 8 bit */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V )		/* valid */
#define CONFIG_SYS_OR1_PRELIM	( 0xFFFF8000		/* length 32K */ \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR )
				/* 0xFFFF8396 */

#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_NAND_BASE
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

#ifdef CONFIG_VSC7385_ENET
#define CONFIG_TSEC2
#define CONFIG_SYS_VSC7385_BASE		0xF0000000
#define CONFIG_SYS_BR2_PRELIM		0xf0000801 /* VSC7385 Base address */
#define CONFIG_SYS_OR2_PRELIM		0xfffe09ff /* VSC7385, 128K bytes*/
/* Access window base at VSC7385 base */
#define CONFIG_SYS_LBLAWBAR2_PRELIM	CONFIG_SYS_VSC7385_BASE
/* Access window size 128K */
#define CONFIG_SYS_LBLAWAR2_PRELIM	(LBLAWAR_EN | LBLAWAR_128KB)
/* The flash address and size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE		0xFE7FE000
#define CONFIG_VSC7385_IMAGE_SIZE	8192
#endif
/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR + 0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR + 0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "

/* Pass open firmware flat tree */
#define CONFIG_OF_LIBFDT	1
#define CONFIG_OF_BOARD_SETUP	1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/* I2C */
#define CONFIG_HARD_I2C		/* I2C with hardware support */
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED	400000 /* I2C speed and slave address */
#define CONFIG_SYS_I2C_SLAVE	0x7F
#define CONFIG_SYS_I2C_NOPROBES	{{0x51}} /* Don't probe these addrs */
#define CONFIG_SYS_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C2_OFFSET	0x3100


/*
 * Board info - revision and where boot from
 */
#define CONFIG_SYS_I2C_PCF8574A_ADDR	0x39

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1337	/* ds1339 on board, use ds1337 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68 /* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCIE1_BASE		0xA0000000
#define CONFIG_SYS_PCIE1_MEM_BASE	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xA0000000
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x10000000
#define CONFIG_SYS_PCIE1_CFG_BASE	0xB0000000
#define CONFIG_SYS_PCIE1_CFG_SIZE	0x01000000
#define CONFIG_SYS_PCIE1_IO_BASE	0x00000000
#define CONFIG_SYS_PCIE1_IO_PHYS	0xB1000000
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00800000

/* enable PCIE clock */
#define CONFIG_SYS_SCCR_PCIEXP1CM	1

#define CONFIG_PCI
#define CONFIG_PCIE

#define CONFIG_PCI_PNP		/* do pci plug-and-play */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957	/* Freescale */
#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1

/*
 * TSEC
 */
#define CONFIG_NET_MULTI
#define CONFIG_TSEC_ENET	/* TSEC ethernet support */
#define CONFIG_SYS_TSEC1_OFFSET	0x24000
#define CONFIG_SYS_TSEC1	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
#define CONFIG_SYS_TSEC2_OFFSET	0x25000
#define CONFIG_SYS_TSEC2	(CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)

/*
 * TSEC ethernet configuration
 */
#define CONFIG_MII		1 /* MII PHY management */
#define CONFIG_TSEC1_NAME	"eTSEC0"
#define CONFIG_TSEC2_NAME	"eTSEC1"
#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: eTSEC[0-1] */
#define CONFIG_ETHPRIME		"eTSEC0"

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + \
				 CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE	0x10000 /* 64K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_NET
#define CONFIG_CMD_PCI
#define CONFIG_CMD_PING

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR		0x2000000 /* default load address */
#define CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt */

#define CONFIG_SYS_CBSIZE	1024 /* Console I/O Buffer Size */

/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ		1000	/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* Initial Memory map for Linux */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE | \
				 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR | BATL_PP_10 | \
			BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \
					BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
					BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
					BATL_CACHEINHIBIT | \
					BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
					BATU_VS | BATU_VP)
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02 /* Software reboot */

/*
 * Environment Configuration
 */

#define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_BAUDRATE 115200

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

#define CONFIG_BOOTDELAY	5	/* -1 disables auto-boot */

#define xstr(s)	str(s)
#define str(s)	#s

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=${serverip}:${rootpath}\0"			\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off panic=1\0"			\
	"addtty=setenv bootargs ${bootargs}"				\
		" console=${consoledev},${baudrate}\0"			\
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0"		\
	"addmisc=setenv bootargs ${bootargs}\0"				\
	"kernel_addr=FE080000\0"					\
	"fdt_addr=FE280000\0"						\
	"ramdisk_addr=FE290000\0"					\
	"u-boot=mpc8308rdb/u-boot.bin\0"				\
	"kernel_addr_r=1000000\0"					\
	"fdt_addr_r=C00000\0"						\
	"hostname=mpc8308rdb\0"						\
	"bootfile=mpc8308rdb/uImage\0"					\
	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0"				\
	"rootpath=/opt/eldk-4.2/ppc_6xx\0"				\
	"flash_self=run ramargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"	\
	"flash_nfs=run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr} - ${fdt_addr}\0"			\
	"net_nfs=tftp ${kernel_addr_r} ${bootfile};"			\
		"tftp ${fdt_addr_r} ${fdtfile};"			\
		"run nfsargs addip addtty addmtd addmisc;"		\
		"bootm ${kernel_addr_r} - ${fdt_addr_r}\0"		\
	"bootcmd=run flash_self\0"					\
	"load=tftp ${loadaddr} ${u-boot}\0"				\
	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE)		\
		" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE)	\
		" +${filesize};cp.b ${fileaddr} "			\
		xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"		\
	"upd=run load update\0"						\

#endif	/* __CONFIG_H */
Commit	Line	Data
5fb17030 IY	1	/*
	2	* Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
	3	* Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
	4	*
	5	*
	6	* See file CREDITS for list of people who contributed to this
	7	* project.
	8	*
	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License as
	11	* published by the Free Software Foundation; either version 2 of
	12	* the License, or (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	22	* MA 02111-1307 USA
	23	*/
	24
	25	#ifndef __CONFIG_H
	26	#define __CONFIG_H
	27
	28	/*
	29	* High Level Configuration Options
	30	*/
	31	#define CONFIG_E300 1 /* E300 family */
	32	#define CONFIG_MPC83xx 1 /* MPC83xx family */
	33	#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */
	34	#define CONFIG_MPC8308RDB 1 /* MPC8308RDB board specific */
	35
	36	#define CONFIG_MISC_INIT_R
	37
	38	/*
	39	* On-board devices
	40	*
	41	* TSEC1 is SoC TSEC
	42	* TSEC2 is VSC switch
	43	*/
	44	#define CONFIG_TSEC1
	45	#define CONFIG_VSC7385_ENET
	46
	47	/*
	48	* System Clock Setup
	49	*/
	50	#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
	51	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	52
	53	/*
	54	* Hardware Reset Configuration Word
	55	* if CLKIN is 66.66MHz, then
	56	* CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz
	57	* We choose the A type silicon as default, so the core is 400Mhz.
	58	*/
	59	#define CONFIG_SYS_HRCW_LOW (\
	60	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	61	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	62	HRCWL_SVCOD_DIV_2 \|\
	63	HRCWL_CSB_TO_CLKIN_4X1 \|\
	64	HRCWL_CORE_TO_CSB_3X1)
65	/*
66	* There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits
67	* in 8308's HRCWH according to the manual, but original Freescale's
68	* code has them and I've expirienced some problems using the board
69	* with BDI3000 attached when I've tried to set these bits to zero
70	* (UART doesn't work after the 'reset run' command).
71	*/
72	#define CONFIG_SYS_HRCW_HIGH (\
73	HRCWH_PCI_HOST \|\
74	HRCWH_PCI1_ARBITER_ENABLE \|\
75	HRCWH_CORE_ENABLE \|\
76	HRCWH_FROM_0X00000100 \|\
77	HRCWH_BOOTSEQ_DISABLE \|\
78	HRCWH_SW_WATCHDOG_DISABLE \|\
79	HRCWH_ROM_LOC_LOCAL_16BIT \|\
80	HRCWH_RL_EXT_LEGACY \|\
81	HRCWH_TSEC1M_IN_RGMII \|\
82	HRCWH_TSEC2M_IN_RGMII \|\
83	HRCWH_BIG_ENDIAN)
84
85	/*
86	* System IO Config
87	*/
65ea7589 IY	88	#define CONFIG_SYS_SICRH (\
	89	SICRH_ESDHC_A_SD \|\
	90	SICRH_ESDHC_B_SD \|\
	91	SICRH_ESDHC_C_SD \|\
	92	SICRH_GPIO_A_TSEC2 \|\
	93	SICRH_GPIO_B_TSEC2_GTX_CLK125 \|\
	94	SICRH_IEEE1588_A_GPIO \|\
	95	SICRH_USB \|\
	96	SICRH_GTM_GPIO \|\
	97	SICRH_IEEE1588_B_GPIO \|\
	98	SICRH_ETSEC2_CRS \|\
	99	SICRH_GPIOSEL_1 \|\
	100	SICRH_TMROBI_V3P3 \|\
	101	SICRH_TSOBI1_V2P5 \|\
	102	SICRH_TSOBI2_V2P5) /* 0x01b7d103 */
	103	#define CONFIG_SYS_SICRL (\
	104	SICRL_SPI_PF0 \|\
	105	SICRL_UART_PF0 \|\
	106	SICRL_IRQ_PF0 \|\
	107	SICRL_I2C2_PF0 \|\
	108	SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */
5fb17030 IY	109
	110	/*
	111	* IMMR new address
	112	*/
	113	#define CONFIG_SYS_IMMR 0xE0000000
	114
	115	/*
	116	* SERDES
	117	*/
	118	#define CONFIG_FSL_SERDES
	119	#define CONFIG_FSL_SERDES1 0xe3000
	120
	121	/*
	122	* Arbiter Setup
	123	*/
	124	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
	125	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
	126	#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */
	127
	128	/*
	129	* DDR Setup
	130	*/
	131	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
	132	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
	133	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
	134	#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	135	#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
	136	\| DDRCDR_PZ_LOZ \
	137	\| DDRCDR_NZ_LOZ \
	138	\| DDRCDR_ODT \
	139	\| DDRCDR_Q_DRN)
	140	/* 0x7b880001 */
	141	/*
	142	* Manually set up DDR parameters
	143	* consist of two chips HY5PS12621BFP-C4 from HYNIX
	144	*/
	145
	146	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
	147
	148	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
	149	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
	150	\| 0x00010000 /* ODT_WR to CSn */ \
	151	\| CSCONFIG_ROW_BIT_13 \| CSCONFIG_COL_BIT_10)
	152	/* 0x80010102 */
	153	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
	154	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	155	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	156	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	157	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	158	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	159	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	160	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	161	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
	162	/* 0x00220802 */
	163	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	164	\| (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	165	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	166	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	167	\| (6 << TIMING_CFG1_REFREC_SHIFT) \
	168	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	169	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	170	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
	171	/* 0x27256222 */
	172	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
173	\| (4 << TIMING_CFG2_CPO_SHIFT) \
174	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
175	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
176	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
177	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
178	\| (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
179	/* 0x121048c5 */
180	#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \
181	\| (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
182	/* 0x03600100 */
183	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
184	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
185	\| SDRAM_CFG_32_BE)
186	/* 0x43080000 */
187
188	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */
189	#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
190	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
191	/* ODT 150ohm CL=3, AL=1 on SDRAM */
192	#define CONFIG_SYS_DDR_MODE2 0x00000000
193
194	/*
195	* Memory test
196	*/
197	#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */
198	#define CONFIG_SYS_MEMTEST_END 0x07f00000
199
200	/*
201	* The reserved memory
202	*/
203	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
204
205	#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
206	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
207
208	/*
209	* Initial RAM Base Address Setup
210	*/
211	#define CONFIG_SYS_INIT_RAM_LOCK 1
212	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
213	#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
214	#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */
215	#define CONFIG_SYS_GBL_DATA_OFFSET \
216	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
217
218	/*
219	* Local Bus Configuration & Clock Setup
220	*/
221	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
222	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
223	#define CONFIG_SYS_LBC_LBCR 0x00040000
224
225	/*
226	* FLASH on the Local Bus
227	*/
228	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
229	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
230	#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
231
232	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
233	#define CONFIG_SYS_FLASH_SIZE 8 /* FLASH size is 8M */
234	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
235
236	/* Window base at flash base */
237	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
65ea7589	238	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_8MB)
5fb17030 IY	239
	240	#define CONFIG_SYS_BR0_PRELIM (\
	241	CONFIG_SYS_FLASH_BASE /* Flash Base address */ \|\
	242	(2 << BR_PS_SHIFT) /* 16 bit port size */ \|\
	243	BR_V) /* valid */
	244	#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
	245	\| OR_UPM_XAM \
	246	\| OR_GPCM_CSNT \
	247	\| OR_GPCM_ACS_DIV2 \
	248	\| OR_GPCM_XACS \
	249	\| OR_GPCM_SCY_15 \
	250	\| OR_GPCM_TRLX \
	251	\| OR_GPCM_EHTR \
	252	\| OR_GPCM_EAD)
	253
	254	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	255	/* 127 64KB sectors and 8 8KB top sectors per device */
	256	#define CONFIG_SYS_MAX_FLASH_SECT 135
	257
	258	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	259	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	260
	261	/*
	262	* NAND Flash on the Local Bus
	263	*/
	264	#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
	265	#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_NAND_BASE \
	266	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	267	\| BR_PS_8 /* Port Size = 8 bit */ \
	268	\| BR_MS_FCM /* MSEL = FCM */ \
	269	\| BR_V ) /* valid */
	270	#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
	271	\| OR_FCM_CSCT \
	272	\| OR_FCM_CST \
	273	\| OR_FCM_CHT \
	274	\| OR_FCM_SCY_1 \
	275	\| OR_FCM_TRLX \
	276	\| OR_FCM_EHTR )
	277	/* 0xFFFF8396 */
	278
	279	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
65ea7589	280	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
5fb17030 IY	281
	282	#ifdef CONFIG_VSC7385_ENET
	283	#define CONFIG_TSEC2
	284	#define CONFIG_SYS_VSC7385_BASE 0xF0000000
	285	#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
	286	#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
	287	/* Access window base at VSC7385 base */
	288	#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE
	289	/* Access window size 128K */
65ea7589	290	#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN \| LBLAWAR_128KB)
5fb17030 IY	291	/* The flash address and size of the VSC7385 firmware image */
	292	#define CONFIG_VSC7385_IMAGE 0xFE7FE000
	293	#define CONFIG_VSC7385_IMAGE_SIZE 8192
	294	#endif
	295	/*
	296	* Serial Port
	297	*/
	298	#define CONFIG_CONS_INDEX 1
5fb17030 IY	299	#define CONFIG_SYS_NS16550
	300	#define CONFIG_SYS_NS16550_SERIAL
	301	#define CONFIG_SYS_NS16550_REG_SIZE 1
	302	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	303
	304	#define CONFIG_SYS_BAUDRATE_TABLE \
	305	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	306
	307	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
	308	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
	309
	310	/* Use the HUSH parser */
	311	#define CONFIG_SYS_HUSH_PARSER
	312	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	313
	314	/* Pass open firmware flat tree */
	315	#define CONFIG_OF_LIBFDT 1
	316	#define CONFIG_OF_BOARD_SETUP 1
	317	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	318
	319	/* I2C */
	320	#define CONFIG_HARD_I2C /* I2C with hardware support */
	321	#define CONFIG_FSL_I2C
	322	#define CONFIG_I2C_MULTI_BUS
	323	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
	324	#define CONFIG_SYS_I2C_SLAVE 0x7F
	325	#define CONFIG_SYS_I2C_NOPROBES {{0x51}} /* Don't probe these addrs */
	326	#define CONFIG_SYS_I2C_OFFSET 0x3000
	327	#define CONFIG_SYS_I2C2_OFFSET 0x3100
	328
	329
	330	/*
	331	* Board info - revision and where boot from
	332	*/
	333	#define CONFIG_SYS_I2C_PCF8574A_ADDR 0x39
	334
	335	/*
	336	* Config on-board RTC
	337	*/
	338	#define CONFIG_RTC_DS1337 /* ds1339 on board, use ds1337 rtc via i2c */
	339	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
	340
	341	/*
	342	* General PCI
	343	* Addresses are mapped 1-1.
	344	*/
	345	#define CONFIG_SYS_PCIE1_BASE 0xA0000000
	346	#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000
	347	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000
	348	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
	349	#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000
	350	#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000
	351	#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
	352	#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000
	353	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
	354
65ea7589 IY	355	/* enable PCIE clock */
65ea7589 IY	356	#define CONFIG_SYS_SCCR_PCIEXP1CM 1
5fb17030 IY	357
	358	#define CONFIG_PCI
	359	#define CONFIG_PCIE
	360
	361	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	362
	363	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
	364	#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
	365
	366	/*
	367	* TSEC
	368	*/
	369	#define CONFIG_NET_MULTI
	370	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
	371	#define CONFIG_SYS_TSEC1_OFFSET 0x24000
	372	#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
	373	#define CONFIG_SYS_TSEC2_OFFSET 0x25000
	374	#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
	375
	376	/*
	377	* TSEC ethernet configuration
	378	*/
	379	#define CONFIG_MII 1 /* MII PHY management */
	380	#define CONFIG_TSEC1_NAME "eTSEC0"
	381	#define CONFIG_TSEC2_NAME "eTSEC1"
	382	#define TSEC1_PHY_ADDR 2
	383	#define TSEC2_PHY_ADDR 1
	384	#define TSEC1_PHYIDX 0
	385	#define TSEC2_PHYIDX 0
	386	#define TSEC1_FLAGS TSEC_GIGABIT
	387	#define TSEC2_FLAGS TSEC_GIGABIT
	388
	389	/* Options are: eTSEC[0-1] */
	390	#define CONFIG_ETHPRIME "eTSEC0"
	391
	392	/*
	393	* Environment
	394	*/
	395	#define CONFIG_ENV_IS_IN_FLASH 1
	396	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \
	397	CONFIG_SYS_MONITOR_LEN)
	398	#define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
	399	#define CONFIG_ENV_SIZE 0x2000
	400	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
	401	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
	402
	403	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	404	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	405
	406	/*
	407	* BOOTP options
	408	*/
	409	#define CONFIG_BOOTP_BOOTFILESIZE
	410	#define CONFIG_BOOTP_BOOTPATH
	411	#define CONFIG_BOOTP_GATEWAY
	412	#define CONFIG_BOOTP_HOSTNAME
	413
	414	/*
	415	* Command line configuration.
	416	*/
	417	#include <config_cmd_default.h>
	418
	419	#define CONFIG_CMD_DATE
	420	#define CONFIG_CMD_DHCP
421	#define CONFIG_CMD_I2C
422	#define CONFIG_CMD_MII
423	#define CONFIG_CMD_NET
424	#define CONFIG_CMD_PCI
425	#define CONFIG_CMD_PING
426
427	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
428
429	/*
430	* Miscellaneous configurable options
431	*/
432	#define CONFIG_SYS_LONGHELP /* undef to save memory */
433	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
434	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
435
436	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
437
438	/* Print Buffer Size */
439	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
440	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
441	/* Boot Argument Buffer Size */
442	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
443	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
444
445	/*
446	* For booting Linux, the board info and command line data
9f530d59	447	* have to be in the first 256 MB of memory, since this is
5fb17030 IY	448	* the maximum mapped by the Linux kernel during initialization.
5fb17030 IY	449	*/
9f530d59	450	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
5fb17030 IY	451
	452	/*
	453	* Core HID Setup
	454	*/
	455	#define CONFIG_SYS_HID0_INIT 0x000000000
	456	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	457	HID0_ENABLE_INSTRUCTION_CACHE \| \
	458	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
	459	#define CONFIG_SYS_HID2 HID2_HBE
	460
	461	/*
	462	* MMU Setup
	463	*/
	464
	465	/* DDR: cache cacheable */
	466	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \| BATL_PP_10 \| \
	467	BATL_MEMCOHERENCE)
	468	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \| BATU_BL_128M \| \
	469	BATU_VS \| BATU_VP)
	470	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
	471	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
	472
	473	/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
	474	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \| BATL_PP_10 \| \
	475	BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	476	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \| BATU_BL_8M \| BATU_VS \| \
	477	BATU_VP)
	478	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
	479	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
	480
	481	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
	482	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_10 \| \
	483	BATL_MEMCOHERENCE)
	484	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \| BATU_BL_8M \| \
	485	BATU_VS \| BATU_VP)
	486	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \| BATL_PP_10 \| \
	487	BATL_CACHEINHIBIT \| \
	488	BATL_GUARDEDSTORAGE)
	489	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
	490
	491	/* Stack in dcache: cacheable, no memory coherence */
	492	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_10)
	493	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR \| BATU_BL_128K \| \
	494	BATU_VS \| BATU_VP)
	495	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	496	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
	497
	498	/*
	499	* Internal Definitions
	500	*
	501	* Boot Flags
	502	*/
	503	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	504	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	505
	506	/*
	507	* Environment Configuration
	508	*/
	509
	510	#define CONFIG_ENV_OVERWRITE
	511
	512	#if defined(CONFIG_TSEC_ENET)
	513	#define CONFIG_HAS_ETH0
	514	#define CONFIG_HAS_ETH1
515	#endif
516
517	#define CONFIG_BAUDRATE 115200
518
519	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
520
521	#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
522
523	#define xstr(s) str(s)
524	#define str(s) #s
525
526	#define CONFIG_EXTRA_ENV_SETTINGS \
527	"netdev=eth0\0" \
528	"consoledev=ttyS0\0" \
529	"nfsargs=setenv bootargs root=/dev/nfs rw " \
530	"nfsroot=${serverip}:${rootpath}\0" \
531	"ramargs=setenv bootargs root=/dev/ram rw\0" \
532	"addip=setenv bootargs ${bootargs} " \
533	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
534	":${hostname}:${netdev}:off panic=1\0" \
535	"addtty=setenv bootargs ${bootargs}" \
536	" console=${consoledev},${baudrate}\0" \
537	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
538	"addmisc=setenv bootargs ${bootargs}\0" \
539	"kernel_addr=FE080000\0" \
540	"fdt_addr=FE280000\0" \
541	"ramdisk_addr=FE290000\0" \
542	"u-boot=mpc8308rdb/u-boot.bin\0" \
543	"kernel_addr_r=1000000\0" \
544	"fdt_addr_r=C00000\0" \
545	"hostname=mpc8308rdb\0" \
546	"bootfile=mpc8308rdb/uImage\0" \
547	"fdtfile=mpc8308rdb/mpc8308rdb.dtb\0" \
548	"rootpath=/opt/eldk-4.2/ppc_6xx\0" \
549	"flash_self=run ramargs addip addtty addmtd addmisc;" \
550	"bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \
551	"flash_nfs=run nfsargs addip addtty addmtd addmisc;" \
552	"bootm ${kernel_addr} - ${fdt_addr}\0" \
553	"net_nfs=tftp ${kernel_addr_r} ${bootfile};" \
554	"tftp ${fdt_addr_r} ${fdtfile};" \
555	"run nfsargs addip addtty addmtd addmisc;" \
556	"bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \
557	"bootcmd=run flash_self\0" \
558	"load=tftp ${loadaddr} ${u-boot}\0" \
559	"update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \
560	" +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \
561	" +${filesize};cp.b ${fileaddr} " \
562	xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \
563	"upd=run load update\0" \
564
565	#endif /* __CONFIG_H */