[people/ms/u-boot.git] / include / configs / MPC8313ERDB.h

/*
 * Copyright (C) Freescale Semiconductor, Inc. 2006.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */
/*
 * mpc8313epb board configuration file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1
#define CONFIG_MPC83XX		1
#define CONFIG_MPC831X		1
#define CONFIG_MPC8313		1
#define CONFIG_MPC8313ERDB	1

#define CONFIG_PCI
#define CONFIG_83XX_GENERIC_PCI

#ifdef CFG_66MHZ
#define CONFIG_83XX_CLKIN	66666667	/* in Hz */
#elif defined(CFG_33MHZ)
#define CONFIG_83XX_CLKIN	33333333	/* in Hz */
#else
#error Unknown oscillator frequency.
#endif

#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN

#define CONFIG_BOARD_EARLY_INIT_F		/* call board_pre_init */

#define CFG_IMMR		0xE0000000

#define CFG_MEMTEST_START	0x00001000
#define CFG_MEMTEST_END		0x07f00000

/* Early revs of this board will lock up hard when attempting
 * to access the PMC registers, unless a JTAG debugger is
 * connected, or some resistor modifications are made.
 */
#define CFG_8313ERDB_BROKEN_PMC 1

#define CFG_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
#define CFG_ACR_RPTCNT		3	/* Arbiter repeat count (0-7) */

/*
 * DDR Setup
 */
#define CFG_DDR_BASE		0x00000000	/* DDR is system memory*/
#define CFG_SDRAM_BASE		CFG_DDR_BASE
#define CFG_DDR_SDRAM_BASE	CFG_DDR_BASE

/*
 * Manually set up DDR parameters, as this board does not
 * seem to have the SPD connected to I2C.
 */
#define CFG_DDR_SIZE		128		/* MB */
#define CFG_DDR_CONFIG		( CSCONFIG_EN | CSCONFIG_AP \
				| 0x00040000 /* TODO */ \
				| CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 )
				/* 0x80840102 */

#define CFG_DDR_TIMING_3	0x00000000
#define CFG_DDR_TIMING_0	( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
				| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
				| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
				| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
				| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
				| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
				| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
				| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
				/* 0x00220802 */
#define CFG_DDR_TIMING_1	( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
				| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
				| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
				| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
				| (13 << TIMING_CFG1_REFREC_SHIFT ) \
				| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
				| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
				| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
				/* 0x3935d322 */
#define CFG_DDR_TIMING_2	( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
				| (31 << TIMING_CFG2_CPO_SHIFT ) \
				| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
				| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
				| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
				| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
				/* 0x0f9048ca */ /* P9-45,may need tuning */
#define CFG_DDR_INTERVAL	( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
				| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
				/* 0x03200064 */
#if defined(CONFIG_DDR_2T_TIMING)
#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
				| SDRAM_CFG_2T_EN \
				| SDRAM_CFG_DBW_32 )
#else
#define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
				| SDRAM_CFG_32_BE )
				/* 0x43080000 */
#endif
#define CFG_SDRAM_CFG2		0x00401000;
/* set burst length to 8 for 32-bit data path */
#define CFG_DDR_MODE		( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
				| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
				/* 0x44400232 */
#define CFG_DDR_MODE_2		0x8000C000;

#define CFG_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
				/*0x02000000*/
#define CFG_DDRCDR_VALUE	( DDRCDR_EN \
				| DDRCDR_PZ_NOMZ \
				| DDRCDR_NZ_NOMZ \
				| DDRCDR_M_ODR )

/*
 * FLASH on the Local Bus
 */
#define CFG_FLASH_CFI				/* use the Common Flash Interface */
#define CFG_FLASH_CFI_DRIVER			/* use the CFI driver */
#define CFG_FLASH_BASE		0xFE000000	/* start of FLASH   */
#define CFG_FLASH_SIZE		8		/* flash size in MB */
#define CFG_FLASH_EMPTY_INFO			/* display empty sectors */
#define CFG_FLASH_USE_BUFFER_WRITE		/* buffer up multiple bytes */

#define CFG_BR0_PRELIM		(CFG_FLASH_BASE |	/* flash Base address */ \
				(2 << BR_PS_SHIFT) |	/* 16 bit port size */ \
				BR_V)			/* valid */
#define CFG_OR0_PRELIM		( 0xFF000000		/* 16 MByte */ \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_9 \
				| OR_GPCM_EHTR \
				| OR_GPCM_EAD )
				/* 0xFF006FF7	TODO SLOW 16 MB flash size */
#define CFG_LBLAWBAR0_PRELIM	CFG_FLASH_BASE	/* window base at flash base */
#define CFG_LBLAWAR0_PRELIM	0x80000017	/* 16 MB window size */

#define CFG_MAX_FLASH_BANKS	1		/* number of banks */
#define CFG_MAX_FLASH_SECT	135		/* sectors per device */

#define CFG_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CFG_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor */

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#endif

#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0xFD000000	/* Initial RAM address */
#define CFG_INIT_RAM_END	0x1000		/* End of used area in RAM*/

#define CFG_GBL_DATA_SIZE	0x100		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */

/*
 * Local Bus LCRR and LBCR regs
 */
#define CFG_LCRR	LCRR_EADC_1 | LCRR_CLKDIV_2	/* 0x00010002 */
#define CFG_LBC_LBCR	( 0x00040000 /* TODO */ \
			| (0xFF << LBCR_BMT_SHIFT) \
			| 0xF )	/* 0x0004ff0f */

#define CFG_LBC_MRTPR	0x20000000  /*TODO */ 	/* LB refresh timer prescal, 266MHz/32 */

/* drivers/nand/nand.c */
#define CFG_NAND_BASE		0xE2800000	/* 0xF0000000 */
#define CFG_MAX_NAND_DEVICE	1
#define NAND_MAX_CHIPS		1
#define CONFIG_MTD_NAND_VERIFY_WRITE

#define CFG_BR1_PRELIM		( CFG_NAND_BASE \
				| (2<<BR_DECC_SHIFT)	/* Use HW ECC */ \
				| BR_PS_8		/* Port Size = 8 bit */ \
				| BR_MS_FCM		/* MSEL = FCM */ \
				| BR_V )		/* valid */
#define CFG_OR1_PRELIM		( 0xFFFF8000		/* length 32K */ \
				| OR_FCM_CSCT \
				| OR_FCM_CST \
				| OR_FCM_CHT \
				| OR_FCM_SCY_1 \
				| OR_FCM_TRLX \
				| OR_FCM_EHTR )
				/* 0xFFFF8396 */
#define CFG_LBLAWBAR1_PRELIM	CFG_NAND_BASE
#define CFG_LBLAWAR1_PRELIM	0x8000000E	/* 32KB  */

#define CFG_VSC7385_BASE	0xF0000000

#define CONFIG_VSC7385_ENET			/* VSC7385 ethernet support */
#define CFG_BR2_PRELIM		0xf0000801	/* VSC7385 Base address */
#define CFG_OR2_PRELIM		0xfffe09ff	/* VSC7385, 128K bytes*/
#define CFG_LBLAWBAR2_PRELIM	CFG_VSC7385_BASE/* Access window base at VSC7385 base */
#define CFG_LBLAWAR2_PRELIM	0x80000010	/* Access window size 128K */

/* local bus read write buffer mapping */
#define CFG_BR3_PRELIM		0xFA000801	/* map at 0xFA000000 */
#define CFG_OR3_PRELIM		0xFFFF8FF7	/* 32kB */
#define CFG_LBLAWBAR3_PRELIM	0xFA000000
#define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */

/* pass open firmware flat tree */
#define CONFIG_OF_FLAT_TREE	1
#define CONFIG_OF_BOARD_SETUP	1

/* maximum size of the flat tree (8K) */
#define OF_FLAT_TREE_MAX_SIZE	8192

#define OF_CPU			"PowerPC,8313@0"
#define OF_SOC			"soc8313@e0000000"
#define OF_TBCLK		(bd->bi_busfreq / 4)
#define OF_STDOUT_PATH		"/soc8313@e0000000/serial@4500"

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CFG_NS16550_COM1	(CFG_IMMR+0x4500)
#define CFG_NS16550_COM2	(CFG_IMMR+0x4600)

/* Use the HUSH parser */
#define CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "

/* I2C */
#define CONFIG_HARD_I2C			/* I2C with hardware support*/
#define CONFIG_FSL_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_I2C_CMD_TREE
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address */
#define CFG_I2C_SLAVE		0x7F
#define CFG_I2C_NOPROBES	{0x69}	/* Don't probe these addrs */
#define CFG_I2C_OFFSET		0x3000
#define CFG_I2C2_OFFSET		0x3100

/* TSEC */
#define CFG_TSEC1_OFFSET	0x24000
#define CFG_TSEC1		(CFG_IMMR+CFG_TSEC1_OFFSET)
#define CFG_TSEC2_OFFSET	0x25000
#define CFG_TSEC2		(CFG_IMMR+CFG_TSEC2_OFFSET)
#define CONFIG_NET_MULTI

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CFG_PCI1_MMIO_BASE	0x90000000
#define CFG_PCI1_MMIO_PHYS	CFG_PCI1_MMIO_BASE
#define CFG_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CFG_PCI1_IO_BASE	0x00000000
#define CFG_PCI1_IO_PHYS	0xE2000000
#define CFG_PCI1_IO_SIZE	0x00100000	/* 1M */

#define CONFIG_PCI_PNP		/* do pci plug-and-play */
#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */

/*
 * TSEC configuration
 */
#define CONFIG_TSEC_ENET		/* TSEC ethernet support */

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI		1
#endif

#define CONFIG_GMII			1	/* MII PHY management */
#define CONFIG_TSEC1		1

#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR			0x1c
#define TSEC2_PHY_ADDR			4
#define TSEC1_PHYIDX			0
#define TSEC2_PHYIDX			0

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME			"TSEC1"

/*
 * Configure on-board RTC
 */
#define CONFIG_RTC_DS1337
#define CFG_I2C_RTC_ADDR		0x68

/*
 * Environment
 */
#ifndef CFG_RAMBOOT
	#define CFG_ENV_IS_IN_FLASH	1
	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE + 0x40000)
	#define CFG_ENV_SECT_SIZE	0x10000	/* 64K(one sector) for env */
	#define CFG_ENV_SIZE		0x2000

/* Address and size of Redundant Environment Sector */
#else
	#define CFG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
	#define CFG_ENV_ADDR		(CFG_MONITOR_BASE - 0x1000)
	#define CFG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

#define CFG_BASE_COMMANDS	( CONFIG_CMD_DFL	\
				| CFG_CMD_PING		\
				| CFG_CMD_DHCP		\
				| CFG_CMD_I2C		\
				| CFG_CMD_MII		\
				| CFG_CMD_DATE		\
				| CFG_CMD_PCI)

#define CONFIG_CMDLINE_EDITING 1

#define CFG_RAMBOOT_COMMANDS	(CFG_BASE_COMMANDS & \
				 ~(CFG_CMD_ENV | CFG_CMD_LOADS))

#if defined(CFG_RAMBOOT)
#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS
#else
#define CONFIG_COMMANDS CFG_BASE_COMMANDS
#endif

#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory */
#define CFG_LOAD_ADDR	0x2000000	/* default load address */
#define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size */

#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args */
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size */
#define CFG_HZ		1000		/* decrementer freq: 1ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ	(8 << 20)	/* Initial Memory map for Linux*/

/* Cache Configuration */
#define CFG_DCACHE_SIZE		16384
#define CFG_CACHELINE_SIZE	32
#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/

#define CFG_RCWH_PCIHOST 0x80000000	/* PCIHOST  */

#ifdef CFG_66MHZ

/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
/* 0x62040000 */
#define CFG_HRCW_LOW (\
	0x20000000 /* reserved, must be set */ |\
	HRCWL_DDRCM |\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_CSB_TO_CLKIN_2X1 |\
	HRCWL_CORE_TO_CSB_2X1)

#elif defined(CFG_33MHZ)

/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
/* 0x65040000 */
#define CFG_HRCW_LOW (\
	0x20000000 /* reserved, must be set */ |\
	HRCWL_DDRCM |\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_CSB_TO_CLKIN_5X1 |\
	HRCWL_CORE_TO_CSB_2X1)

#endif

/* 0xa0606c00 */
#define CFG_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_RL_EXT_LEGACY |\
	HRCWH_TSEC1M_IN_RGMII |\
	HRCWH_TSEC2M_IN_RGMII |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LALE_NORMAL)

/* System IO Config */
#define CFG_SICRH	(SICRH_TSOBI1 | SICRH_TSOBI2)	/* RGMII */
#define CFG_SICRL	SICRL_USBDR			/* Enable Internal USB Phy  */

#define CFG_HID0_INIT	0x000000000
#define CFG_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
			 HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)

#define CFG_HID2 HID2_HBE

/* DDR @ 0x00000000 */
#define CFG_IBAT0L	(CFG_SDRAM_BASE | BATL_PP_10)
#define CFG_IBAT0U	(CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* PCI @ 0x80000000 */
#define CFG_IBAT1L	(CFG_PCI1_MEM_BASE | BATL_PP_10)
#define CFG_IBAT1U	(CFG_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
#define CFG_IBAT2L	(CFG_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT2U	(CFG_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP)

/* PCI2 not supported on 8313 */
#define CFG_IBAT3L	(0)
#define CFG_IBAT3U	(0)
#define CFG_IBAT4L	(0)
#define CFG_IBAT4U	(0)

/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
#define CFG_IBAT5L	(CFG_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
#define CFG_IBAT5U	(CFG_IMMR | BATU_BL_256M | BATU_VS | BATU_VP)

/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
#define CFG_IBAT6L	(0xF0000000 | BATL_PP_10)
#define CFG_IBAT6U	(0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)

#define CFG_IBAT7L	(0)
#define CFG_IBAT7U	(0)

#define CFG_DBAT0L	CFG_IBAT0L
#define CFG_DBAT0U	CFG_IBAT0U
#define CFG_DBAT1L	CFG_IBAT1L
#define CFG_DBAT1U	CFG_IBAT1U
#define CFG_DBAT2L	CFG_IBAT2L
#define CFG_DBAT2U	CFG_IBAT2U
#define CFG_DBAT3L	CFG_IBAT3L
#define CFG_DBAT3U	CFG_IBAT3U
#define CFG_DBAT4L	CFG_IBAT4L
#define CFG_DBAT4U	CFG_IBAT4U
#define CFG_DBAT5L	CFG_IBAT5L
#define CFG_DBAT5U	CFG_IBAT5U
#define CFG_DBAT6L	CFG_IBAT6L
#define CFG_DBAT6U	CFG_IBAT6U
#define CFG_DBAT7L	CFG_IBAT7L
#define CFG_DBAT7U	CFG_IBAT7U

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01	/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02	/* Software reboot */

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_ETHADDR		00:E0:0C:00:95:01
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR		00:E0:0C:00:95:02

#define CONFIG_IPADDR		10.0.0.2
#define CONFIG_SERVERIP		10.0.0.1
#define CONFIG_GATEWAYIP	10.0.0.1
#define CONFIG_NETMASK		255.0.0.0
#define CONFIG_NETDEV		eth1

#define CONFIG_HOSTNAME		mpc8313erdb
#define CONFIG_ROOTPATH		/nfs/root/path
#define CONFIG_BOOTFILE		uImage
#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */
#define CONFIG_FDTFILE		mpc8313erdb.dtb

#define CONFIG_LOADADDR		200000	/* default location for tftp and bootm */
#define CONFIG_BOOTDELAY	-1	/* -1 disables auto-boot */
#define CONFIG_BAUDRATE		115200

#define XMK_STR(x)	#x
#define MK_STR(x)	XMK_STR(x)

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" MK_STR(CONFIG_NETDEV) "\0" 				\
	"ethprime=TSEC1\0"						\
	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" 				\
	"tftpflash=tftpboot $loadaddr $uboot; " 			\
		"protect off " MK_STR(TEXT_BASE) " +$filesize; " 	\
		"erase " MK_STR(TEXT_BASE) " +$filesize; " 		\
		"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " 	\
		"protect on " MK_STR(TEXT_BASE) " +$filesize; " 	\
		"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" 	\
	"fdtaddr=400000\0"						\
	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0"				\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"							\
	"run setipargs;"							\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#undef MK_STR
#undef XMK_STR

#endif	/* __CONFIG_H */
Commit	Line	Data
96b8a054 SW	1	/*
	2	* Copyright (C) Freescale Semiconductor, Inc. 2006.
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
96b8a054 SW	21	*/
	22	/*
	23	* mpc8313epb board configuration file
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/*
	30	* High Level Configuration Options
	31	*/
	32	#define CONFIG_E300 1
	33	#define CONFIG_MPC83XX 1
	34	#define CONFIG_MPC831X 1
	35	#define CONFIG_MPC8313 1
	36	#define CONFIG_MPC8313ERDB 1
	37
	38	#define CONFIG_PCI
	39	#define CONFIG_83XX_GENERIC_PCI
	40
	41	#ifdef CFG_66MHZ
5c5d3242	42	#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
96b8a054	43	#elif defined(CFG_33MHZ)
5c5d3242	44	#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
96b8a054 SW	45	#else
	46	#error Unknown oscillator frequency.
	47	#endif
	48
	49	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	50
	51	#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
	52
	53	#define CFG_IMMR 0xE0000000
	54
	55	#define CFG_MEMTEST_START 0x00001000
	56	#define CFG_MEMTEST_END 0x07f00000
	57
	58	/* Early revs of this board will lock up hard when attempting
	59	* to access the PMC registers, unless a JTAG debugger is
	60	* connected, or some resistor modifications are made.
	61	*/
	62	#define CFG_8313ERDB_BROKEN_PMC 1
	63
	64	#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
	65	#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
	66
	67	/*
	68	* DDR Setup
	69	*/
	70	#define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/
	71	#define CFG_SDRAM_BASE CFG_DDR_BASE
	72	#define CFG_DDR_SDRAM_BASE CFG_DDR_BASE
	73
	74	/*
	75	* Manually set up DDR parameters, as this board does not
	76	* seem to have the SPD connected to I2C.
	77	*/
	78	#define CFG_DDR_SIZE 128 /* MB */
	79	#define CFG_DDR_CONFIG ( CSCONFIG_EN \| CSCONFIG_AP \
	80	\| 0x00040000 /* TODO */ \
	81	\| CSCONFIG_ROW_BIT_13 \| CSCONFIG_COL_BIT_10 )
	82	/* 0x80840102 */
	83
	84	#define CFG_DDR_TIMING_3 0x00000000
	85	#define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \
	86	\| ( 0 << TIMING_CFG0_WRT_SHIFT ) \
	87	\| ( 0 << TIMING_CFG0_RRT_SHIFT ) \
	88	\| ( 0 << TIMING_CFG0_WWT_SHIFT ) \
	89	\| ( 2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \
	90	\| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \
	91	\| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \
	92	\| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) )
	93	/* 0x00220802 */
	94	#define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \
	95	\| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \
	96	\| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \
	97	\| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \
	98	\| (13 << TIMING_CFG1_REFREC_SHIFT ) \
	99	\| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \
	100	\| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \
	101	\| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) )
	102	/* 0x3935d322 */
	103	#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \
	104	\| (31 << TIMING_CFG2_CPO_SHIFT ) \
	105	\| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \
	106	\| ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \
	107	\| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \
	108	\| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \
109	\| (10 << TIMING_CFG2_FOUR_ACT_SHIFT) )
110	/* 0x0f9048ca / / P9-45,may need tuning */
111	#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \
112	\| ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) )
113	/* 0x03200064 */
114	#if defined(CONFIG_DDR_2T_TIMING)
115	#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
116	\| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
117	\| SDRAM_CFG_2T_EN \
118	\| SDRAM_CFG_DBW_32 )
119	#else
120	#define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \
121	\| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
122	\| SDRAM_CFG_32_BE )
123	/* 0x43080000 */
124	#endif
125	#define CFG_SDRAM_CFG2 0x00401000;
126	/* set burst length to 8 for 32-bit data path */
127	#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \
128	\| ( 0x0232 << SDRAM_MODE_SD_SHIFT ) )
129	/* 0x44400232 */
130	#define CFG_DDR_MODE_2 0x8000C000;
131
132	#define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
133	/0x02000000/
134	#define CFG_DDRCDR_VALUE ( DDRCDR_EN \
135	\| DDRCDR_PZ_NOMZ \
136	\| DDRCDR_NZ_NOMZ \
137	\| DDRCDR_M_ODR )
138
139	/*
140	* FLASH on the Local Bus
141	*/
142	#define CFG_FLASH_CFI /* use the Common Flash Interface */
143	#define CFG_FLASH_CFI_DRIVER /* use the CFI driver */
144	#define CFG_FLASH_BASE 0xFE000000 /* start of FLASH */
145	#define CFG_FLASH_SIZE 8 /* flash size in MB */
146	#define CFG_FLASH_EMPTY_INFO /* display empty sectors */
147	#define CFG_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
148
a7676ea7 WD	149	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| /* flash Base address */ \
	150	(2 << BR_PS_SHIFT) \| /* 16 bit port size */ \
	151	BR_V) /* valid */
	152	#define CFG_OR0_PRELIM ( 0xFF000000 /* 16 MByte */ \
96b8a054 SW	153	\| OR_GPCM_XACS \
	154	\| OR_GPCM_SCY_9 \
	155	\| OR_GPCM_EHTR \
	156	\| OR_GPCM_EAD )
	157	/* 0xFF006FF7 TODO SLOW 16 MB flash size */
	158	#define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* window base at flash base */
	159	#define CFG_LBLAWAR0_PRELIM 0x80000017 /* 16 MB window size */
	160
	161	#define CFG_MAX_FLASH_BANKS 1 /* number of banks */
	162	#define CFG_MAX_FLASH_SECT 135 /* sectors per device */
	163
	164	#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	165	#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
	166
	167	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
	168
	169	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	170	#define CFG_RAMBOOT
	171	#endif
	172
	173	#define CFG_INIT_RAM_LOCK 1
	174	#define CFG_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
	175	#define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM*/
	176
	177	#define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */
	178	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	179	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	180
	181	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
	182	#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
	183
	184	/*
	185	* Local Bus LCRR and LBCR regs
	186	*/
	187	#define CFG_LCRR LCRR_EADC_1 \| LCRR_CLKDIV_2 /* 0x00010002 */
	188	#define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \
	189	\| (0xFF << LBCR_BMT_SHIFT) \
	190	\| 0xF ) /* 0x0004ff0f */
	191
a7676ea7	192	#define CFG_LBC_MRTPR 0x20000000 /TODO / /* LB refresh timer prescal, 266MHz/32 */
96b8a054 SW	193
96b8a054 SW	194	/* drivers/nand/nand.c */
a7676ea7	195	#define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */
96b8a054 SW	196	#define CFG_MAX_NAND_DEVICE 1
	197	#define NAND_MAX_CHIPS 1
	198	#define CONFIG_MTD_NAND_VERIFY_WRITE
	199
	200	#define CFG_BR1_PRELIM ( CFG_NAND_BASE \
a7676ea7 WD	201	\| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
	202	\| BR_PS_8 /* Port Size = 8 bit */ \
	203	\| BR_MS_FCM /* MSEL = FCM */ \
	204	\| BR_V ) /* valid */
	205	#define CFG_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
96b8a054 SW	206	\| OR_FCM_CSCT \
	207	\| OR_FCM_CST \
	208	\| OR_FCM_CHT \
	209	\| OR_FCM_SCY_1 \
	210	\| OR_FCM_TRLX \
	211	\| OR_FCM_EHTR )
	212	/* 0xFFFF8396 */
	213	#define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE
	214	#define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
	215
	216	#define CFG_VSC7385_BASE 0xF0000000
	217
	218	#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */
	219	#define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */
	220	#define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/
	221	#define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */
	222	#define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */
	223
	224	/* local bus read write buffer mapping */
	225	#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */
	226	#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */
	227	#define CFG_LBLAWBAR3_PRELIM 0xFA000000
	228	#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */
	229
	230	/* pass open firmware flat tree */
	231	#define CONFIG_OF_FLAT_TREE 1
	232	#define CONFIG_OF_BOARD_SETUP 1
	233
	234	/* maximum size of the flat tree (8K) */
	235	#define OF_FLAT_TREE_MAX_SIZE 8192
	236
	237	#define OF_CPU "PowerPC,8313@0"
	238	#define OF_SOC "soc8313@e0000000"
	239	#define OF_TBCLK (bd->bi_busfreq / 4)
	240	#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500"
	241
	242	/*
	243	* Serial Port
	244	*/
	245	#define CONFIG_CONS_INDEX 1
	246	#define CFG_NS16550
	247	#define CFG_NS16550_SERIAL
	248	#define CFG_NS16550_REG_SIZE 1
	249	#define CFG_NS16550_CLK get_bus_freq(0)
	250
	251	#define CFG_BAUDRATE_TABLE \
	252	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	253
	254	#define CFG_NS16550_COM1 (CFG_IMMR+0x4500)
	255	#define CFG_NS16550_COM2 (CFG_IMMR+0x4600)
	256
	257	/* Use the HUSH parser */
	258	#define CFG_HUSH_PARSER
	259	#define CFG_PROMPT_HUSH_PS2 "> "
	260
	261	/* I2C */
	262	#define CONFIG_HARD_I2C /* I2C with hardware support*/
	263	#define CONFIG_FSL_I2C
	264	#define CONFIG_I2C_MULTI_BUS
	265	#define CONFIG_I2C_CMD_TREE
	266	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	267	#define CFG_I2C_SLAVE 0x7F
	268	#define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */
	269	#define CFG_I2C_OFFSET 0x3000
270	#define CFG_I2C2_OFFSET 0x3100
271
272	/* TSEC */
273	#define CFG_TSEC1_OFFSET 0x24000
274	#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET)
275	#define CFG_TSEC2_OFFSET 0x25000
276	#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET)
277	#define CONFIG_NET_MULTI
278
279	/*
280	* General PCI
281	* Addresses are mapped 1-1.
282	*/
283	#define CFG_PCI1_MEM_BASE 0x80000000
284	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
285	#define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */
286	#define CFG_PCI1_MMIO_BASE 0x90000000
287	#define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE
288	#define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */
289	#define CFG_PCI1_IO_BASE 0x00000000
290	#define CFG_PCI1_IO_PHYS 0xE2000000
291	#define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */
292
293	#define CONFIG_PCI_PNP /* do pci plug-and-play */
294	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
295
296	/*
297	* TSEC configuration
298	*/
299	#define CONFIG_TSEC_ENET /* TSEC ethernet support */
300
301	#ifndef CONFIG_NET_MULTI
302	#define CONFIG_NET_MULTI 1
303	#endif
304
305	#define CONFIG_GMII 1 /* MII PHY management */
255a3577	306	#define CONFIG_TSEC1 1
96b8a054	307
255a3577 KP	308	#define CONFIG_TSEC1_NAME "TSEC0"
	309	#define CONFIG_TSEC2 1
	310	#define CONFIG_TSEC2_NAME "TSEC1"
96b8a054 SW	311	#define TSEC1_PHY_ADDR 0x1c
	312	#define TSEC2_PHY_ADDR 4
	313	#define TSEC1_PHYIDX 0
	314	#define TSEC2_PHYIDX 0
	315
	316	/* Options are: TSEC[0-1] */
	317	#define CONFIG_ETHPRIME "TSEC1"
	318
	319	/*
	320	* Configure on-board RTC
	321	*/
	322	#define CONFIG_RTC_DS1337
	323	#define CFG_I2C_RTC_ADDR 0x68
	324
	325	/*
	326	* Environment
	327	*/
	328	#ifndef CFG_RAMBOOT
	329	#define CFG_ENV_IS_IN_FLASH 1
	330	#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000)
	331	#define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
	332	#define CFG_ENV_SIZE 0x2000
	333
	334	/* Address and size of Redundant Environment Sector */
	335	#else
	336	#define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
	337	#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000)
	338	#define CFG_ENV_SIZE 0x2000
	339	#endif
	340
	341	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	342	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	343
	344	#define CFG_BASE_COMMANDS ( CONFIG_CMD_DFL \
	345	\| CFG_CMD_PING \
	346	\| CFG_CMD_DHCP \
	347	\| CFG_CMD_I2C \
	348	\| CFG_CMD_MII \
	349	\| CFG_CMD_DATE \
	350	\| CFG_CMD_PCI)
	351
	352	#define CONFIG_CMDLINE_EDITING 1
	353
	354	#define CFG_RAMBOOT_COMMANDS (CFG_BASE_COMMANDS & \
	355	~(CFG_CMD_ENV \| CFG_CMD_LOADS))
	356
	357	#if defined(CFG_RAMBOOT)
	358	#define CONFIG_COMMANDS CFG_RAMBOOT_COMMANDS
	359	#else
	360	#define CONFIG_COMMANDS CFG_BASE_COMMANDS
	361	#endif
	362
	363	#include <cmd_confdefs.h>
	364
	365	/*
	366	* Miscellaneous configurable options
	367	*/
	368	#define CFG_LONGHELP /* undef to save memory */
	369	#define CFG_LOAD_ADDR 0x2000000 /* default load address */
	370	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	371	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	372
a7676ea7	373	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
96b8a054 SW	374	#define CFG_MAXARGS 16 /* max number of command args */
	375	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	376	#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
	377
	378	/*
	379	* For booting Linux, the board info and command line data
	380	* have to be in the first 8 MB of memory, since this is
	381	* the maximum mapped by the Linux kernel during initialization.
	382	*/
	383	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/
	384
	385	/* Cache Configuration */
	386	#define CFG_DCACHE_SIZE 16384
	387	#define CFG_CACHELINE_SIZE 32
	388	#define CFG_CACHELINE_SHIFT 5 /log base 2 of the above value/
	389
a7676ea7	390	#define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */
96b8a054 SW	391
	392	#ifdef CFG_66MHZ
	393
	394	/* 66MHz IN, 133MHz CSB, 266 DDR, 266 CORE */
	395	/* 0x62040000 */
	396	#define CFG_HRCW_LOW (\
	397	0x20000000 /* reserved, must be set */ \|\
	398	HRCWL_DDRCM \|\
	399	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	400	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	401	HRCWL_CSB_TO_CLKIN_2X1 \|\
	402	HRCWL_CORE_TO_CSB_2X1)
	403
	404	#elif defined(CFG_33MHZ)
	405
	406	/* 33MHz IN, 165MHz CSB, 330 DDR, 330 CORE */
	407	/* 0x65040000 */
	408	#define CFG_HRCW_LOW (\
	409	0x20000000 /* reserved, must be set */ \|\
	410	HRCWL_DDRCM \|\
	411	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	412	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	413	HRCWL_CSB_TO_CLKIN_5X1 \|\
	414	HRCWL_CORE_TO_CSB_2X1)
	415
	416	#endif
	417
	418	/* 0xa0606c00 */
	419	#define CFG_HRCW_HIGH (\
	420	HRCWH_PCI_HOST \|\
	421	HRCWH_PCI1_ARBITER_ENABLE \|\
	422	HRCWH_CORE_ENABLE \|\
	423	HRCWH_FROM_0X00000100 \|\
	424	HRCWH_BOOTSEQ_DISABLE \|\
	425	HRCWH_SW_WATCHDOG_DISABLE \|\
	426	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	427	HRCWH_RL_EXT_LEGACY \|\
	428	HRCWH_TSEC1M_IN_RGMII \|\
	429	HRCWH_TSEC2M_IN_RGMII \|\
	430	HRCWH_BIG_ENDIAN \|\
	431	HRCWH_LALE_NORMAL)
	432
	433	/* System IO Config */
a7676ea7 WD	434	#define CFG_SICRH (SICRH_TSOBI1 \| SICRH_TSOBI2) /* RGMII */
a7676ea7 WD	435	#define CFG_SICRL SICRL_USBDR /* Enable Internal USB Phy */
96b8a054 SW	436
	437	#define CFG_HID0_INIT 0x000000000
	438	#define CFG_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
a7676ea7	439	HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
96b8a054 SW	440
	441	#define CFG_HID2 HID2_HBE
	442
	443	/* DDR @ 0x00000000 */
	444	#define CFG_IBAT0L (CFG_SDRAM_BASE \| BATL_PP_10)
	445	#define CFG_IBAT0U (CFG_SDRAM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	446
	447	/* PCI @ 0x80000000 */
	448	#define CFG_IBAT1L (CFG_PCI1_MEM_BASE \| BATL_PP_10)
	449	#define CFG_IBAT1U (CFG_PCI1_MEM_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	450	#define CFG_IBAT2L (CFG_PCI1_MMIO_BASE \| BATL_PP_10 \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	451	#define CFG_IBAT2U (CFG_PCI1_MMIO_BASE \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	452
	453	/* PCI2 not supported on 8313 */
	454	#define CFG_IBAT3L (0)
	455	#define CFG_IBAT3U (0)
	456	#define CFG_IBAT4L (0)
	457	#define CFG_IBAT4U (0)
	458
	459	/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */
	460	#define CFG_IBAT5L (CFG_IMMR \| BATL_PP_10 \| BATL_CACHEINHIBIT \| BATL_GUARDEDSTORAGE)
	461	#define CFG_IBAT5U (CFG_IMMR \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	462
	463	/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
	464	#define CFG_IBAT6L (0xF0000000 \| BATL_PP_10)
	465	#define CFG_IBAT6U (0xF0000000 \| BATU_BL_256M \| BATU_VS \| BATU_VP)
	466
	467	#define CFG_IBAT7L (0)
	468	#define CFG_IBAT7U (0)
	469
	470	#define CFG_DBAT0L CFG_IBAT0L
	471	#define CFG_DBAT0U CFG_IBAT0U
	472	#define CFG_DBAT1L CFG_IBAT1L
	473	#define CFG_DBAT1U CFG_IBAT1U
	474	#define CFG_DBAT2L CFG_IBAT2L
	475	#define CFG_DBAT2U CFG_IBAT2U
	476	#define CFG_DBAT3L CFG_IBAT3L
	477	#define CFG_DBAT3U CFG_IBAT3U
	478	#define CFG_DBAT4L CFG_IBAT4L
	479	#define CFG_DBAT4U CFG_IBAT4U
	480	#define CFG_DBAT5L CFG_IBAT5L
	481	#define CFG_DBAT5U CFG_IBAT5U
	482	#define CFG_DBAT6L CFG_IBAT6L
	483	#define CFG_DBAT6U CFG_IBAT6U
	484	#define CFG_DBAT7L CFG_IBAT7L
	485	#define CFG_DBAT7U CFG_IBAT7U
	486
	487	/*
	488	* Internal Definitions
	489	*
	490	* Boot Flags
	491	*/
	492	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	493	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	494
	495	/*
	496	* Environment Configuration
	497	*/
	498	#define CONFIG_ENV_OVERWRITE
	499
	500	#define CONFIG_ETHADDR 00:E0:0C:00:95:01
	501	#define CONFIG_HAS_ETH1
	502	#define CONFIG_ETH1ADDR 00:E0:0C:00:95:02
	503
504	#define CONFIG_IPADDR 10.0.0.2
505	#define CONFIG_SERVERIP 10.0.0.1
506	#define CONFIG_GATEWAYIP 10.0.0.1
507	#define CONFIG_NETMASK 255.0.0.0
508	#define CONFIG_NETDEV eth1
509
510	#define CONFIG_HOSTNAME mpc8313erdb
511	#define CONFIG_ROOTPATH /nfs/root/path
512	#define CONFIG_BOOTFILE uImage
513	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
514	#define CONFIG_FDTFILE mpc8313erdb.dtb
515
516	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
517	#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */
518	#define CONFIG_BAUDRATE 115200
519
520	#define XMK_STR(x) #x
521	#define MK_STR(x) XMK_STR(x)
522
523	#define CONFIG_EXTRA_ENV_SETTINGS \
524	"netdev=" MK_STR(CONFIG_NETDEV) "\0" \
525	"ethprime=TSEC1\0" \
526	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
527	"tftpflash=tftpboot $loadaddr $uboot; " \
528	"protect off " MK_STR(TEXT_BASE) " +$filesize; " \
529	"erase " MK_STR(TEXT_BASE) " +$filesize; " \
530	"cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
531	"protect on " MK_STR(TEXT_BASE) " +$filesize; " \
532	"cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
533	"fdtaddr=400000\0" \
534	"fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
535	"console=ttyS0\0" \
536	"setbootargs=setenv bootargs " \
537	"root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
538	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
539	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
540	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
541
542	#define CONFIG_NFSBOOTCOMMAND \
543	"setenv rootdev /dev/nfs;" \
544	"run setbootargs;" \
545	"run setipargs;" \
546	"tftp $loadaddr $bootfile;" \
547	"tftp $fdtaddr $fdtfile;" \
548	"bootm $loadaddr - $fdtaddr"
549
550	#define CONFIG_RAMBOOTCOMMAND \
551	"setenv rootdev /dev/ram;" \
552	"run setbootargs;" \
553	"tftp $ramdiskaddr $ramdiskfile;" \
554	"tftp $loadaddr $bootfile;" \
555	"tftp $fdtaddr $fdtfile;" \
556	"bootm $loadaddr $ramdiskaddr $fdtaddr"
557
558	#undef MK_STR
559	#undef XMK_STR
560
561	#endif /* __CONFIG_H */