[people/ms/u-boot.git] / include / configs / MPC8323ERDB.h

/*
 * Copyright (C) 2007 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License version 2 as published
 * by the Free Software Foundation.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 family */
#define CONFIG_QE		1	/* Has QE */
#define CONFIG_MPC832x		1	/* MPC832x CPU specific */

/*
 * System Clock Setup
 */
#define CONFIG_83XX_CLKIN	66666667	/* in Hz */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	CONFIG_83XX_CLKIN
#endif

/*
 * Hardware Reset Configuration Word
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CSB_TO_CLKIN_2X1 |\
	HRCWL_CORE_TO_CSB_2_5X1 |\
	HRCWL_CE_PLL_VCO_DIV_2 |\
	HRCWL_CE_PLL_DIV_1X1 |\
	HRCWL_CE_TO_PLL_1X3)

#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LALE_NORMAL)

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRL		0x00000000

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * System performance
 */
#define CONFIG_SYS_ACR_PIPE_DEP	3	/* Arbiter pipeline depth (0-3) */
#define CONFIG_SYS_ACR_RPTCNT	3	/* Arbiter repeat count (0-7) */
/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
#define CONFIG_SYS_SPCR_OPT	1

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE

#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface
 */
#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
#else
/* Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE	64	/* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
				| CSCONFIG_ROW_BIT_13 \
				| CSCONFIG_COL_BIT_9)
				/* 0x80010101 */
#define CONFIG_SYS_DDR_TIMING_0	((0 << TIMING_CFG0_RWT_SHIFT) \
				| (0 << TIMING_CFG0_WRT_SHIFT) \
				| (0 << TIMING_CFG0_RRT_SHIFT) \
				| (0 << TIMING_CFG0_WWT_SHIFT) \
				| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
				| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
				| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
				/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1	((2 << TIMING_CFG1_PRETOACT_SHIFT) \
				| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
				| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
				| (5 << TIMING_CFG1_CASLAT_SHIFT) \
				| (3 << TIMING_CFG1_REFREC_SHIFT) \
				| (2 << TIMING_CFG1_WRREC_SHIFT) \
				| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
				| (2 << TIMING_CFG1_WRTORD_SHIFT))
				/* 0x26253222 */
#define CONFIG_SYS_DDR_TIMING_2	((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (31 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x1f9048c7 */
#define CONFIG_SYS_DDR_TIMING_3	0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL	DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
				/* 0x02000000 */
#define CONFIG_SYS_DDR_MODE	((0x4448 << SDRAM_MODE_ESD_SHIFT) \
				| (0x0232 << SDRAM_MODE_SD_SHIFT))
				/* 0x44480232 */
#define CONFIG_SYS_DDR_MODE2	0x8000c000
#define CONFIG_SYS_DDR_INTERVAL	((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
				| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
				/* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000003
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
				| SDRAM_CFG_32_BE)
				/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#endif

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00030000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x03f00000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00000000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER	/* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE		16	/* FLASH size is 16M */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_GPCM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET \
				| OR_GPCM_EAD)
				/* 0xFE006FF7 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

#define CONFIG_CMDLINE_EDITING	1	/* add command line history */
#define CONFIG_AUTO_COMPLETE		/* add autocompletion support   */

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Config on-board EEPROM
 */
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	6
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	10

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0xd0000000
#define CONFIG_SYS_PCI1_IO_PHYS		CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE		0x04000000	/* 64M */

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_PCI_SKIP_HOST_BRIDGE

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"UEC0"

#define CONFIG_UEC_ETH1		/* ETH3 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	4
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif

#define CONFIG_UEC_ETH2		/* ETH4 */

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM	1	/* UCC2 */
#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK16
#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK3
#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR	0
#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
#endif

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
	#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x20000
	#define CONFIG_ENV_SIZE		0x2000
#else
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
					/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */
#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
				| BATU_BL_4M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_32M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT2L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

#define CONFIG_SYS_IBAT3L	(0)
#define CONFIG_SYS_IBAT3U	(0)
#define CONFIG_SYS_DBAT3L	CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT4L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT4U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_PCI1_MEM_PHYS \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_PCI1_MEM_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MMIO_PHYS \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MMIO_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#else
#define CONFIG_SYS_IBAT5L	(0)
#define CONFIG_SYS_IBAT5U	(0)
#define CONFIG_SYS_IBAT6L	(0)
#define CONFIG_SYS_IBAT6U	(0)
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#endif

/* Nothing in BAT7 */
#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U

#if (CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_HAS_ETH0		/* add support for "ethaddr" */
#define CONFIG_HAS_ETH1		/* add support for "eth1addr" */

/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
 * (see CONFIG_SYS_I2C_EEPROM) */
					/* MAC address offset in I2C EEPROM */
#define CONFIG_SYS_I2C_MAC_OFFSET	0x7f00

#define CONFIG_NETDEV		"eth1"

#define CONFIG_HOSTNAME		mpc8323erdb
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"uImage"
				/* U-Boot image on TFTP server */
#define CONFIG_UBOOTPATH	"u-boot.bin"
#define CONFIG_FDTFILE		"mpc832x_rdb.dtb"
#define CONFIG_RAMDISKFILE	"rootfs.ext2.gz.uboot"

				/* default location for tftp and bootm */
#define CONFIG_LOADADDR		800000

#define CONFIG_EXTRA_ENV_SETTINGS \
	"netdev=" CONFIG_NETDEV "\0"					\
	"uboot=" CONFIG_UBOOTPATH "\0"					\
	"tftpflash=tftp $loadaddr $uboot;"				\
		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" +$filesize; "	\
		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize; "	\
		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
			" +$filesize; "	\
		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
			" $filesize\0"	\
	"fdtaddr=780000\0"						\
	"fdtfile=" CONFIG_FDTFILE "\0"					\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=" CONFIG_RAMDISKFILE "\0"				\
	"console=ttyS0\0"						\
	"setbootargs=setenv bootargs "					\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath "	\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
								"$netdev:off "\
		"root=$rootdev rw console=$console,$baudrate $othbootargs\0"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv rootdev /dev/nfs;"					\
	"run setbootargs;"						\
	"run setipargs;"						\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv rootdev /dev/ram;"					\
	"run setbootargs;"						\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#endif	/* __CONFIG_H */
Commit	Line	Data
1c274c4e KP	1	/*
	2	* Copyright (C) 2007 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms of the GNU General Public License version 2 as published
	6	* by the Free Software Foundation.
	7	*/
	8
	9	#ifndef __CONFIG_H
	10	#define __CONFIG_H
	11
1c274c4e KP	12	/*
	13	* High Level Configuration Options
	14	*/
	15	#define CONFIG_E300 1 /* E300 family */
	16	#define CONFIG_QE 1 /* Has QE */
2c7920af	17	#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
1c274c4e	18
1c274c4e KP	19	/*
	20	* System Clock Setup
	21	*/
	22	#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
	23
	24	#ifndef CONFIG_SYS_CLK_FREQ
	25	#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
	26	#endif
	27
	28	/*
	29	* Hardware Reset Configuration Word
	30	*/
6d0f6bcf	31	#define CONFIG_SYS_HRCW_LOW (\
1c274c4e KP	32	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	33	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	34	HRCWL_VCO_1X2 \|\
	35	HRCWL_CSB_TO_CLKIN_2X1 \|\
	36	HRCWL_CORE_TO_CSB_2_5X1 \|\
	37	HRCWL_CE_PLL_VCO_DIV_2 \|\
	38	HRCWL_CE_PLL_DIV_1X1 \|\
	39	HRCWL_CE_TO_PLL_1X3)
	40
6d0f6bcf	41	#define CONFIG_SYS_HRCW_HIGH (\
1c274c4e KP	42	HRCWH_PCI_HOST \|\
	43	HRCWH_PCI1_ARBITER_ENABLE \|\
	44	HRCWH_CORE_ENABLE \|\
	45	HRCWH_FROM_0X00000100 \|\
	46	HRCWH_BOOTSEQ_DISABLE \|\
	47	HRCWH_SW_WATCHDOG_DISABLE \|\
	48	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	49	HRCWH_BIG_ENDIAN \|\
	50	HRCWH_LALE_NORMAL)
	51
	52	/*
	53	* System IO Config
	54	*/
6d0f6bcf	55	#define CONFIG_SYS_SICRL 0x00000000
1c274c4e	56
1c274c4e KP	57	/*
	58	* IMMR new address
	59	*/
6d0f6bcf	60	#define CONFIG_SYS_IMMR 0xE0000000
1c274c4e	61
5bbeea86 MB	62	/*
	63	* System performance
	64	*/
6d0f6bcf	65	#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
4dde49d8 JH	66	#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
	67	/* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */
	68	#define CONFIG_SYS_SPCR_OPT 1
5bbeea86	69
1c274c4e KP	70	/*
	71	* DDR Setup
	72	*/
4dde49d8 JH	73	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
4dde49d8 JH	74	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf	75	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
1c274c4e KP	76
	77	#undef CONFIG_SPD_EEPROM
	78	#if defined(CONFIG_SPD_EEPROM)
	79	/* Determine DDR configuration from I2C interface
	80	*/
	81	#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
	82	#else
	83	/* Manually set up DDR parameters
	84	*/
4dde49d8 JH	85	#define CONFIG_SYS_DDR_SIZE 64 /* MB */
4dde49d8 JH	86	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
4dde49d8 JH	87	\| CSCONFIG_ROW_BIT_13 \
4dde49d8 JH	88	\| CSCONFIG_COL_BIT_9)
5bbeea86	89	/* 0x80010101 */
4dde49d8 JH	90	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	91	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	92	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	93	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	94	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	95	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	96	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	97	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
fc549c87	98	/* 0x00220802 */
4dde49d8 JH	99	#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
	100	\| (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	101	\| (2 << TIMING_CFG1_ACTTORW_SHIFT) \
	102	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	103	\| (3 << TIMING_CFG1_REFREC_SHIFT) \
	104	\| (2 << TIMING_CFG1_WRREC_SHIFT) \
	105	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	106	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
5bbeea86	107	/* 0x26253222 */
4dde49d8 JH	108	#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
	109	\| (31 << TIMING_CFG2_CPO_SHIFT) \
	110	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	111	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	112	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	113	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	114	\| (7 << TIMING_CFG2_FOUR_ACT_SHIFT))
5bbeea86	115	/* 0x1f9048c7 */
6d0f6bcf JCPV	116	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
6d0f6bcf JCPV	117	#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
fc549c87	118	/* 0x02000000 */
4dde49d8 JH	119	#define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \
4dde49d8 JH	120	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
5bbeea86	121	/* 0x44480232 */
4dde49d8 JH	122	#define CONFIG_SYS_DDR_MODE2 0x8000c000
	123	#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
	124	\| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
fc549c87	125	/* 0x03200064 */
6d0f6bcf	126	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000003
4dde49d8	127	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
fc549c87	128	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
4dde49d8	129	\| SDRAM_CFG_32_BE)
fc549c87	130	/* 0x43080000 */
6d0f6bcf	131	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
1c274c4e KP	132	#endif
	133
	134	/*
	135	* Memory test
	136	*/
6d0f6bcf JCPV	137	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	138	#define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */
	139	#define CONFIG_SYS_MEMTEST_END 0x03f00000
1c274c4e KP	140
	141	/*
	142	* The reserved memory
	143	*/
14d0a02a	144	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
1c274c4e	145
6d0f6bcf JCPV	146	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	147	#define CONFIG_SYS_RAMBOOT
1c274c4e	148	#else
6d0f6bcf	149	#undef CONFIG_SYS_RAMBOOT
1c274c4e KP	150	#endif
1c274c4e KP	151
6d0f6bcf	152	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
16c8c170	153	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
c8a90646	154	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
1c274c4e KP	155
	156	/*
	157	* Initial RAM Base Address Setup
	158	*/
6d0f6bcf	159	#define CONFIG_SYS_INIT_RAM_LOCK 1
4dde49d8 JH	160	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
	161	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
	162	#define CONFIG_SYS_GBL_DATA_OFFSET \
	163	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
1c274c4e KP	164
	165	/*
	166	* Local Bus Configuration & Clock Setup
	167	*/
c7190f02 KP	168	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	169	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
6d0f6bcf	170	#define CONFIG_SYS_LBC_LBCR 0x00000000
1c274c4e KP	171
	172	/*
	173	* FLASH on the Local Bus
	174	*/
6d0f6bcf	175	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
00b1883a	176	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
4dde49d8	177	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
6d0f6bcf	178	#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
4dde49d8	179	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
1c274c4e	180
4dde49d8 JH	181	/* Window base at flash base */
4dde49d8 JH	182	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	183	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_32MB)
1c274c4e	184
4dde49d8	185	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
7d6a0982 JH	186	\| BR_PS_16 /* 16 bit port */ \
	187	\| BR_MS_GPCM /* MSEL = GPCM */ \
	188	\| BR_V) /* valid */
	189	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
	190	\| OR_GPCM_XAM \
	191	\| OR_GPCM_CSNT \
	192	\| OR_GPCM_ACS_DIV2 \
	193	\| OR_GPCM_XACS \
	194	\| OR_GPCM_SCY_15 \
	195	\| OR_GPCM_TRLX_SET \
	196	\| OR_GPCM_EHTR_SET \
	197	\| OR_GPCM_EAD)
	198	/* 0xFE006FF7 */
1c274c4e	199
4dde49d8 JH	200	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
4dde49d8 JH	201	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
1c274c4e	202
6d0f6bcf	203	#undef CONFIG_SYS_FLASH_CHECKSUM
1c274c4e	204
1c274c4e KP	205	/*
	206	* Serial Port
	207	*/
	208	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	209	#define CONFIG_SYS_NS16550_SERIAL
	210	#define CONFIG_SYS_NS16550_REG_SIZE 1
	211	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
1c274c4e	212
6d0f6bcf	213	#define CONFIG_SYS_BAUDRATE_TABLE \
4dde49d8	214	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
1c274c4e	215
6d0f6bcf JCPV	216	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	217	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
1c274c4e KP	218
1c274c4e KP	219	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
a059e90e	220	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
1c274c4e	221
1c274c4e	222	/* I2C */
00f792e0 HS	223	#define CONFIG_SYS_I2C
	224	#define CONFIG_SYS_I2C_FSL
	225	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	226	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	227	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	228	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
1c274c4e KP	229
1c274c4e KP	230	/*
0fa7a1b4	231	* Config on-board EEPROM
1c274c4e	232	*/
6d0f6bcf JCPV	233	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	234	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	235	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
	236	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
1c274c4e KP	237
	238	/*
	239	* General PCI
	240	* Addresses are mapped 1-1.
	241	*/
6d0f6bcf JCPV	242	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	243	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	244	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	245	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	246	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	247	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	248	#define CONFIG_SYS_PCI1_IO_BASE 0xd0000000
	249	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	250	#define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */
1c274c4e KP	251
1c274c4e KP	252	#ifdef CONFIG_PCI
842033e6	253	#define CONFIG_PCI_INDIRECT_BRIDGE
8f325cff	254	#define CONFIG_PCI_SKIP_HOST_BRIDGE
1c274c4e KP	255
	256	#undef CONFIG_EEPRO100
	257	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	258	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
1c274c4e KP	259
	260	#endif /* CONFIG_PCI */
	261
1c274c4e KP	262	/*
	263	* QE UEC ethernet configuration
	264	*/
	265	#define CONFIG_UEC_ETH
78b7a8ef	266	#define CONFIG_ETHPRIME "UEC0"
1c274c4e KP	267
	268	#define CONFIG_UEC_ETH1 /* ETH3 */
	269
	270	#ifdef CONFIG_UEC_ETH1
6d0f6bcf JCPV	271	#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
	272	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
	273	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
	274	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	275	#define CONFIG_SYS_UEC1_PHY_ADDR 4
865ff856	276	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	277	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
1c274c4e KP	278	#endif
	279
	280	#define CONFIG_UEC_ETH2 /* ETH4 */
	281
	282	#ifdef CONFIG_UEC_ETH2
6d0f6bcf JCPV	283	#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
	284	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK16
	285	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK3
	286	#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
	287	#define CONFIG_SYS_UEC2_PHY_ADDR 0
865ff856	288	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	289	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
1c274c4e KP	290	#endif
	291
	292	/*
	293	* Environment
	294	*/
6d0f6bcf	295	#ifndef CONFIG_SYS_RAMBOOT
4dde49d8 JH	296	#define CONFIG_ENV_ADDR \
4dde49d8 JH	297	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586 JCPV	298	#define CONFIG_ENV_SECT_SIZE 0x20000
0e8d1586 JCPV	299	#define CONFIG_ENV_SIZE 0x2000
1c274c4e	300	#else
6d0f6bcf	301	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	302	#define CONFIG_ENV_SIZE 0x2000
1c274c4e KP	303	#endif
	304
	305	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	306	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
1c274c4e KP	307
	308	/*
	309	* BOOTP options
	310	*/
	311	#define CONFIG_BOOTP_BOOTFILESIZE
	312	#define CONFIG_BOOTP_BOOTPATH
	313	#define CONFIG_BOOTP_GATEWAY
	314	#define CONFIG_BOOTP_HOSTNAME
	315
	316	/*
	317	* Command line configuration.
	318	*/
1c274c4e	319
1c274c4e KP	320	#undef CONFIG_WATCHDOG /* watchdog disabled */
	321
	322	/*
	323	* Miscellaneous configurable options
	324	*/
4dde49d8 JH	325	#define CONFIG_SYS_LONGHELP /* undef to save memory */
4dde49d8 JH	326	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
1c274c4e	327
1c274c4e KP	328	/*
1c274c4e KP	329	* For booting Linux, the board info and command line data
9f530d59	330	* have to be in the first 256 MB of memory, since this is
1c274c4e KP	331	* the maximum mapped by the Linux kernel during initialization.
1c274c4e KP	332	*/
4dde49d8 JH	333	/* Initial Memory map for Linux */
4dde49d8 JH	334	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278	335	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
1c274c4e KP	336
	337	/*
	338	* Core HID Setup
	339	*/
1a2e203b KP	340	#define CONFIG_SYS_HID0_INIT 0x000000000
	341	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	342	HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf	343	#define CONFIG_SYS_HID2 HID2_HBE
1c274c4e	344
1c274c4e KP	345	/*
	346	* MMU Setup
	347	*/
31d82672	348	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
1c274c4e KP	349
1c274c4e KP	350	/* DDR: cache cacheable */
4dde49d8	351	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	352	\| BATL_PP_RW \
4dde49d8 JH	353	\| BATL_MEMCOHERENCE)
	354	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	355	\| BATU_BL_256M \
	356	\| BATU_VS \
	357	\| BATU_VP)
6d0f6bcf JCPV	358	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
6d0f6bcf JCPV	359	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
1c274c4e KP	360
1c274c4e KP	361	/* IMMRBAR & PCI IO: cache-inhibit and guarded */
4dde49d8	362	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
72cd4087	363	\| BATL_PP_RW \
4dde49d8 JH	364	\| BATL_CACHEINHIBIT \
	365	\| BATL_GUARDEDSTORAGE)
	366	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
	367	\| BATU_BL_4M \
	368	\| BATU_VS \
	369	\| BATU_VP)
6d0f6bcf JCPV	370	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
6d0f6bcf JCPV	371	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
1c274c4e KP	372
1c274c4e KP	373	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
4dde49d8	374	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \
72cd4087	375	\| BATL_PP_RW \
4dde49d8 JH	376	\| BATL_MEMCOHERENCE)
	377	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \
	378	\| BATU_BL_32M \
	379	\| BATU_VS \
	380	\| BATU_VP)
	381	#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \
72cd4087	382	\| BATL_PP_RW \
4dde49d8 JH	383	\| BATL_CACHEINHIBIT \
4dde49d8 JH	384	\| BATL_GUARDEDSTORAGE)
6d0f6bcf	385	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
1c274c4e	386
6d0f6bcf JCPV	387	#define CONFIG_SYS_IBAT3L (0)
	388	#define CONFIG_SYS_IBAT3U (0)
	389	#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
	390	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
1c274c4e KP	391
1c274c4e KP	392	/* Stack in dcache: cacheable, no memory coherence */
72cd4087	393	#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
4dde49d8 JH	394	#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
	395	\| BATU_BL_128K \
	396	\| BATU_VS \
	397	\| BATU_VP)
6d0f6bcf JCPV	398	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
6d0f6bcf JCPV	399	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
1c274c4e KP	400
	401	#ifdef CONFIG_PCI
	402	/* PCI MEM space: cacheable */
4dde49d8	403	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \
72cd4087	404	\| BATL_PP_RW \
4dde49d8 JH	405	\| BATL_MEMCOHERENCE)
	406	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \
	407	\| BATU_BL_256M \
	408	\| BATU_VS \
	409	\| BATU_VP)
6d0f6bcf JCPV	410	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
6d0f6bcf JCPV	411	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
1c274c4e	412	/* PCI MMIO space: cache-inhibit and guarded */
4dde49d8	413	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \
72cd4087	414	\| BATL_PP_RW \
4dde49d8 JH	415	\| BATL_CACHEINHIBIT \
	416	\| BATL_GUARDEDSTORAGE)
	417	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \
	418	\| BATU_BL_256M \
	419	\| BATU_VS \
	420	\| BATU_VP)
6d0f6bcf JCPV	421	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
6d0f6bcf JCPV	422	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
1c274c4e	423	#else
6d0f6bcf JCPV	424	#define CONFIG_SYS_IBAT5L (0)
	425	#define CONFIG_SYS_IBAT5U (0)
	426	#define CONFIG_SYS_IBAT6L (0)
	427	#define CONFIG_SYS_IBAT6U (0)
	428	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
	429	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
	430	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	431	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
1c274c4e KP	432	#endif
	433
	434	/* Nothing in BAT7 */
6d0f6bcf JCPV	435	#define CONFIG_SYS_IBAT7L (0)
	436	#define CONFIG_SYS_IBAT7U (0)
	437	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	438	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
1c274c4e	439
1c274c4e KP	440	#if (CONFIG_CMD_KGDB)
1c274c4e KP	441	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
1c274c4e KP	442	#endif
	443
	444	/*
	445	* Environment Configuration
	446	*/
	447	#define CONFIG_ENV_OVERWRITE
	448
4dde49d8 JH	449	#define CONFIG_HAS_ETH0 /* add support for "ethaddr" */
4dde49d8 JH	450	#define CONFIG_HAS_ETH1 /* add support for "eth1addr" */
1c274c4e	451
4dde49d8 JH	452	/* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM
	453	* (see CONFIG_SYS_I2C_EEPROM) */
	454	/* MAC address offset in I2C EEPROM */
	455	#define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00
5b2793a3	456
4dde49d8	457	#define CONFIG_NETDEV "eth1"
1c274c4e KP	458
1c274c4e KP	459	#define CONFIG_HOSTNAME mpc8323erdb
8b3637c6	460	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	461	#define CONFIG_BOOTFILE "uImage"
4dde49d8 JH	462	/* U-Boot image on TFTP server */
	463	#define CONFIG_UBOOTPATH "u-boot.bin"
	464	#define CONFIG_FDTFILE "mpc832x_rdb.dtb"
	465	#define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot"
1c274c4e	466
4dde49d8 JH	467	/* default location for tftp and bootm */
4dde49d8 JH	468	#define CONFIG_LOADADDR 800000
1c274c4e	469
1c274c4e	470	#define CONFIG_EXTRA_ENV_SETTINGS \
4dde49d8 JH	471	"netdev=" CONFIG_NETDEV "\0" \
4dde49d8 JH	472	"uboot=" CONFIG_UBOOTPATH "\0" \
1c274c4e	473	"tftpflash=tftp $loadaddr $uboot;" \
5368c55d MV	474	"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
	475	" +$filesize; " \
	476	"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
	477	" +$filesize; " \
	478	"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	479	" $filesize; " \
	480	"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
	481	" +$filesize; " \
	482	"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
	483	" $filesize\0" \
79f516bc	484	"fdtaddr=780000\0" \
4dde49d8	485	"fdtfile=" CONFIG_FDTFILE "\0" \
1c274c4e	486	"ramdiskaddr=1000000\0" \
4dde49d8	487	"ramdiskfile=" CONFIG_RAMDISKFILE "\0" \
1c274c4e KP	488	"console=ttyS0\0" \
1c274c4e KP	489	"setbootargs=setenv bootargs " \
4dde49d8	490	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"\
1c274c4e	491	"setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
4dde49d8 JH	492	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\
4dde49d8 JH	493	"$netdev:off "\
1c274c4e KP	494	"root=$rootdev rw console=$console,$baudrate $othbootargs\0"
	495
	496	#define CONFIG_NFSBOOTCOMMAND \
	497	"setenv rootdev /dev/nfs;" \
	498	"run setbootargs;" \
	499	"run setipargs;" \
	500	"tftp $loadaddr $bootfile;" \
	501	"tftp $fdtaddr $fdtfile;" \
	502	"bootm $loadaddr - $fdtaddr"
	503
	504	#define CONFIG_RAMBOOTCOMMAND \
	505	"setenv rootdev /dev/ram;" \
	506	"run setbootargs;" \
	507	"tftp $ramdiskaddr $ramdiskfile;" \
	508	"tftp $loadaddr $bootfile;" \
	509	"tftp $fdtaddr $fdtfile;" \
	510	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	511
1c274c4e	512	#endif /* __CONFIG_H */