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1c274c4e KP |
1 | /* |
2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * This program is free software; you can redistribute it and/or modify it | |
5 | * under the terms of the GNU General Public License version 2 as published | |
6 | * by the Free Software Foundation. | |
7 | */ | |
8 | ||
9 | #ifndef __CONFIG_H | |
10 | #define __CONFIG_H | |
11 | ||
fdfaa29e KP |
12 | #define CONFIG_DISPLAY_BOARDINFO |
13 | ||
1c274c4e KP |
14 | /* |
15 | * High Level Configuration Options | |
16 | */ | |
17 | #define CONFIG_E300 1 /* E300 family */ | |
18 | #define CONFIG_QE 1 /* Has QE */ | |
2c7920af | 19 | #define CONFIG_MPC832x 1 /* MPC832x CPU specific */ |
1c274c4e | 20 | |
2ae18241 WD |
21 | #define CONFIG_SYS_TEXT_BASE 0xFE000000 |
22 | ||
1c274c4e | 23 | #define CONFIG_PCI 1 |
1c274c4e KP |
24 | |
25 | /* | |
26 | * System Clock Setup | |
27 | */ | |
28 | #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ | |
29 | ||
30 | #ifndef CONFIG_SYS_CLK_FREQ | |
31 | #define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN | |
32 | #endif | |
33 | ||
34 | /* | |
35 | * Hardware Reset Configuration Word | |
36 | */ | |
6d0f6bcf | 37 | #define CONFIG_SYS_HRCW_LOW (\ |
1c274c4e KP |
38 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
39 | HRCWL_DDR_TO_SCB_CLK_2X1 |\ | |
40 | HRCWL_VCO_1X2 |\ | |
41 | HRCWL_CSB_TO_CLKIN_2X1 |\ | |
42 | HRCWL_CORE_TO_CSB_2_5X1 |\ | |
43 | HRCWL_CE_PLL_VCO_DIV_2 |\ | |
44 | HRCWL_CE_PLL_DIV_1X1 |\ | |
45 | HRCWL_CE_TO_PLL_1X3) | |
46 | ||
6d0f6bcf | 47 | #define CONFIG_SYS_HRCW_HIGH (\ |
1c274c4e KP |
48 | HRCWH_PCI_HOST |\ |
49 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
50 | HRCWH_CORE_ENABLE |\ | |
51 | HRCWH_FROM_0X00000100 |\ | |
52 | HRCWH_BOOTSEQ_DISABLE |\ | |
53 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
54 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
55 | HRCWH_BIG_ENDIAN |\ | |
56 | HRCWH_LALE_NORMAL) | |
57 | ||
58 | /* | |
59 | * System IO Config | |
60 | */ | |
6d0f6bcf | 61 | #define CONFIG_SYS_SICRL 0x00000000 |
1c274c4e | 62 | |
1c274c4e KP |
63 | /* |
64 | * IMMR new address | |
65 | */ | |
6d0f6bcf | 66 | #define CONFIG_SYS_IMMR 0xE0000000 |
1c274c4e | 67 | |
5bbeea86 MB |
68 | /* |
69 | * System performance | |
70 | */ | |
6d0f6bcf | 71 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
4dde49d8 JH |
72 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
73 | /* (0-1) Optimize transactions between CSB and the SEC and QUICC Engine block */ | |
74 | #define CONFIG_SYS_SPCR_OPT 1 | |
5bbeea86 | 75 | |
1c274c4e KP |
76 | /* |
77 | * DDR Setup | |
78 | */ | |
4dde49d8 JH |
79 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ |
80 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 81 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
1c274c4e KP |
82 | |
83 | #undef CONFIG_SPD_EEPROM | |
84 | #if defined(CONFIG_SPD_EEPROM) | |
85 | /* Determine DDR configuration from I2C interface | |
86 | */ | |
87 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */ | |
88 | #else | |
89 | /* Manually set up DDR parameters | |
90 | */ | |
4dde49d8 JH |
91 | #define CONFIG_SYS_DDR_SIZE 64 /* MB */ |
92 | #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | |
4dde49d8 JH |
93 | | CSCONFIG_ROW_BIT_13 \ |
94 | | CSCONFIG_COL_BIT_9) | |
5bbeea86 | 95 | /* 0x80010101 */ |
4dde49d8 JH |
96 | #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ |
97 | | (0 << TIMING_CFG0_WRT_SHIFT) \ | |
98 | | (0 << TIMING_CFG0_RRT_SHIFT) \ | |
99 | | (0 << TIMING_CFG0_WWT_SHIFT) \ | |
100 | | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ | |
101 | | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ | |
102 | | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ | |
103 | | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) | |
fc549c87 | 104 | /* 0x00220802 */ |
4dde49d8 JH |
105 | #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ |
106 | | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \ | |
107 | | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ | |
108 | | (5 << TIMING_CFG1_CASLAT_SHIFT) \ | |
109 | | (3 << TIMING_CFG1_REFREC_SHIFT) \ | |
110 | | (2 << TIMING_CFG1_WRREC_SHIFT) \ | |
111 | | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ | |
112 | | (2 << TIMING_CFG1_WRTORD_SHIFT)) | |
5bbeea86 | 113 | /* 0x26253222 */ |
4dde49d8 JH |
114 | #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ |
115 | | (31 << TIMING_CFG2_CPO_SHIFT) \ | |
116 | | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ | |
117 | | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ | |
118 | | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ | |
119 | | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ | |
120 | | (7 << TIMING_CFG2_FOUR_ACT_SHIFT)) | |
5bbeea86 | 121 | /* 0x1f9048c7 */ |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
123 | #define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
fc549c87 | 124 | /* 0x02000000 */ |
4dde49d8 JH |
125 | #define CONFIG_SYS_DDR_MODE ((0x4448 << SDRAM_MODE_ESD_SHIFT) \ |
126 | | (0x0232 << SDRAM_MODE_SD_SHIFT)) | |
5bbeea86 | 127 | /* 0x44480232 */ |
4dde49d8 JH |
128 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 |
129 | #define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \ | |
130 | | (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) | |
fc549c87 | 131 | /* 0x03200064 */ |
6d0f6bcf | 132 | #define CONFIG_SYS_DDR_CS0_BNDS 0x00000003 |
4dde49d8 | 133 | #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ |
fc549c87 | 134 | | SDRAM_CFG_SDRAM_TYPE_DDR2 \ |
4dde49d8 | 135 | | SDRAM_CFG_32_BE) |
fc549c87 | 136 | /* 0x43080000 */ |
6d0f6bcf | 137 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
1c274c4e KP |
138 | #endif |
139 | ||
140 | /* | |
141 | * Memory test | |
142 | */ | |
6d0f6bcf JCPV |
143 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
144 | #define CONFIG_SYS_MEMTEST_START 0x00030000 /* memtest region */ | |
145 | #define CONFIG_SYS_MEMTEST_END 0x03f00000 | |
1c274c4e KP |
146 | |
147 | /* | |
148 | * The reserved memory | |
149 | */ | |
14d0a02a | 150 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
1c274c4e | 151 | |
6d0f6bcf JCPV |
152 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
153 | #define CONFIG_SYS_RAMBOOT | |
1c274c4e | 154 | #else |
6d0f6bcf | 155 | #undef CONFIG_SYS_RAMBOOT |
1c274c4e KP |
156 | #endif |
157 | ||
6d0f6bcf | 158 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
4dde49d8 | 159 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
c8a90646 | 160 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
1c274c4e KP |
161 | |
162 | /* | |
163 | * Initial RAM Base Address Setup | |
164 | */ | |
6d0f6bcf | 165 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
4dde49d8 JH |
166 | #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ |
167 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ | |
168 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
169 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
1c274c4e KP |
170 | |
171 | /* | |
172 | * Local Bus Configuration & Clock Setup | |
173 | */ | |
c7190f02 KP |
174 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
175 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 | |
6d0f6bcf | 176 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
1c274c4e KP |
177 | |
178 | /* | |
179 | * FLASH on the Local Bus | |
180 | */ | |
6d0f6bcf | 181 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 182 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
4dde49d8 | 183 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ |
6d0f6bcf | 184 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */ |
4dde49d8 | 185 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ |
1c274c4e | 186 | |
4dde49d8 JH |
187 | /* Window base at flash base */ |
188 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 189 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
1c274c4e | 190 | |
4dde49d8 | 191 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
7d6a0982 JH |
192 | | BR_PS_16 /* 16 bit port */ \ |
193 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
194 | | BR_V) /* valid */ | |
195 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
196 | | OR_GPCM_XAM \ | |
197 | | OR_GPCM_CSNT \ | |
198 | | OR_GPCM_ACS_DIV2 \ | |
199 | | OR_GPCM_XACS \ | |
200 | | OR_GPCM_SCY_15 \ | |
201 | | OR_GPCM_TRLX_SET \ | |
202 | | OR_GPCM_EHTR_SET \ | |
203 | | OR_GPCM_EAD) | |
204 | /* 0xFE006FF7 */ | |
1c274c4e | 205 | |
4dde49d8 JH |
206 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
207 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ | |
1c274c4e | 208 | |
6d0f6bcf | 209 | #undef CONFIG_SYS_FLASH_CHECKSUM |
1c274c4e | 210 | |
1c274c4e KP |
211 | /* |
212 | * Serial Port | |
213 | */ | |
214 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_NS16550_SERIAL |
216 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
217 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
1c274c4e | 218 | |
6d0f6bcf | 219 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
4dde49d8 | 220 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
1c274c4e | 221 | |
6d0f6bcf JCPV |
222 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
223 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
1c274c4e KP |
224 | |
225 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
a059e90e | 226 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
1c274c4e | 227 | /* Use the HUSH parser */ |
6d0f6bcf | 228 | #define CONFIG_SYS_HUSH_PARSER |
1c274c4e | 229 | |
1c274c4e | 230 | /* I2C */ |
00f792e0 HS |
231 | #define CONFIG_SYS_I2C |
232 | #define CONFIG_SYS_I2C_FSL | |
233 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
234 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
235 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
236 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } | |
1c274c4e KP |
237 | |
238 | /* | |
0fa7a1b4 | 239 | * Config on-board EEPROM |
1c274c4e | 240 | */ |
6d0f6bcf JCPV |
241 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 |
242 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
243 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 | |
244 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 | |
1c274c4e KP |
245 | |
246 | /* | |
247 | * General PCI | |
248 | * Addresses are mapped 1-1. | |
249 | */ | |
6d0f6bcf JCPV |
250 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
251 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
252 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
253 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
254 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
255 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
256 | #define CONFIG_SYS_PCI1_IO_BASE 0xd0000000 | |
257 | #define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE | |
258 | #define CONFIG_SYS_PCI1_IO_SIZE 0x04000000 /* 64M */ | |
1c274c4e KP |
259 | |
260 | #ifdef CONFIG_PCI | |
842033e6 | 261 | #define CONFIG_PCI_INDIRECT_BRIDGE |
8f325cff | 262 | #define CONFIG_PCI_SKIP_HOST_BRIDGE |
1c274c4e KP |
263 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
264 | ||
265 | #undef CONFIG_EEPRO100 | |
266 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 267 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
1c274c4e KP |
268 | |
269 | #endif /* CONFIG_PCI */ | |
270 | ||
1c274c4e KP |
271 | /* |
272 | * QE UEC ethernet configuration | |
273 | */ | |
274 | #define CONFIG_UEC_ETH | |
78b7a8ef | 275 | #define CONFIG_ETHPRIME "UEC0" |
1c274c4e KP |
276 | |
277 | #define CONFIG_UEC_ETH1 /* ETH3 */ | |
278 | ||
279 | #ifdef CONFIG_UEC_ETH1 | |
6d0f6bcf JCPV |
280 | #define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */ |
281 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 | |
282 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 | |
283 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
284 | #define CONFIG_SYS_UEC1_PHY_ADDR 4 | |
865ff856 | 285 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII |
582c55a0 | 286 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
1c274c4e KP |
287 | #endif |
288 | ||
289 | #define CONFIG_UEC_ETH2 /* ETH4 */ | |
290 | ||
291 | #ifdef CONFIG_UEC_ETH2 | |
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ |
293 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK16 | |
294 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK3 | |
295 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
296 | #define CONFIG_SYS_UEC2_PHY_ADDR 0 | |
865ff856 | 297 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII |
582c55a0 | 298 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
1c274c4e KP |
299 | #endif |
300 | ||
301 | /* | |
302 | * Environment | |
303 | */ | |
6d0f6bcf | 304 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 305 | #define CONFIG_ENV_IS_IN_FLASH 1 |
4dde49d8 JH |
306 | #define CONFIG_ENV_ADDR \ |
307 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
308 | #define CONFIG_ENV_SECT_SIZE 0x20000 |
309 | #define CONFIG_ENV_SIZE 0x2000 | |
1c274c4e | 310 | #else |
4dde49d8 | 311 | #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 312 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
6d0f6bcf | 313 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 314 | #define CONFIG_ENV_SIZE 0x2000 |
1c274c4e KP |
315 | #endif |
316 | ||
317 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 318 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
1c274c4e KP |
319 | |
320 | /* | |
321 | * BOOTP options | |
322 | */ | |
323 | #define CONFIG_BOOTP_BOOTFILESIZE | |
324 | #define CONFIG_BOOTP_BOOTPATH | |
325 | #define CONFIG_BOOTP_GATEWAY | |
326 | #define CONFIG_BOOTP_HOSTNAME | |
327 | ||
328 | /* | |
329 | * Command line configuration. | |
330 | */ | |
1c274c4e KP |
331 | #define CONFIG_CMD_PING |
332 | #define CONFIG_CMD_I2C | |
0fa7a1b4 | 333 | #define CONFIG_CMD_EEPROM |
1c274c4e KP |
334 | #define CONFIG_CMD_ASKENV |
335 | ||
336 | #if defined(CONFIG_PCI) | |
337 | #define CONFIG_CMD_PCI | |
338 | #endif | |
1c274c4e KP |
339 | |
340 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
341 | ||
342 | /* | |
343 | * Miscellaneous configurable options | |
344 | */ | |
4dde49d8 JH |
345 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
346 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
1c274c4e KP |
347 | |
348 | #if (CONFIG_CMD_KGDB) | |
6d0f6bcf | 349 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
1c274c4e | 350 | #else |
6d0f6bcf | 351 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
1c274c4e KP |
352 | #endif |
353 | ||
4dde49d8 JH |
354 | /* Print Buffer Size */ |
355 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
6d0f6bcf | 356 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
4dde49d8 JH |
357 | /* Boot Argument Buffer Size */ |
358 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
1c274c4e KP |
359 | |
360 | /* | |
361 | * For booting Linux, the board info and command line data | |
9f530d59 | 362 | * have to be in the first 256 MB of memory, since this is |
1c274c4e KP |
363 | * the maximum mapped by the Linux kernel during initialization. |
364 | */ | |
4dde49d8 JH |
365 | /* Initial Memory map for Linux */ |
366 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
1c274c4e KP |
367 | |
368 | /* | |
369 | * Core HID Setup | |
370 | */ | |
1a2e203b KP |
371 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
372 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ | |
373 | HID0_ENABLE_INSTRUCTION_CACHE) | |
6d0f6bcf | 374 | #define CONFIG_SYS_HID2 HID2_HBE |
1c274c4e | 375 | |
1c274c4e KP |
376 | /* |
377 | * MMU Setup | |
378 | */ | |
31d82672 | 379 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
1c274c4e KP |
380 | |
381 | /* DDR: cache cacheable */ | |
4dde49d8 | 382 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 383 | | BATL_PP_RW \ |
4dde49d8 JH |
384 | | BATL_MEMCOHERENCE) |
385 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
386 | | BATU_BL_256M \ | |
387 | | BATU_VS \ | |
388 | | BATU_VP) | |
6d0f6bcf JCPV |
389 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L |
390 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
1c274c4e KP |
391 | |
392 | /* IMMRBAR & PCI IO: cache-inhibit and guarded */ | |
4dde49d8 | 393 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ |
72cd4087 | 394 | | BATL_PP_RW \ |
4dde49d8 JH |
395 | | BATL_CACHEINHIBIT \ |
396 | | BATL_GUARDEDSTORAGE) | |
397 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ | |
398 | | BATU_BL_4M \ | |
399 | | BATU_VS \ | |
400 | | BATU_VP) | |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L |
402 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
1c274c4e KP |
403 | |
404 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
4dde49d8 | 405 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE \ |
72cd4087 | 406 | | BATL_PP_RW \ |
4dde49d8 JH |
407 | | BATL_MEMCOHERENCE) |
408 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE \ | |
409 | | BATU_BL_32M \ | |
410 | | BATU_VS \ | |
411 | | BATU_VP) | |
412 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE \ | |
72cd4087 | 413 | | BATL_PP_RW \ |
4dde49d8 JH |
414 | | BATL_CACHEINHIBIT \ |
415 | | BATL_GUARDEDSTORAGE) | |
6d0f6bcf | 416 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U |
1c274c4e | 417 | |
6d0f6bcf JCPV |
418 | #define CONFIG_SYS_IBAT3L (0) |
419 | #define CONFIG_SYS_IBAT3U (0) | |
420 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
421 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
1c274c4e KP |
422 | |
423 | /* Stack in dcache: cacheable, no memory coherence */ | |
72cd4087 | 424 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) |
4dde49d8 JH |
425 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ |
426 | | BATU_BL_128K \ | |
427 | | BATU_VS \ | |
428 | | BATU_VP) | |
6d0f6bcf JCPV |
429 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L |
430 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
1c274c4e KP |
431 | |
432 | #ifdef CONFIG_PCI | |
433 | /* PCI MEM space: cacheable */ | |
4dde49d8 | 434 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_PCI1_MEM_PHYS \ |
72cd4087 | 435 | | BATL_PP_RW \ |
4dde49d8 JH |
436 | | BATL_MEMCOHERENCE) |
437 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_PCI1_MEM_PHYS \ | |
438 | | BATU_BL_256M \ | |
439 | | BATU_VS \ | |
440 | | BATU_VP) | |
6d0f6bcf JCPV |
441 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L |
442 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
1c274c4e | 443 | /* PCI MMIO space: cache-inhibit and guarded */ |
4dde49d8 | 444 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MMIO_PHYS \ |
72cd4087 | 445 | | BATL_PP_RW \ |
4dde49d8 JH |
446 | | BATL_CACHEINHIBIT \ |
447 | | BATL_GUARDEDSTORAGE) | |
448 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MMIO_PHYS \ | |
449 | | BATU_BL_256M \ | |
450 | | BATU_VS \ | |
451 | | BATU_VP) | |
6d0f6bcf JCPV |
452 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L |
453 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
1c274c4e | 454 | #else |
6d0f6bcf JCPV |
455 | #define CONFIG_SYS_IBAT5L (0) |
456 | #define CONFIG_SYS_IBAT5U (0) | |
457 | #define CONFIG_SYS_IBAT6L (0) | |
458 | #define CONFIG_SYS_IBAT6U (0) | |
459 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
460 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
461 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
462 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
1c274c4e KP |
463 | #endif |
464 | ||
465 | /* Nothing in BAT7 */ | |
6d0f6bcf JCPV |
466 | #define CONFIG_SYS_IBAT7L (0) |
467 | #define CONFIG_SYS_IBAT7U (0) | |
468 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
469 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
1c274c4e | 470 | |
1c274c4e KP |
471 | #if (CONFIG_CMD_KGDB) |
472 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
1c274c4e KP |
473 | #endif |
474 | ||
475 | /* | |
476 | * Environment Configuration | |
477 | */ | |
478 | #define CONFIG_ENV_OVERWRITE | |
479 | ||
4dde49d8 JH |
480 | #define CONFIG_HAS_ETH0 /* add support for "ethaddr" */ |
481 | #define CONFIG_HAS_ETH1 /* add support for "eth1addr" */ | |
1c274c4e | 482 | |
4dde49d8 JH |
483 | /* use mac_read_from_eeprom() to read ethaddr from I2C EEPROM |
484 | * (see CONFIG_SYS_I2C_EEPROM) */ | |
485 | /* MAC address offset in I2C EEPROM */ | |
486 | #define CONFIG_SYS_I2C_MAC_OFFSET 0x7f00 | |
5b2793a3 | 487 | |
4dde49d8 | 488 | #define CONFIG_NETDEV "eth1" |
1c274c4e KP |
489 | |
490 | #define CONFIG_HOSTNAME mpc8323erdb | |
8b3637c6 | 491 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 492 | #define CONFIG_BOOTFILE "uImage" |
4dde49d8 JH |
493 | /* U-Boot image on TFTP server */ |
494 | #define CONFIG_UBOOTPATH "u-boot.bin" | |
495 | #define CONFIG_FDTFILE "mpc832x_rdb.dtb" | |
496 | #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" | |
1c274c4e | 497 | |
4dde49d8 JH |
498 | /* default location for tftp and bootm */ |
499 | #define CONFIG_LOADADDR 800000 | |
7fd0bea2 | 500 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ |
1c274c4e KP |
501 | #define CONFIG_BAUDRATE 115200 |
502 | ||
1c274c4e | 503 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
4dde49d8 JH |
504 | "netdev=" CONFIG_NETDEV "\0" \ |
505 | "uboot=" CONFIG_UBOOTPATH "\0" \ | |
1c274c4e | 506 | "tftpflash=tftp $loadaddr $uboot;" \ |
5368c55d MV |
507 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ |
508 | " +$filesize; " \ | |
509 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
510 | " +$filesize; " \ | |
511 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
512 | " $filesize; " \ | |
513 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
514 | " +$filesize; " \ | |
515 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
516 | " $filesize\0" \ | |
79f516bc | 517 | "fdtaddr=780000\0" \ |
4dde49d8 | 518 | "fdtfile=" CONFIG_FDTFILE "\0" \ |
1c274c4e | 519 | "ramdiskaddr=1000000\0" \ |
4dde49d8 | 520 | "ramdiskfile=" CONFIG_RAMDISKFILE "\0" \ |
1c274c4e KP |
521 | "console=ttyS0\0" \ |
522 | "setbootargs=setenv bootargs " \ | |
4dde49d8 | 523 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0"\ |
1c274c4e | 524 | "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ |
4dde49d8 JH |
525 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"\ |
526 | "$netdev:off "\ | |
1c274c4e KP |
527 | "root=$rootdev rw console=$console,$baudrate $othbootargs\0" |
528 | ||
529 | #define CONFIG_NFSBOOTCOMMAND \ | |
530 | "setenv rootdev /dev/nfs;" \ | |
531 | "run setbootargs;" \ | |
532 | "run setipargs;" \ | |
533 | "tftp $loadaddr $bootfile;" \ | |
534 | "tftp $fdtaddr $fdtfile;" \ | |
535 | "bootm $loadaddr - $fdtaddr" | |
536 | ||
537 | #define CONFIG_RAMBOOTCOMMAND \ | |
538 | "setenv rootdev /dev/ram;" \ | |
539 | "run setbootargs;" \ | |
540 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
541 | "tftp $loadaddr $bootfile;" \ | |
542 | "tftp $fdtaddr $fdtfile;" \ | |
543 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
544 | ||
1c274c4e | 545 | #endif /* __CONFIG_H */ |