[people/ms/u-boot.git] / include / configs / MPC832XEMDS.h

/*
 * Copyright (C) 2006 Freescale Semiconductor, Inc.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_E300		1	/* E300 family */
#define CONFIG_QE		1	/* Has QE */
#define CONFIG_MPC832x		1	/* MPC832x CPU specific */
#define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */

/*
 * System Clock Setup
 */
#ifdef CONFIG_PCISLAVE
#define CONFIG_83XX_PCICLK	66000000	/* in HZ */
#else
#define CONFIG_83XX_CLKIN	66000000	/* in Hz */
#endif

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	66000000
#endif

/*
 * Hardware Reset Configuration Word
 */
#define CONFIG_SYS_HRCW_LOW (\
	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
	HRCWL_DDR_TO_SCB_CLK_2X1 |\
	HRCWL_VCO_1X2 |\
	HRCWL_CSB_TO_CLKIN_2X1 |\
	HRCWL_CORE_TO_CSB_2X1 |\
	HRCWL_CE_PLL_VCO_DIV_2 |\
	HRCWL_CE_PLL_DIV_1X1 |\
	HRCWL_CE_TO_PLL_1X3)

#ifdef CONFIG_PCISLAVE
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_AGENT |\
	HRCWH_PCI1_ARBITER_DISABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0XFFF00100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LALE_NORMAL)
#else
#define CONFIG_SYS_HRCW_HIGH (\
	HRCWH_PCI_HOST |\
	HRCWH_PCI1_ARBITER_ENABLE |\
	HRCWH_CORE_ENABLE |\
	HRCWH_FROM_0X00000100 |\
	HRCWH_BOOTSEQ_DISABLE |\
	HRCWH_SW_WATCHDOG_DISABLE |\
	HRCWH_ROM_LOC_LOCAL_16BIT |\
	HRCWH_BIG_ENDIAN |\
	HRCWH_LALE_NORMAL)
#endif

/*
 * System IO Config
 */
#define CONFIG_SYS_SICRL		0x00000000

#define CONFIG_BOARD_EARLY_INIT_R

/*
 * IMMR new address
 */
#define CONFIG_SYS_IMMR		0xE0000000

/*
 * DDR Setup
 */
#define CONFIG_SYS_DDR_BASE	0x00000000	/* DDR is system memory */
#define CONFIG_SYS_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDR_SDRAM_BASE	CONFIG_SYS_DDR_BASE
#define CONFIG_SYS_DDRCDR	0x73000002	/* DDR II voltage is 1.8V */

#undef CONFIG_SPD_EEPROM
#if defined(CONFIG_SPD_EEPROM)
/* Determine DDR configuration from I2C interface
 */
#define SPD_EEPROM_ADDRESS	0x51	/* DDR SODIMM */
#else
/* Manually set up DDR parameters
 */
#define CONFIG_SYS_DDR_SIZE		128	/* MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	(CSCONFIG_EN \
					| CSCONFIG_AP \
					| CSCONFIG_ODT_WR_CFG \
					| CSCONFIG_ROW_BIT_13 \
					| CSCONFIG_COL_BIT_10)
					/* 0x80840102 */
#define CONFIG_SYS_DDR_TIMING_0		((0 << TIMING_CFG0_RWT_SHIFT) \
					| (0 << TIMING_CFG0_WRT_SHIFT) \
					| (0 << TIMING_CFG0_RRT_SHIFT) \
					| (0 << TIMING_CFG0_WWT_SHIFT) \
					| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
					| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
					| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
					| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
					/* 0x00220802 */
#define CONFIG_SYS_DDR_TIMING_1		((3 << TIMING_CFG1_PRETOACT_SHIFT) \
					| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
					| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
					| (5 << TIMING_CFG1_CASLAT_SHIFT) \
					| (13 << TIMING_CFG1_REFREC_SHIFT) \
					| (3 << TIMING_CFG1_WRREC_SHIFT) \
					| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
					| (2 << TIMING_CFG1_WRTORD_SHIFT))
					/* 0x3935D322 */
#define CONFIG_SYS_DDR_TIMING_2		((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
				| (31 << TIMING_CFG2_CPO_SHIFT) \
				| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
				| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
				| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
				| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
				| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
				/* 0x0F9048CA */
#define CONFIG_SYS_DDR_TIMING_3		0x00000000
#define CONFIG_SYS_DDR_CLK_CNTL		DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
					/* 0x02000000 */
#define CONFIG_SYS_DDR_MODE		((0x4440 << SDRAM_MODE_ESD_SHIFT) \
					| (0x0232 << SDRAM_MODE_SD_SHIFT))
					/* 0x44400232 */
#define CONFIG_SYS_DDR_MODE2		0x8000c000
#define CONFIG_SYS_DDR_INTERVAL		((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
					| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
					/* 0x03200064 */
#define CONFIG_SYS_DDR_CS0_BNDS		0x00000007
#define CONFIG_SYS_DDR_SDRAM_CFG	(SDRAM_CFG_SREN \
					| SDRAM_CFG_SDRAM_TYPE_DDR2 \
					| SDRAM_CFG_32_BE)
					/* 0x43080000 */
#define CONFIG_SYS_DDR_SDRAM_CFG2	0x00401000
#endif

/*
 * Memory test
 */
#undef CONFIG_SYS_DRAM_TEST		/* memory test, takes time */
#define CONFIG_SYS_MEMTEST_START	0x00000000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00100000

/*
 * The reserved memory
 */
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
#define CONFIG_SYS_MONITOR_LEN	(512 * 1024)	/* Reserve 512 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN	(256 * 1024)	/* Reserved for malloc */

/*
 * Initial RAM Base Address Setup
 */
#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xE6000000	/* Initial RAM addr */
#define CONFIG_SYS_INIT_RAM_SIZE	0x1000	/* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET	\
			(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)

/*
 * Local Bus Configuration & Clock Setup
 */
#define CONFIG_SYS_LCRR_DBYP		LCRR_DBYP
#define CONFIG_SYS_LCRR_CLKDIV		LCRR_CLKDIV_2
#define CONFIG_SYS_LBC_LBCR		0x00000000

/*
 * FLASH on the Local Bus
 */
#define CONFIG_SYS_FLASH_CFI		/* use the Common Flash Interface */
#define CONFIG_FLASH_CFI_DRIVER		/* use the CFI driver */
#define CONFIG_SYS_FLASH_BASE	0xFE000000	/* FLASH base address */
#define CONFIG_SYS_FLASH_SIZE	16	/* FLASH size is 16M */
#define CONFIG_SYS_FLASH_PROTECTION	1	/* Use h/w Flash protection. */

					/* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM	(LBLAWAR_EN | LBLAWAR_32MB)

#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE \
				| BR_PS_16	/* 16 bit port */ \
				| BR_MS_GPCM	/* MSEL = GPCM */ \
				| BR_V)		/* valid */
#define CONFIG_SYS_OR0_PRELIM	(MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
				| OR_GPCM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_ACS_DIV2 \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET \
				| OR_GPCM_EAD)
				/* 0xfe006ff7 */

#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* sectors per device */

#undef CONFIG_SYS_FLASH_CHECKSUM

/*
 * BCSR on the Local Bus
 */
#define CONFIG_SYS_BCSR			0xF8000000
					/* Access window base at BCSR base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM	CONFIG_SYS_BCSR
#define CONFIG_SYS_LBLAWAR1_PRELIM	(LBLAWAR_EN | LBLAWAR_32KB)

#define CONFIG_SYS_BR1_PRELIM		(CONFIG_SYS_BCSR \
					| BR_PS_8 \
					| BR_MS_GPCM \
					| BR_V)
#define CONFIG_SYS_OR1_PRELIM		(OR_AM_32KB \
					| OR_GPCM_XAM \
					| OR_GPCM_CSNT \
					| OR_GPCM_XACS \
					| OR_GPCM_SCY_15 \
					| OR_GPCM_TRLX_SET \
					| OR_GPCM_EHTR_SET \
					| OR_GPCM_EAD)
					/* 0xFFFFE9F7 */

/*
 * Windows to access PIB via local bus
 */
					/* PIB window base 0xF8008000 */
#define CONFIG_SYS_PIB_BASE		0xF8008000
#define CONFIG_SYS_PIB_WINDOW_SIZE	(32 * 1024)
#define CONFIG_SYS_LBLAWBAR3_PRELIM	CONFIG_SYS_PIB_BASE
#define CONFIG_SYS_LBLAWAR3_PRELIM	(LBLAWAR_EN | LBLAWAR_64KB)

/*
 * CS2 on Local Bus, to PIB
 */
#define CONFIG_SYS_BR2_PRELIM	(CONFIG_SYS_PIB_BASE \
				| BR_PS_8 \
				| BR_MS_GPCM \
				| BR_V)
				/* 0xF8008801 */
#define CONFIG_SYS_OR2_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
				| OR_GPCM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET \
				| OR_GPCM_EAD)
				/* 0xffffe9f7 */

/*
 * CS3 on Local Bus, to PIB
 */
#define CONFIG_SYS_BR3_PRELIM	((CONFIG_SYS_PIB_BASE + \
					CONFIG_SYS_PIB_WINDOW_SIZE) \
				| BR_PS_8 \
				| BR_MS_GPCM \
				| BR_V)
				/* 0xF8010801 */
#define CONFIG_SYS_OR3_PRELIM	(P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
				| OR_GPCM_XAM \
				| OR_GPCM_CSNT \
				| OR_GPCM_XACS \
				| OR_GPCM_SCY_15 \
				| OR_GPCM_TRLX_SET \
				| OR_GPCM_EHTR_SET \
				| OR_GPCM_EAD)
				/* 0xffffe9f7 */

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX	1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
		{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_IMMR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_IMMR+0x4600)

/* I2C */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x51} }

/*
 * Config on-board RTC
 */
#define CONFIG_RTC_DS1374		/* use ds1374 rtc via i2c */
#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68 */

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_MMIO_BASE	0x90000000
#define CONFIG_SYS_PCI1_MMIO_PHYS	CONFIG_SYS_PCI1_MMIO_BASE
#define CONFIG_SYS_PCI1_MMIO_SIZE	0x10000000	/* 256M */
#define CONFIG_SYS_PCI1_IO_BASE		0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS		0xE0300000
#define CONFIG_SYS_PCI1_IO_SIZE		0x100000	/* 1M */

#define CONFIG_SYS_PCI_SLV_MEM_LOCAL	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_PCI_SLV_MEM_BUS	0x00000000
#define CONFIG_SYS_PCI_SLV_MEM_SIZE	0x80000000

#ifdef CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE

#define CONFIG_83XX_PCI_STREAMING

#undef CONFIG_EEPRO100
#undef CONFIG_PCI_SCAN_SHOW	/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID	0x1957	/* Freescale */

#endif	/* CONFIG_PCI */

/*
 * QE UEC ethernet configuration
 */
#define CONFIG_UEC_ETH
#define CONFIG_ETHPRIME		"UEC0"

#define CONFIG_UEC_ETH1		/* ETH3 */

#ifdef CONFIG_UEC_ETH1
#define CONFIG_SYS_UEC1_UCC_NUM	2	/* UCC3 */
#define CONFIG_SYS_UEC1_RX_CLK		QE_CLK9
#define CONFIG_SYS_UEC1_TX_CLK		QE_CLK10
#define CONFIG_SYS_UEC1_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC1_PHY_ADDR	3
#define CONFIG_SYS_UEC1_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC1_INTERFACE_SPEED	100
#endif

#define CONFIG_UEC_ETH2		/* ETH4 */

#ifdef CONFIG_UEC_ETH2
#define CONFIG_SYS_UEC2_UCC_NUM	3	/* UCC4 */
#define CONFIG_SYS_UEC2_RX_CLK		QE_CLK7
#define CONFIG_SYS_UEC2_TX_CLK		QE_CLK8
#define CONFIG_SYS_UEC2_ETH_TYPE	FAST_ETH
#define CONFIG_SYS_UEC2_PHY_ADDR	4
#define CONFIG_SYS_UEC2_INTERFACE_TYPE	PHY_INTERFACE_MODE_MII
#define CONFIG_SYS_UEC2_INTERFACE_SPEED	100
#endif

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
	#define CONFIG_ENV_ADDR		\
			(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
	#define CONFIG_ENV_SECT_SIZE	0x20000
	#define CONFIG_ENV_SIZE		0x2000
#else
	#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
	#define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

/*
 * Command line configuration.
 */

#undef CONFIG_WATCHDOG		/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 256 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
					/* Initial Memory map for Linux */
#define CONFIG_SYS_BOOTMAPSZ		(256 << 20)
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

/*
 * Core HID Setup
 */
#define CONFIG_SYS_HID0_INIT	0x000000000
#define CONFIG_SYS_HID0_FINAL	(HID0_ENABLE_MACHINE_CHECK | \
				 HID0_ENABLE_INSTRUCTION_CACHE)
#define CONFIG_SYS_HID2		HID2_HBE

/*
 * MMU Setup
 */

#define CONFIG_HIGH_BATS	1	/* High BATs supported */

/* DDR: cache cacheable */
#define CONFIG_SYS_IBAT0L	(CONFIG_SYS_SDRAM_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U	(CONFIG_SYS_SDRAM_BASE \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT0L	CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U	CONFIG_SYS_IBAT0U

/* IMMRBAR & PCI IO: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT1L	(CONFIG_SYS_IMMR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT1U	(CONFIG_SYS_IMMR \
				| BATU_BL_4M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT1L	CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U	CONFIG_SYS_IBAT1U

/* BCSR: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L	(CONFIG_SYS_BCSR \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U	(CONFIG_SYS_BCSR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT2L	CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U	CONFIG_SYS_IBAT2U

/* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT3U	(CONFIG_SYS_FLASH_BASE \
				| BATU_BL_32M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT3L	(CONFIG_SYS_FLASH_BASE \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT3U	CONFIG_SYS_IBAT3U

#define CONFIG_SYS_IBAT4L	(0)
#define CONFIG_SYS_IBAT4U	(0)
#define CONFIG_SYS_DBAT4L	CONFIG_SYS_IBAT4L
#define CONFIG_SYS_DBAT4U	CONFIG_SYS_IBAT4U

/* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT5L	(CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
#define CONFIG_SYS_IBAT5U	(CONFIG_SYS_INIT_RAM_ADDR \
				| BATU_BL_128K \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT5L	CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U	CONFIG_SYS_IBAT5U

#ifdef CONFIG_PCI
/* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L	(CONFIG_SYS_PCI1_MEM_PHYS \
				| BATL_PP_RW \
				| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U	(CONFIG_SYS_PCI1_MEM_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L	(CONFIG_SYS_PCI1_MMIO_PHYS \
				| BATL_PP_RW \
				| BATL_CACHEINHIBIT \
				| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U	(CONFIG_SYS_PCI1_MMIO_PHYS \
				| BATU_BL_256M \
				| BATU_VS \
				| BATU_VP)
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
#else
#define CONFIG_SYS_IBAT6L	(0)
#define CONFIG_SYS_IBAT6U	(0)
#define CONFIG_SYS_IBAT7L	(0)
#define CONFIG_SYS_IBAT7U	(0)
#define CONFIG_SYS_DBAT6L	CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U	CONFIG_SYS_IBAT6U
#define CONFIG_SYS_DBAT7L	CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U	CONFIG_SYS_IBAT7U
#endif

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed of kgdb serial port */
#endif

/*
 * Environment Configuration
 */ #define CONFIG_ENV_OVERWRITE

#if defined(CONFIG_UEC_ETH)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#endif

#define CONFIG_LOADADDR	800000	/* default location for tftp and bootm */

#define CONFIG_EXTRA_ENV_SETTINGS					\
	"netdev=eth0\0"							\
	"consoledev=ttyS0\0"						\
	"ramdiskaddr=1000000\0"						\
	"ramdiskfile=ramfs.83xx\0"					\
	"fdtaddr=780000\0"						\
	"fdtfile=mpc832x_mds.dtb\0"					\
	""

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
		"nfsroot=$serverip:$rootpath "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:"	\
							"$netdev:off "	\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
		"console=$consoledev,$baudrate $othbootargs;"		\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
24c3aca3 DL	1	/*
	2	* Copyright (C) 2006 Freescale Semiconductor, Inc.
	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
24c3aca3 DL	5	*/
	6
	7	#ifndef __CONFIG_H
	8	#define __CONFIG_H
	9
24c3aca3 DL	10	/*
	11	* High Level Configuration Options
	12	*/
	13	#define CONFIG_E300 1 /* E300 family */
	14	#define CONFIG_QE 1 /* Has QE */
2c7920af	15	#define CONFIG_MPC832x 1 /* MPC832x CPU specific */
24c3aca3	16	#define CONFIG_MPC832XEMDS 1 /* MPC832XEMDS board specific */
2ae18241	17
24c3aca3 DL	18	/*
	19	* System Clock Setup
	20	*/
	21	#ifdef CONFIG_PCISLAVE
	22	#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
	23	#else
	24	#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
	25	#endif
	26
	27	#ifndef CONFIG_SYS_CLK_FREQ
	28	#define CONFIG_SYS_CLK_FREQ 66000000
	29	#endif
	30
	31	/*
	32	* Hardware Reset Configuration Word
	33	*/
6d0f6bcf	34	#define CONFIG_SYS_HRCW_LOW (\
24c3aca3 DL	35	HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \|\
	36	HRCWL_DDR_TO_SCB_CLK_2X1 \|\
	37	HRCWL_VCO_1X2 \|\
	38	HRCWL_CSB_TO_CLKIN_2X1 \|\
	39	HRCWL_CORE_TO_CSB_2X1 \|\
	40	HRCWL_CE_PLL_VCO_DIV_2 \|\
	41	HRCWL_CE_PLL_DIV_1X1 \|\
	42	HRCWL_CE_TO_PLL_1X3)
	43
	44	#ifdef CONFIG_PCISLAVE
6d0f6bcf	45	#define CONFIG_SYS_HRCW_HIGH (\
24c3aca3 DL	46	HRCWH_PCI_AGENT \|\
	47	HRCWH_PCI1_ARBITER_DISABLE \|\
	48	HRCWH_CORE_ENABLE \|\
	49	HRCWH_FROM_0XFFF00100 \|\
	50	HRCWH_BOOTSEQ_DISABLE \|\
	51	HRCWH_SW_WATCHDOG_DISABLE \|\
	52	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	53	HRCWH_BIG_ENDIAN \|\
	54	HRCWH_LALE_NORMAL)
	55	#else
6d0f6bcf	56	#define CONFIG_SYS_HRCW_HIGH (\
24c3aca3 DL	57	HRCWH_PCI_HOST \|\
	58	HRCWH_PCI1_ARBITER_ENABLE \|\
	59	HRCWH_CORE_ENABLE \|\
	60	HRCWH_FROM_0X00000100 \|\
	61	HRCWH_BOOTSEQ_DISABLE \|\
	62	HRCWH_SW_WATCHDOG_DISABLE \|\
	63	HRCWH_ROM_LOC_LOCAL_16BIT \|\
	64	HRCWH_BIG_ENDIAN \|\
	65	HRCWH_LALE_NORMAL)
	66	#endif
	67
	68	/*
	69	* System IO Config
	70	*/
6d0f6bcf	71	#define CONFIG_SYS_SICRL 0x00000000
24c3aca3	72
14778585	73	#define CONFIG_BOARD_EARLY_INIT_R
24c3aca3 DL	74
	75	/*
	76	* IMMR new address
	77	*/
6d0f6bcf	78	#define CONFIG_SYS_IMMR 0xE0000000
24c3aca3 DL	79
	80	/*
	81	* DDR Setup
	82	*/
989091ac JH	83	#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
989091ac JH	84	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
6d0f6bcf	85	#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
989091ac	86	#define CONFIG_SYS_DDRCDR 0x73000002 /* DDR II voltage is 1.8V */
24c3aca3 DL	87
	88	#undef CONFIG_SPD_EEPROM
	89	#if defined(CONFIG_SPD_EEPROM)
	90	/* Determine DDR configuration from I2C interface
	91	*/
	92	#define SPD_EEPROM_ADDRESS 0x51 /* DDR SODIMM */
	93	#else
	94	/* Manually set up DDR parameters
	95	*/
6d0f6bcf	96	#define CONFIG_SYS_DDR_SIZE 128 /* MB */
2fef4020 JH	97	#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
	98	\| CSCONFIG_AP \
	99	\| CSCONFIG_ODT_WR_CFG \
	100	\| CSCONFIG_ROW_BIT_13 \
	101	\| CSCONFIG_COL_BIT_10)
	102	/* 0x80840102 */
	103	#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
	104	\| (0 << TIMING_CFG0_WRT_SHIFT) \
	105	\| (0 << TIMING_CFG0_RRT_SHIFT) \
	106	\| (0 << TIMING_CFG0_WWT_SHIFT) \
	107	\| (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
	108	\| (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
	109	\| (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
	110	\| (2 << TIMING_CFG0_MRS_CYC_SHIFT))
	111	/* 0x00220802 */
	112	#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
	113	\| (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
	114	\| (3 << TIMING_CFG1_ACTTORW_SHIFT) \
	115	\| (5 << TIMING_CFG1_CASLAT_SHIFT) \
	116	\| (13 << TIMING_CFG1_REFREC_SHIFT) \
	117	\| (3 << TIMING_CFG1_WRREC_SHIFT) \
	118	\| (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
	119	\| (2 << TIMING_CFG1_WRTORD_SHIFT))
	120	/* 0x3935D322 */
	121	#define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
	122	\| (31 << TIMING_CFG2_CPO_SHIFT) \
	123	\| (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
	124	\| (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
	125	\| (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
	126	\| (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
	127	\| (10 << TIMING_CFG2_FOUR_ACT_SHIFT))
	128	/* 0x0F9048CA */
989091ac	129	#define CONFIG_SYS_DDR_TIMING_3 0x00000000
2fef4020 JH	130	#define CONFIG_SYS_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
	131	/* 0x02000000 */
	132	#define CONFIG_SYS_DDR_MODE ((0x4440 << SDRAM_MODE_ESD_SHIFT) \
	133	\| (0x0232 << SDRAM_MODE_SD_SHIFT))
	134	/* 0x44400232 */
6d0f6bcf	135	#define CONFIG_SYS_DDR_MODE2 0x8000c000
2fef4020 JH	136	#define CONFIG_SYS_DDR_INTERVAL ((800 << SDRAM_INTERVAL_REFINT_SHIFT) \
	137	\| (100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
	138	/* 0x03200064 */
989091ac	139	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
2fef4020 JH	140	#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
	141	\| SDRAM_CFG_SDRAM_TYPE_DDR2 \
	142	\| SDRAM_CFG_32_BE)
	143	/* 0x43080000 */
6d0f6bcf	144	#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
24c3aca3 DL	145	#endif
	146
	147	/*
	148	* Memory test
	149	*/
6d0f6bcf JCPV	150	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	151	#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
	152	#define CONFIG_SYS_MEMTEST_END 0x00100000
24c3aca3 DL	153
	154	/*
	155	* The reserved memory
	156	*/
14d0a02a	157	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
24c3aca3	158
6d0f6bcf JCPV	159	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	160	#define CONFIG_SYS_RAMBOOT
24c3aca3	161	#else
6d0f6bcf	162	#undef CONFIG_SYS_RAMBOOT
24c3aca3 DL	163	#endif
24c3aca3 DL	164
6d0f6bcf	165	/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
16c8c170	166	#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */
3b6b256c	167	#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
24c3aca3 DL	168
	169	/*
	170	* Initial RAM Base Address Setup
	171	*/
6d0f6bcf	172	#define CONFIG_SYS_INIT_RAM_LOCK 1
989091ac JH	173	#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM addr */
	174	#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
	175	#define CONFIG_SYS_GBL_DATA_OFFSET \
	176	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
24c3aca3 DL	177
	178	/*
	179	* Local Bus Configuration & Clock Setup
	180	*/
c7190f02 KP	181	#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
c7190f02 KP	182	#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
6d0f6bcf	183	#define CONFIG_SYS_LBC_LBCR 0x00000000
24c3aca3 DL	184
	185	/*
	186	* FLASH on the Local Bus
	187	*/
6d0f6bcf	188	#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
989091ac JH	189	#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
	190	#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
	191	#define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size is 16M */
	192	#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
24c3aca3	193
989091ac JH	194	/* Window base at flash base */
989091ac JH	195	#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982	196	#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN \| LBLAWAR_32MB)
24c3aca3	197
989091ac	198	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
7d6a0982 JH	199	\| BR_PS_16 /* 16 bit port */ \
	200	\| BR_MS_GPCM /* MSEL = GPCM */ \
	201	\| BR_V) /* valid */
	202	#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
	203	\| OR_GPCM_XAM \
	204	\| OR_GPCM_CSNT \
	205	\| OR_GPCM_ACS_DIV2 \
	206	\| OR_GPCM_XACS \
	207	\| OR_GPCM_SCY_15 \
	208	\| OR_GPCM_TRLX_SET \
	209	\| OR_GPCM_EHTR_SET \
	210	\| OR_GPCM_EAD)
	211	/* 0xfe006ff7 */
24c3aca3	212
989091ac JH	213	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
989091ac JH	214	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
24c3aca3	215
6d0f6bcf	216	#undef CONFIG_SYS_FLASH_CHECKSUM
24c3aca3 DL	217
	218	/*
	219	* BCSR on the Local Bus
	220	*/
989091ac JH	221	#define CONFIG_SYS_BCSR 0xF8000000
	222	/* Access window base at BCSR base */
	223	#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
7d6a0982 JH	224	#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN \| LBLAWAR_32KB)
	225
	226	#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
	227	\| BR_PS_8 \
	228	\| BR_MS_GPCM \
	229	\| BR_V)
	230	#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
	231	\| OR_GPCM_XAM \
	232	\| OR_GPCM_CSNT \
	233	\| OR_GPCM_XACS \
	234	\| OR_GPCM_SCY_15 \
	235	\| OR_GPCM_TRLX_SET \
	236	\| OR_GPCM_EHTR_SET \
	237	\| OR_GPCM_EAD)
	238	/* 0xFFFFE9F7 */
24c3aca3 DL	239
	240	/*
	241	* Windows to access PIB via local bus
	242	*/
7d6a0982 JH	243	/* PIB window base 0xF8008000 */
	244	#define CONFIG_SYS_PIB_BASE 0xF8008000
	245	#define CONFIG_SYS_PIB_WINDOW_SIZE (32 * 1024)
	246	#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PIB_BASE
	247	#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN \| LBLAWAR_64KB)
24c3aca3 DL	248
	249	/*
	250	* CS2 on Local Bus, to PIB
	251	*/
7d6a0982 JH	252	#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_PIB_BASE \
	253	\| BR_PS_8 \
	254	\| BR_MS_GPCM \
	255	\| BR_V)
	256	/* 0xF8008801 */
	257	#define CONFIG_SYS_OR2_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
	258	\| OR_GPCM_XAM \
	259	\| OR_GPCM_CSNT \
	260	\| OR_GPCM_XACS \
	261	\| OR_GPCM_SCY_15 \
	262	\| OR_GPCM_TRLX_SET \
	263	\| OR_GPCM_EHTR_SET \
	264	\| OR_GPCM_EAD)
	265	/* 0xffffe9f7 */
24c3aca3 DL	266
	267	/*
	268	* CS3 on Local Bus, to PIB
	269	*/
7d6a0982 JH	270	#define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_PIB_BASE + \
	271	CONFIG_SYS_PIB_WINDOW_SIZE) \
	272	\| BR_PS_8 \
	273	\| BR_MS_GPCM \
	274	\| BR_V)
	275	/* 0xF8010801 */
	276	#define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_PIB_WINDOW_SIZE) \
	277	\| OR_GPCM_XAM \
	278	\| OR_GPCM_CSNT \
	279	\| OR_GPCM_XACS \
	280	\| OR_GPCM_SCY_15 \
	281	\| OR_GPCM_TRLX_SET \
	282	\| OR_GPCM_EHTR_SET \
	283	\| OR_GPCM_EAD)
	284	/* 0xffffe9f7 */
24c3aca3 DL	285
	286	/*
	287	* Serial Port
	288	*/
	289	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	290	#define CONFIG_SYS_NS16550_SERIAL
	291	#define CONFIG_SYS_NS16550_REG_SIZE 1
	292	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
24c3aca3	293
6d0f6bcf	294	#define CONFIG_SYS_BAUDRATE_TABLE \
989091ac	295	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
24c3aca3	296
6d0f6bcf JCPV	297	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
6d0f6bcf JCPV	298	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
24c3aca3	299
24c3aca3	300	/* I2C */
00f792e0 HS	301	#define CONFIG_SYS_I2C
	302	#define CONFIG_SYS_I2C_FSL
	303	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	304	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	305	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	306	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
24c3aca3 DL	307
	308	/*
	309	* Config on-board RTC
	310	*/
	311	#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
6d0f6bcf	312	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
24c3aca3 DL	313
	314	/*
	315	* General PCI
	316	* Addresses are mapped 1-1.
	317	*/
9993e196 KP	318	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	319	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	320	#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
	321	#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
	322	#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
	323	#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
	324	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	325	#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
	326	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
24c3aca3	327
6d0f6bcf JCPV	328	#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
	329	#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
	330	#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
24c3aca3	331
24c3aca3	332	#ifdef CONFIG_PCI
842033e6	333	#define CONFIG_PCI_INDIRECT_BRIDGE
24c3aca3	334
9993e196	335	#define CONFIG_83XX_PCI_STREAMING
24c3aca3 DL	336
	337	#undef CONFIG_EEPRO100
	338	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	339	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
24c3aca3 DL	340
	341	#endif /* CONFIG_PCI */
	342
24c3aca3 DL	343	/*
	344	* QE UEC ethernet configuration
	345	*/
	346	#define CONFIG_UEC_ETH
78b7a8ef	347	#define CONFIG_ETHPRIME "UEC0"
24c3aca3 DL	348
	349	#define CONFIG_UEC_ETH1 /* ETH3 */
	350
	351	#ifdef CONFIG_UEC_ETH1
6d0f6bcf JCPV	352	#define CONFIG_SYS_UEC1_UCC_NUM 2 /* UCC3 */
	353	#define CONFIG_SYS_UEC1_RX_CLK QE_CLK9
	354	#define CONFIG_SYS_UEC1_TX_CLK QE_CLK10
	355	#define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH
	356	#define CONFIG_SYS_UEC1_PHY_ADDR 3
865ff856	357	#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	358	#define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
24c3aca3 DL	359	#endif
	360
	361	#define CONFIG_UEC_ETH2 /* ETH4 */
	362
	363	#ifdef CONFIG_UEC_ETH2
6d0f6bcf JCPV	364	#define CONFIG_SYS_UEC2_UCC_NUM 3 /* UCC4 */
	365	#define CONFIG_SYS_UEC2_RX_CLK QE_CLK7
	366	#define CONFIG_SYS_UEC2_TX_CLK QE_CLK8
	367	#define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH
	368	#define CONFIG_SYS_UEC2_PHY_ADDR 4
865ff856	369	#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
582c55a0	370	#define CONFIG_SYS_UEC2_INTERFACE_SPEED 100
24c3aca3 DL	371	#endif
	372
	373	/*
	374	* Environment
	375	*/
6d0f6bcf	376	#ifndef CONFIG_SYS_RAMBOOT
989091ac JH	377	#define CONFIG_ENV_ADDR \
989091ac JH	378	(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
0e8d1586 JCPV	379	#define CONFIG_ENV_SECT_SIZE 0x20000
0e8d1586 JCPV	380	#define CONFIG_ENV_SIZE 0x2000
24c3aca3	381	#else
6d0f6bcf	382	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	383	#define CONFIG_ENV_SIZE 0x2000
24c3aca3 DL	384	#endif
	385
	386	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	387	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
24c3aca3	388
079a136c JL	389	/*
	390	* BOOTP options
	391	*/
	392	#define CONFIG_BOOTP_BOOTFILESIZE
079a136c	393
8ea5499a JL	394	/*
	395	* Command line configuration.
	396	*/
8ea5499a	397
24c3aca3 DL	398	#undef CONFIG_WATCHDOG /* watchdog disabled */
	399
	400	/*
	401	* Miscellaneous configurable options
	402	*/
989091ac	403	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
24c3aca3	404
24c3aca3 DL	405	/*
24c3aca3 DL	406	* For booting Linux, the board info and command line data
9f530d59	407	* have to be in the first 256 MB of memory, since this is
24c3aca3 DL	408	* the maximum mapped by the Linux kernel during initialization.
24c3aca3 DL	409	*/
989091ac JH	410	/* Initial Memory map for Linux */
989091ac JH	411	#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
63865278	412	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
24c3aca3 DL	413
	414	/*
	415	* Core HID Setup
	416	*/
1a2e203b KP	417	#define CONFIG_SYS_HID0_INIT 0x000000000
	418	#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \| \
	419	HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf	420	#define CONFIG_SYS_HID2 HID2_HBE
24c3aca3	421
24c3aca3 DL	422	/*
	423	* MMU Setup
	424	*/
	425
31d82672 BB	426	#define CONFIG_HIGH_BATS 1 /* High BATs supported */
31d82672 BB	427
24c3aca3	428	/* DDR: cache cacheable */
989091ac	429	#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087	430	\| BATL_PP_RW \
989091ac JH	431	\| BATL_MEMCOHERENCE)
	432	#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
	433	\| BATU_BL_256M \
	434	\| BATU_VS \
	435	\| BATU_VP)
6d0f6bcf JCPV	436	#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
6d0f6bcf JCPV	437	#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
24c3aca3 DL	438
24c3aca3 DL	439	/* IMMRBAR & PCI IO: cache-inhibit and guarded */
989091ac	440	#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
72cd4087	441	\| BATL_PP_RW \
989091ac JH	442	\| BATL_CACHEINHIBIT \
	443	\| BATL_GUARDEDSTORAGE)
	444	#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
	445	\| BATU_BL_4M \
	446	\| BATU_VS \
	447	\| BATU_VP)
6d0f6bcf JCPV	448	#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
6d0f6bcf JCPV	449	#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
24c3aca3 DL	450
24c3aca3 DL	451	/* BCSR: cache-inhibit and guarded */
989091ac	452	#define CONFIG_SYS_IBAT2L (CONFIG_SYS_BCSR \
72cd4087	453	\| BATL_PP_RW \
989091ac JH	454	\| BATL_CACHEINHIBIT \
	455	\| BATL_GUARDEDSTORAGE)
	456	#define CONFIG_SYS_IBAT2U (CONFIG_SYS_BCSR \
	457	\| BATU_BL_128K \
	458	\| BATU_VS \
	459	\| BATU_VP)
6d0f6bcf JCPV	460	#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
6d0f6bcf JCPV	461	#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
24c3aca3 DL	462
24c3aca3 DL	463	/* FLASH: icache cacheable, but dcache-inhibit and guarded */
989091ac	464	#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
72cd4087	465	\| BATL_PP_RW \
989091ac JH	466	\| BATL_MEMCOHERENCE)
	467	#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
	468	\| BATU_BL_32M \
	469	\| BATU_VS \
	470	\| BATU_VP)
	471	#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
72cd4087	472	\| BATL_PP_RW \
989091ac JH	473	\| BATL_CACHEINHIBIT \
989091ac JH	474	\| BATL_GUARDEDSTORAGE)
6d0f6bcf	475	#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
24c3aca3	476
6d0f6bcf JCPV	477	#define CONFIG_SYS_IBAT4L (0)
	478	#define CONFIG_SYS_IBAT4U (0)
	479	#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
	480	#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
24c3aca3 DL	481
24c3aca3 DL	482	/* Stack in dcache: cacheable, no memory coherence */
72cd4087	483	#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR \| BATL_PP_RW)
989091ac JH	484	#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
	485	\| BATU_BL_128K \
	486	\| BATU_VS \
	487	\| BATU_VP)
6d0f6bcf JCPV	488	#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
6d0f6bcf JCPV	489	#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
24c3aca3 DL	490
	491	#ifdef CONFIG_PCI
	492	/* PCI MEM space: cacheable */
989091ac	493	#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
72cd4087	494	\| BATL_PP_RW \
989091ac JH	495	\| BATL_MEMCOHERENCE)
	496	#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
	497	\| BATU_BL_256M \
	498	\| BATU_VS \
	499	\| BATU_VP)
6d0f6bcf JCPV	500	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
6d0f6bcf JCPV	501	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
24c3aca3	502	/* PCI MMIO space: cache-inhibit and guarded */
989091ac	503	#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
72cd4087	504	\| BATL_PP_RW \
989091ac JH	505	\| BATL_CACHEINHIBIT \
	506	\| BATL_GUARDEDSTORAGE)
	507	#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
	508	\| BATU_BL_256M \
	509	\| BATU_VS \
	510	\| BATU_VP)
6d0f6bcf JCPV	511	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
6d0f6bcf JCPV	512	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
24c3aca3	513	#else
6d0f6bcf JCPV	514	#define CONFIG_SYS_IBAT6L (0)
	515	#define CONFIG_SYS_IBAT6U (0)
	516	#define CONFIG_SYS_IBAT7L (0)
	517	#define CONFIG_SYS_IBAT7U (0)
	518	#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
	519	#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
	520	#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
	521	#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
24c3aca3 DL	522	#endif
24c3aca3 DL	523
8ea5499a	524	#if defined(CONFIG_CMD_KGDB)
24c3aca3	525	#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
24c3aca3 DL	526	#endif
	527
	528	/*
	529	* Environment Configuration
9993e196	530	*/ #define CONFIG_ENV_OVERWRITE
24c3aca3 DL	531
24c3aca3 DL	532	#if defined(CONFIG_UEC_ETH)
977b5758	533	#define CONFIG_HAS_ETH0
24c3aca3	534	#define CONFIG_HAS_ETH1
24c3aca3 DL	535	#endif
24c3aca3 DL	536
79f516bc	537	#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
24c3aca3	538
24c3aca3	539	#define CONFIG_EXTRA_ENV_SETTINGS \
989091ac JH	540	"netdev=eth0\0" \
	541	"consoledev=ttyS0\0" \
	542	"ramdiskaddr=1000000\0" \
	543	"ramdiskfile=ramfs.83xx\0" \
	544	"fdtaddr=780000\0" \
	545	"fdtfile=mpc832x_mds.dtb\0" \
	546	""
24c3aca3 DL	547
24c3aca3 DL	548	#define CONFIG_NFSBOOTCOMMAND \
989091ac JH	549	"setenv bootargs root=/dev/nfs rw " \
	550	"nfsroot=$serverip:$rootpath " \
	551	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
	552	"$netdev:off " \
	553	"console=$consoledev,$baudrate $othbootargs;" \
	554	"tftp $loadaddr $bootfile;" \
	555	"tftp $fdtaddr $fdtfile;" \
	556	"bootm $loadaddr - $fdtaddr"
24c3aca3 DL	557
24c3aca3 DL	558	#define CONFIG_RAMBOOTCOMMAND \
989091ac JH	559	"setenv bootargs root=/dev/ram rw " \
	560	"console=$consoledev,$baudrate $othbootargs;" \
	561	"tftp $ramdiskaddr $ramdiskfile;" \
	562	"tftp $loadaddr $bootfile;" \
	563	"tftp $fdtaddr $fdtfile;" \
	564	"bootm $loadaddr $ramdiskaddr $fdtaddr"
24c3aca3	565
24c3aca3 DL	566	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	567
	568	#endif /* __CONFIG_H */