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Commit | Line | Data |
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991425fe | 1 | /* |
2ae18241 | 2 | * (C) Copyright 2006-2010 |
991425fe MB |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
4 | * | |
3765b3e7 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
991425fe MB |
6 | */ |
7 | ||
8 | /* | |
9 | * mpc8349emds board configuration file | |
10 | * | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
991425fe MB |
16 | /* |
17 | * High Level Configuration Options | |
18 | */ | |
19 | #define CONFIG_E300 1 /* E300 Family */ | |
2c7920af | 20 | #define CONFIG_MPC834x 1 /* MPC834x family */ |
991425fe | 21 | #define CONFIG_MPC8349 1 /* MPC8349 specific */ |
991425fe | 22 | |
2ae18241 WD |
23 | #define CONFIG_PCI_66M |
24 | #ifdef CONFIG_PCI_66M | |
991425fe MB |
25 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ |
26 | #else | |
27 | #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ | |
28 | #endif | |
29 | ||
447ad576 | 30 | #ifdef CONFIG_PCISLAVE |
447ad576 IS |
31 | #define CONFIG_83XX_PCICLK 66666666 /* in Hz */ |
32 | #endif /* CONFIG_PCISLAVE */ | |
33 | ||
991425fe | 34 | #ifndef CONFIG_SYS_CLK_FREQ |
2ae18241 | 35 | #ifdef CONFIG_PCI_66M |
991425fe | 36 | #define CONFIG_SYS_CLK_FREQ 66000000 |
8fe9bf61 | 37 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 |
991425fe MB |
38 | #else |
39 | #define CONFIG_SYS_CLK_FREQ 33000000 | |
8fe9bf61 | 40 | #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_8X1 |
991425fe MB |
41 | #endif |
42 | #endif | |
43 | ||
6d0f6bcf | 44 | #define CONFIG_SYS_IMMR 0xE0000000 |
991425fe | 45 | |
32795eca | 46 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
6d0f6bcf JCPV |
47 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */ |
48 | #define CONFIG_SYS_MEMTEST_END 0x00100000 | |
991425fe MB |
49 | |
50 | /* | |
51 | * DDR Setup | |
52 | */ | |
8d172c0f | 53 | #define CONFIG_DDR_ECC /* support DDR ECC function */ |
d326f4a2 | 54 | #define CONFIG_DDR_ECC_CMD /* use DDR ECC user commands */ |
991425fe MB |
55 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ |
56 | ||
d4b91066 | 57 | /* |
d26e34c4 YS |
58 | * SYS_FSL_DDR2 is selected in Kconfig to use unified DDR driver |
59 | * unselect it to use old spd_sdram.c | |
d4b91066 | 60 | */ |
d4b91066 YS |
61 | #define CONFIG_SYS_SPD_BUS_NUM 0 |
62 | #define SPD_EEPROM_ADDRESS1 0x52 | |
63 | #define SPD_EEPROM_ADDRESS2 0x51 | |
d4b91066 YS |
64 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 |
65 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
66 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER | |
67 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
d4b91066 | 68 | |
dc9e499c RJ |
69 | /* |
70 | * 32-bit data path mode. | |
cf48eb9a | 71 | * |
dc9e499c RJ |
72 | * Please note that using this mode for devices with the real density of 64-bit |
73 | * effectively reduces the amount of available memory due to the effect of | |
74 | * wrapping around while translating address to row/columns, for example in the | |
75 | * 256MB module the upper 128MB get aliased with contents of the lower | |
76 | * 128MB); normally this define should be used for devices with real 32-bit | |
cf48eb9a | 77 | * data path. |
dc9e499c RJ |
78 | */ |
79 | #undef CONFIG_DDR_32BIT | |
80 | ||
32795eca JH |
81 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
82 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
6d0f6bcf | 83 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE |
32795eca JH |
84 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \ |
85 | | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05) | |
991425fe MB |
86 | #undef CONFIG_DDR_2T_TIMING |
87 | ||
8d172c0f XX |
88 | /* |
89 | * DDRCDR - DDR Control Driver Register | |
90 | */ | |
6d0f6bcf | 91 | #define CONFIG_SYS_DDRCDR_VALUE 0x80080001 |
8d172c0f | 92 | |
991425fe | 93 | #if defined(CONFIG_SPD_EEPROM) |
dc9e499c RJ |
94 | /* |
95 | * Determine DDR configuration from I2C interface. | |
96 | */ | |
97 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
991425fe | 98 | #else |
dc9e499c RJ |
99 | /* |
100 | * Manually set up DDR parameters | |
101 | */ | |
6d0f6bcf | 102 | #define CONFIG_SYS_DDR_SIZE 256 /* MB */ |
8d172c0f | 103 | #if defined(CONFIG_DDR_II) |
6d0f6bcf | 104 | #define CONFIG_SYS_DDRCDR 0x80080001 |
32795eca | 105 | #define CONFIG_SYS_DDR_CS2_BNDS 0x0000000f |
6d0f6bcf | 106 | #define CONFIG_SYS_DDR_CS2_CONFIG 0x80330102 |
32795eca JH |
107 | #define CONFIG_SYS_DDR_TIMING_0 0x00220802 |
108 | #define CONFIG_SYS_DDR_TIMING_1 0x38357322 | |
109 | #define CONFIG_SYS_DDR_TIMING_2 0x2f9048c8 | |
110 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
111 | #define CONFIG_SYS_DDR_CLK_CNTL 0x02000000 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_DDR_MODE 0x47d00432 |
113 | #define CONFIG_SYS_DDR_MODE2 0x8000c000 | |
32795eca | 114 | #define CONFIG_SYS_DDR_INTERVAL 0x03cf0080 |
6d0f6bcf JCPV |
115 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 |
116 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 | |
8d172c0f | 117 | #else |
2e651b24 | 118 | #define CONFIG_SYS_DDR_CS2_CONFIG (CSCONFIG_EN \ |
32795eca JH |
119 | | CSCONFIG_ROW_BIT_13 \ |
120 | | CSCONFIG_COL_BIT_10) | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_DDR_TIMING_1 0x36332321 |
122 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */ | |
32795eca | 123 | #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */ |
6d0f6bcf | 124 | #define CONFIG_SYS_DDR_INTERVAL 0x04060100 /* autocharge,no open page */ |
dc9e499c RJ |
125 | |
126 | #if defined(CONFIG_DDR_32BIT) | |
127 | /* set burst length to 8 for 32-bit data path */ | |
32795eca JH |
128 | /* DLL,normal,seq,4/2.5, 8 burst len */ |
129 | #define CONFIG_SYS_DDR_MODE 0x00000023 | |
dc9e499c RJ |
130 | #else |
131 | /* the default burst length is 4 - for 64-bit data path */ | |
32795eca JH |
132 | /* DLL,normal,seq,4/2.5, 4 burst len */ |
133 | #define CONFIG_SYS_DDR_MODE 0x00000022 | |
dc9e499c | 134 | #endif |
991425fe | 135 | #endif |
8d172c0f | 136 | #endif |
991425fe MB |
137 | |
138 | /* | |
139 | * SDRAM on the Local Bus | |
140 | */ | |
6d0f6bcf JCPV |
141 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xF0000000 /* Localbus SDRAM */ |
142 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
991425fe MB |
143 | |
144 | /* | |
145 | * FLASH on the Local Bus | |
146 | */ | |
32795eca JH |
147 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
148 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
6d0f6bcf | 149 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
32795eca JH |
150 | #define CONFIG_SYS_FLASH_SIZE 32 /* max flash size in MB */ |
151 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
6d0f6bcf | 152 | /* #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE */ |
991425fe | 153 | |
7d6a0982 JH |
154 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ |
155 | | BR_PS_16 /* 16 bit port */ \ | |
156 | | BR_MS_GPCM /* MSEL = GPCM */ \ | |
157 | | BR_V) /* valid */ | |
158 | #define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | |
32795eca JH |
159 | | OR_UPM_XAM \ |
160 | | OR_GPCM_CSNT \ | |
161 | | OR_GPCM_ACS_DIV2 \ | |
162 | | OR_GPCM_XACS \ | |
163 | | OR_GPCM_SCY_15 \ | |
7d6a0982 JH |
164 | | OR_GPCM_TRLX_SET \ |
165 | | OR_GPCM_EHTR_SET \ | |
32795eca | 166 | | OR_GPCM_EAD) |
7d6a0982 | 167 | |
32795eca JH |
168 | /* window base at flash base */ |
169 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE | |
7d6a0982 | 170 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) |
991425fe | 171 | |
32795eca JH |
172 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
173 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ | |
991425fe | 174 | |
6d0f6bcf JCPV |
175 | #undef CONFIG_SYS_FLASH_CHECKSUM |
176 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
177 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
991425fe | 178 | |
14d0a02a | 179 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
991425fe | 180 | |
6d0f6bcf JCPV |
181 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
182 | #define CONFIG_SYS_RAMBOOT | |
991425fe | 183 | #else |
6d0f6bcf | 184 | #undef CONFIG_SYS_RAMBOOT |
991425fe MB |
185 | #endif |
186 | ||
187 | /* | |
188 | * BCSR register on local bus 32KB, 8-bit wide for MDS config reg | |
189 | */ | |
32795eca JH |
190 | #define CONFIG_SYS_BCSR 0xE2400000 |
191 | /* Access window base at BCSR base */ | |
192 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR | |
7d6a0982 JH |
193 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) |
194 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \ | |
195 | | BR_PS_8 \ | |
196 | | BR_MS_GPCM \ | |
197 | | BR_V) | |
198 | /* 0x00000801 */ | |
199 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ | |
200 | | OR_GPCM_XAM \ | |
201 | | OR_GPCM_CSNT \ | |
202 | | OR_GPCM_SCY_15 \ | |
203 | | OR_GPCM_TRLX_CLEAR \ | |
204 | | OR_GPCM_EHTR_CLEAR) | |
205 | /* 0xFFFFE8F0 */ | |
991425fe | 206 | |
6d0f6bcf | 207 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
32795eca JH |
208 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM addr */ |
209 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ | |
991425fe | 210 | |
32795eca JH |
211 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
212 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
6d0f6bcf | 213 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
991425fe | 214 | |
16c8c170 | 215 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ |
c8a90646 | 216 | #define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
991425fe MB |
217 | |
218 | /* | |
219 | * Local Bus LCRR and LBCR regs | |
220 | * LCRR: DLL bypass, Clock divider is 4 | |
221 | * External Local Bus rate is | |
222 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
223 | */ | |
32795eca JH |
224 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
225 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 226 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
991425fe | 227 | |
8d172c0f XX |
228 | /* |
229 | * The MPC834xEA MDS for 834xE rev3.1 may not be assembled SDRAM memory. | |
6d0f6bcf | 230 | * if board has SRDAM on local bus, you can define CONFIG_SYS_LB_SDRAM |
8d172c0f | 231 | */ |
6d0f6bcf | 232 | #undef CONFIG_SYS_LB_SDRAM |
991425fe | 233 | |
6d0f6bcf | 234 | #ifdef CONFIG_SYS_LB_SDRAM |
991425fe MB |
235 | /* Local bus BR2, OR2 definition for SDRAM if soldered on the MDS board */ |
236 | /* | |
237 | * Base Register 2 and Option Register 2 configure SDRAM. | |
6d0f6bcf | 238 | * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. |
991425fe MB |
239 | * |
240 | * For BR2, need: | |
241 | * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0 | |
242 | * port-size = 32-bits = BR2[19:20] = 11 | |
243 | * no parity checking = BR2[21:22] = 00 | |
244 | * SDRAM for MSEL = BR2[24:26] = 011 | |
245 | * Valid = BR[31] = 1 | |
246 | * | |
247 | * 0 4 8 12 16 20 24 28 | |
248 | * 1111 0000 0000 0000 0001 1000 0110 0001 = F0001861 | |
991425fe MB |
249 | */ |
250 | ||
7d6a0982 JH |
251 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LBC_SDRAM_BASE \ |
252 | | BR_PS_32 /* 32-bit port */ \ | |
253 | | BR_MS_SDRAM /* MSEL = SDRAM */ \ | |
254 | | BR_V) /* Valid */ | |
255 | /* 0xF0001861 */ | |
256 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_LBC_SDRAM_BASE | |
257 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) | |
991425fe MB |
258 | |
259 | /* | |
6d0f6bcf | 260 | * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. |
991425fe MB |
261 | * |
262 | * For OR2, need: | |
263 | * 64MB mask for AM, OR2[0:7] = 1111 1100 | |
264 | * XAM, OR2[17:18] = 11 | |
265 | * 9 columns OR2[19-21] = 010 | |
266 | * 13 rows OR2[23-25] = 100 | |
267 | * EAD set for extra time OR[31] = 1 | |
268 | * | |
269 | * 0 4 8 12 16 20 24 28 | |
270 | * 1111 1100 0000 0000 0110 1001 0000 0001 = FC006901 | |
271 | */ | |
272 | ||
7d6a0982 JH |
273 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB \ |
274 | | OR_SDRAM_XAM \ | |
275 | | ((9 - OR_SDRAM_MIN_COLS) << OR_SDRAM_COLS_SHIFT) \ | |
276 | | ((13 - OR_SDRAM_MIN_ROWS) << OR_SDRAM_ROWS_SHIFT) \ | |
277 | | OR_SDRAM_EAD) | |
278 | /* 0xFC006901 */ | |
991425fe | 279 | |
32795eca JH |
280 | /* LB sdram refresh timer, about 6us */ |
281 | #define CONFIG_SYS_LBC_LSRT 0x32000000 | |
282 | /* LB refresh timer prescal, 266MHz/32 */ | |
283 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
991425fe | 284 | |
32795eca | 285 | #define CONFIG_SYS_LBC_LSDMR_COMMON (LSDMR_RFEN \ |
540dcf1c KG |
286 | | LSDMR_BSMA1516 \ |
287 | | LSDMR_RFCR8 \ | |
288 | | LSDMR_PRETOACT6 \ | |
289 | | LSDMR_ACTTORW3 \ | |
290 | | LSDMR_BL8 \ | |
291 | | LSDMR_WRC3 \ | |
32795eca | 292 | | LSDMR_CL3) |
991425fe MB |
293 | |
294 | /* | |
295 | * SDRAM Controller configuration sequence. | |
296 | */ | |
540dcf1c KG |
297 | #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) |
298 | #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
299 | #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) | |
300 | #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) | |
301 | #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) | |
991425fe MB |
302 | #endif |
303 | ||
304 | /* | |
305 | * Serial Port | |
306 | */ | |
307 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
308 | #define CONFIG_SYS_NS16550_SERIAL |
309 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
310 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
991425fe | 311 | |
6d0f6bcf | 312 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
32795eca | 313 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
991425fe | 314 | |
6d0f6bcf JCPV |
315 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500) |
316 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) | |
991425fe | 317 | |
991425fe | 318 | /* I2C */ |
00f792e0 HS |
319 | #define CONFIG_SYS_I2C |
320 | #define CONFIG_SYS_I2C_FSL | |
321 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
322 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
323 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
324 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
325 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
326 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
327 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
991425fe | 328 | |
80ddd226 | 329 | /* SPI */ |
80ddd226 | 330 | #undef CONFIG_SOFT_SPI /* SPI bit-banged */ |
80ddd226 BW |
331 | |
332 | /* GPIOs. Used as SPI chip selects */ | |
6d0f6bcf JCPV |
333 | #define CONFIG_SYS_GPIO1_PRELIM |
334 | #define CONFIG_SYS_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ | |
335 | #define CONFIG_SYS_GPIO1_DAT 0xC0000000 /* Both are active LOW */ | |
80ddd226 | 336 | |
991425fe | 337 | /* TSEC */ |
6d0f6bcf | 338 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
32795eca | 339 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) |
6d0f6bcf | 340 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
32795eca | 341 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) |
991425fe | 342 | |
8fe9bf61 | 343 | /* USB */ |
6d0f6bcf | 344 | #define CONFIG_SYS_USE_MPC834XSYS_USB_PHY 1 /* Use SYS board PHY */ |
991425fe MB |
345 | |
346 | /* | |
347 | * General PCI | |
348 | * Addresses are mapped 1-1. | |
349 | */ | |
6d0f6bcf JCPV |
350 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
351 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
352 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
353 | #define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000 | |
354 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
355 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
32795eca JH |
356 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 |
357 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
358 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
6d0f6bcf JCPV |
359 | |
360 | #define CONFIG_SYS_PCI2_MEM_BASE 0xA0000000 | |
361 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
362 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
363 | #define CONFIG_SYS_PCI2_MMIO_BASE 0xB0000000 | |
364 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
365 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
32795eca JH |
366 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 |
367 | #define CONFIG_SYS_PCI2_IO_PHYS 0xE2100000 | |
368 | #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ | |
991425fe MB |
369 | |
370 | #if defined(CONFIG_PCI) | |
371 | ||
8fe9bf61 | 372 | #define PCI_ONE_PCI1 |
991425fe MB |
373 | #if defined(PCI_64BIT) |
374 | #undef PCI_ALL_PCI1 | |
375 | #undef PCI_TWO_PCI1 | |
376 | #undef PCI_ONE_PCI1 | |
377 | #endif | |
378 | ||
162338e1 | 379 | #define CONFIG_83XX_PCI_STREAMING |
991425fe MB |
380 | |
381 | #undef CONFIG_EEPRO100 | |
382 | #undef CONFIG_TULIP | |
383 | ||
384 | #if !defined(CONFIG_PCI_PNP) | |
385 | #define PCI_ENET0_IOADDR 0xFIXME | |
386 | #define PCI_ENET0_MEMADDR 0xFIXME | |
53677ef1 | 387 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
991425fe MB |
388 | #endif |
389 | ||
390 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
6d0f6bcf | 391 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ |
991425fe MB |
392 | |
393 | #endif /* CONFIG_PCI */ | |
394 | ||
395 | /* | |
396 | * TSEC configuration | |
397 | */ | |
32795eca | 398 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ |
991425fe MB |
399 | |
400 | #if defined(CONFIG_TSEC_ENET) | |
991425fe MB |
401 | |
402 | #define CONFIG_GMII 1 /* MII PHY management */ | |
32795eca | 403 | #define CONFIG_TSEC1 1 |
255a3577 | 404 | #define CONFIG_TSEC1_NAME "TSEC0" |
32795eca | 405 | #define CONFIG_TSEC2 1 |
255a3577 | 406 | #define CONFIG_TSEC2_NAME "TSEC1" |
991425fe MB |
407 | #define TSEC1_PHY_ADDR 0 |
408 | #define TSEC2_PHY_ADDR 1 | |
409 | #define TSEC1_PHYIDX 0 | |
410 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
411 | #define TSEC1_FLAGS TSEC_GIGABIT |
412 | #define TSEC2_FLAGS TSEC_GIGABIT | |
991425fe MB |
413 | |
414 | /* Options are: TSEC[0-1] */ | |
415 | #define CONFIG_ETHPRIME "TSEC0" | |
416 | ||
417 | #endif /* CONFIG_TSEC_ENET */ | |
418 | ||
419 | /* | |
420 | * Configure on-board RTC | |
421 | */ | |
32795eca JH |
422 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ |
423 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
991425fe MB |
424 | |
425 | /* | |
426 | * Environment | |
427 | */ | |
6d0f6bcf | 428 | #ifndef CONFIG_SYS_RAMBOOT |
32795eca JH |
429 | #define CONFIG_ENV_ADDR \ |
430 | (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) | |
0e8d1586 JCPV |
431 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
432 | #define CONFIG_ENV_SIZE 0x2000 | |
991425fe MB |
433 | |
434 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
435 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) |
436 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
991425fe MB |
437 | |
438 | #else | |
6d0f6bcf | 439 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 440 | #define CONFIG_ENV_SIZE 0x2000 |
991425fe MB |
441 | #endif |
442 | ||
443 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 444 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
991425fe | 445 | |
659e2f67 JL |
446 | /* |
447 | * BOOTP options | |
448 | */ | |
449 | #define CONFIG_BOOTP_BOOTFILESIZE | |
659e2f67 | 450 | |
8ea5499a JL |
451 | /* |
452 | * Command line configuration. | |
453 | */ | |
8ea5499a | 454 | |
991425fe MB |
455 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
456 | ||
457 | /* | |
458 | * Miscellaneous configurable options | |
459 | */ | |
6d0f6bcf | 460 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
991425fe | 461 | |
991425fe MB |
462 | /* |
463 | * For booting Linux, the board info and command line data | |
9f530d59 | 464 | * have to be in the first 256 MB of memory, since this is |
991425fe MB |
465 | * the maximum mapped by the Linux kernel during initialization. |
466 | */ | |
32795eca JH |
467 | /* Initial Memory map for Linux*/ |
468 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) | |
63865278 | 469 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ |
991425fe | 470 | |
6d0f6bcf | 471 | #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ |
991425fe MB |
472 | |
473 | #if 1 /*528/264*/ | |
6d0f6bcf | 474 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
475 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
476 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 477 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
478 | HRCWL_VCO_1X2 |\ |
479 | HRCWL_CORE_TO_CSB_2X1) | |
480 | #elif 0 /*396/132*/ | |
6d0f6bcf | 481 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
482 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
483 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 484 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
485 | HRCWL_VCO_1X4 |\ |
486 | HRCWL_CORE_TO_CSB_3X1) | |
487 | #elif 0 /*264/132*/ | |
6d0f6bcf | 488 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
489 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
490 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 491 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
492 | HRCWL_VCO_1X4 |\ |
493 | HRCWL_CORE_TO_CSB_2X1) | |
494 | #elif 0 /*132/132*/ | |
6d0f6bcf | 495 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
496 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
497 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 498 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
499 | HRCWL_VCO_1X4 |\ |
500 | HRCWL_CORE_TO_CSB_1X1) | |
501 | #elif 0 /*264/264 */ | |
6d0f6bcf | 502 | #define CONFIG_SYS_HRCW_LOW (\ |
991425fe MB |
503 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
504 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
8fe9bf61 | 505 | HRCWL_CSB_TO_CLKIN |\ |
991425fe MB |
506 | HRCWL_VCO_1X4 |\ |
507 | HRCWL_CORE_TO_CSB_1X1) | |
508 | #endif | |
509 | ||
447ad576 | 510 | #ifdef CONFIG_PCISLAVE |
6d0f6bcf | 511 | #define CONFIG_SYS_HRCW_HIGH (\ |
447ad576 IS |
512 | HRCWH_PCI_AGENT |\ |
513 | HRCWH_64_BIT_PCI |\ | |
514 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
515 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
516 | HRCWH_CORE_ENABLE |\ | |
517 | HRCWH_FROM_0X00000100 |\ | |
518 | HRCWH_BOOTSEQ_DISABLE |\ | |
519 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
520 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
521 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 522 | HRCWH_TSEC2M_IN_GMII) |
447ad576 | 523 | #else |
991425fe | 524 | #if defined(PCI_64BIT) |
6d0f6bcf | 525 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
526 | HRCWH_PCI_HOST |\ |
527 | HRCWH_64_BIT_PCI |\ | |
528 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
529 | HRCWH_PCI2_ARBITER_DISABLE |\ | |
530 | HRCWH_CORE_ENABLE |\ | |
531 | HRCWH_FROM_0X00000100 |\ | |
532 | HRCWH_BOOTSEQ_DISABLE |\ | |
533 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
534 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
535 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 536 | HRCWH_TSEC2M_IN_GMII) |
991425fe | 537 | #else |
6d0f6bcf | 538 | #define CONFIG_SYS_HRCW_HIGH (\ |
991425fe MB |
539 | HRCWH_PCI_HOST |\ |
540 | HRCWH_32_BIT_PCI |\ | |
541 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
542 | HRCWH_PCI2_ARBITER_ENABLE |\ | |
543 | HRCWH_CORE_ENABLE |\ | |
544 | HRCWH_FROM_0X00000100 |\ | |
545 | HRCWH_BOOTSEQ_DISABLE |\ | |
546 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
547 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
548 | HRCWH_TSEC1M_IN_GMII |\ | |
32795eca | 549 | HRCWH_TSEC2M_IN_GMII) |
447ad576 IS |
550 | #endif /* PCI_64BIT */ |
551 | #endif /* CONFIG_PCISLAVE */ | |
991425fe | 552 | |
a5fe514e LN |
553 | /* |
554 | * System performance | |
555 | */ | |
6d0f6bcf | 556 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
32795eca | 557 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ |
6d0f6bcf JCPV |
558 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ |
559 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
560 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
561 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
a5fe514e | 562 | |
991425fe | 563 | /* System IO Config */ |
3c9b1ee1 | 564 | #define CONFIG_SYS_SICRH 0 |
6d0f6bcf | 565 | #define CONFIG_SYS_SICRL SICRL_LDP_A |
991425fe | 566 | |
6d0f6bcf | 567 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
32795eca JH |
568 | #define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ |
569 | | HID0_ENABLE_INSTRUCTION_CACHE) | |
991425fe | 570 | |
32795eca | 571 | /* #define CONFIG_SYS_HID0_FINAL (\ |
991425fe MB |
572 | HID0_ENABLE_INSTRUCTION_CACHE |\ |
573 | HID0_ENABLE_M_BIT |\ | |
32795eca | 574 | HID0_ENABLE_ADDRESS_BROADCAST) */ |
991425fe | 575 | |
6d0f6bcf | 576 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 577 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
991425fe MB |
578 | |
579 | /* DDR @ 0x00000000 */ | |
32795eca | 580 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ |
72cd4087 | 581 | | BATL_PP_RW \ |
32795eca JH |
582 | | BATL_MEMCOHERENCE) |
583 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | |
584 | | BATU_BL_256M \ | |
585 | | BATU_VS \ | |
586 | | BATU_VP) | |
991425fe MB |
587 | |
588 | /* PCI @ 0x80000000 */ | |
589 | #ifdef CONFIG_PCI | |
842033e6 | 590 | #define CONFIG_PCI_INDIRECT_BRIDGE |
32795eca | 591 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE \ |
72cd4087 | 592 | | BATL_PP_RW \ |
32795eca JH |
593 | | BATL_MEMCOHERENCE) |
594 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE \ | |
595 | | BATU_BL_256M \ | |
596 | | BATU_VS \ | |
597 | | BATU_VP) | |
598 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE \ | |
72cd4087 | 599 | | BATL_PP_RW \ |
32795eca JH |
600 | | BATL_CACHEINHIBIT \ |
601 | | BATL_GUARDEDSTORAGE) | |
602 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE \ | |
603 | | BATU_BL_256M \ | |
604 | | BATU_VS \ | |
605 | | BATU_VP) | |
991425fe | 606 | #else |
6d0f6bcf JCPV |
607 | #define CONFIG_SYS_IBAT1L (0) |
608 | #define CONFIG_SYS_IBAT1U (0) | |
609 | #define CONFIG_SYS_IBAT2L (0) | |
610 | #define CONFIG_SYS_IBAT2U (0) | |
991425fe MB |
611 | #endif |
612 | ||
8fe9bf61 | 613 | #ifdef CONFIG_MPC83XX_PCI2 |
32795eca | 614 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE \ |
72cd4087 | 615 | | BATL_PP_RW \ |
32795eca JH |
616 | | BATL_MEMCOHERENCE) |
617 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE \ | |
618 | | BATU_BL_256M \ | |
619 | | BATU_VS \ | |
620 | | BATU_VP) | |
621 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE \ | |
72cd4087 | 622 | | BATL_PP_RW \ |
32795eca JH |
623 | | BATL_CACHEINHIBIT \ |
624 | | BATL_GUARDEDSTORAGE) | |
625 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE \ | |
626 | | BATU_BL_256M \ | |
627 | | BATU_VS \ | |
628 | | BATU_VP) | |
8fe9bf61 | 629 | #else |
6d0f6bcf JCPV |
630 | #define CONFIG_SYS_IBAT3L (0) |
631 | #define CONFIG_SYS_IBAT3U (0) | |
632 | #define CONFIG_SYS_IBAT4L (0) | |
633 | #define CONFIG_SYS_IBAT4U (0) | |
8fe9bf61 | 634 | #endif |
991425fe | 635 | |
8fe9bf61 | 636 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ |
32795eca | 637 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \ |
72cd4087 | 638 | | BATL_PP_RW \ |
32795eca JH |
639 | | BATL_CACHEINHIBIT \ |
640 | | BATL_GUARDEDSTORAGE) | |
641 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \ | |
642 | | BATU_BL_256M \ | |
643 | | BATU_VS \ | |
644 | | BATU_VP) | |
991425fe | 645 | |
8fe9bf61 | 646 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ |
32795eca | 647 | #define CONFIG_SYS_IBAT6L (0xF0000000 \ |
72cd4087 JH |
648 | | BATL_PP_RW \ |
649 | | BATL_MEMCOHERENCE \ | |
650 | | BATL_GUARDEDSTORAGE) | |
32795eca JH |
651 | #define CONFIG_SYS_IBAT6U (0xF0000000 \ |
652 | | BATU_BL_256M \ | |
653 | | BATU_VS \ | |
654 | | BATU_VP) | |
6d0f6bcf JCPV |
655 | |
656 | #define CONFIG_SYS_IBAT7L (0) | |
657 | #define CONFIG_SYS_IBAT7U (0) | |
658 | ||
659 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
660 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
661 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
662 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
663 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
664 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
665 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
666 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
667 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
668 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
669 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
670 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
671 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
672 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
673 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
674 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
991425fe | 675 | |
8ea5499a | 676 | #if defined(CONFIG_CMD_KGDB) |
991425fe | 677 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
991425fe MB |
678 | #endif |
679 | ||
680 | /* | |
681 | * Environment Configuration | |
682 | */ | |
683 | #define CONFIG_ENV_OVERWRITE | |
684 | ||
685 | #if defined(CONFIG_TSEC_ENET) | |
991425fe | 686 | #define CONFIG_HAS_ETH1 |
10327dc5 | 687 | #define CONFIG_HAS_ETH0 |
991425fe MB |
688 | #endif |
689 | ||
991425fe | 690 | #define CONFIG_HOSTNAME mpc8349emds |
8b3637c6 | 691 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 692 | #define CONFIG_BOOTFILE "uImage" |
991425fe | 693 | |
32795eca | 694 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
991425fe | 695 | |
991425fe | 696 | #define CONFIG_PREBOOT "echo;" \ |
32bf3d14 | 697 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
991425fe MB |
698 | "echo" |
699 | ||
700 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
701 | "netdev=eth0\0" \ | |
702 | "hostname=mpc8349emds\0" \ | |
703 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
704 | "nfsroot=${serverip}:${rootpath}\0" \ | |
705 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
706 | "addip=setenv bootargs ${bootargs} " \ | |
707 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
708 | ":${hostname}:${netdev}:off panic=1\0" \ | |
709 | "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ | |
710 | "flash_nfs=run nfsargs addip addtty;" \ | |
711 | "bootm ${kernel_addr}\0" \ | |
712 | "flash_self=run ramargs addip addtty;" \ | |
713 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
714 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ | |
715 | "bootm\0" \ | |
991425fe MB |
716 | "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ |
717 | "update=protect off fe000000 fe03ffff; " \ | |
32795eca | 718 | "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0"\ |
d8ab58b2 | 719 | "upd=run load update\0" \ |
79f516bc | 720 | "fdtaddr=780000\0" \ |
cc861f71 | 721 | "fdtfile=mpc834x_mds.dtb\0" \ |
991425fe MB |
722 | "" |
723 | ||
32795eca JH |
724 | #define CONFIG_NFSBOOTCOMMAND \ |
725 | "setenv bootargs root=/dev/nfs rw " \ | |
726 | "nfsroot=$serverip:$rootpath " \ | |
727 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \ | |
728 | "$netdev:off " \ | |
729 | "console=$consoledev,$baudrate $othbootargs;" \ | |
730 | "tftp $loadaddr $bootfile;" \ | |
731 | "tftp $fdtaddr $fdtfile;" \ | |
732 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d KP |
733 | |
734 | #define CONFIG_RAMBOOTCOMMAND \ | |
32795eca JH |
735 | "setenv bootargs root=/dev/ram rw " \ |
736 | "console=$consoledev,$baudrate $othbootargs;" \ | |
737 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
738 | "tftp $loadaddr $bootfile;" \ | |
739 | "tftp $fdtaddr $fdtfile;" \ | |
740 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
bf0b542d | 741 | |
991425fe MB |
742 | #define CONFIG_BOOTCOMMAND "run flash_self" |
743 | ||
744 | #endif /* __CONFIG_H */ |