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2ad6b513 | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) Freescale Semiconductor, Inc. 2006. |
2ad6b513 TT |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
7a78f148 | 24 | MPC8349E-mITX and MPC8349E-mITX-GP board configuration file |
2ad6b513 TT |
25 | |
26 | Memory map: | |
27 | ||
28 | 0x0000_0000-0x0FFF_FFFF DDR SDRAM (256 MB) | |
29 | 0x8000_0000-0x9FFF_FFFF PCI1 memory space (512 MB) | |
30 | 0xA000_0000-0xBFFF_FFFF PCI2 memory space (512 MB) | |
31 | 0xE000_0000-0xEFFF_FFFF IMMR (1 MB) | |
32 | 0xE200_0000-0xE2FF_FFFF PCI1 I/O space (16 MB) | |
33 | 0xE300_0000-0xE3FF_FFFF PCI2 I/O space (16 MB) | |
7a78f148 | 34 | 0xF000_0000-0xF000_FFFF Compact Flash (MPC8349E-mITX only) |
2ad6b513 | 35 | 0xF001_0000-0xF001_FFFF Local bus expansion slot |
7a78f148 TT |
36 | 0xF800_0000-0xF801_FFFF Vitesse 7385 Parallel Interface (MPC8349E-mITX only) |
37 | 0xFE00_0000-0xFE7F_FFFF First 8MB bank of Flash memory | |
38 | 0xFE80_0000-0xFEFF_FFFF Second 8MB bank of Flash memory (MPC8349E-mITX only) | |
2ad6b513 TT |
39 | |
40 | I2C address list: | |
dd520bf3 WD |
41 | Align. Board |
42 | Bus Addr Part No. Description Length Location | |
2ad6b513 | 43 | ---------------------------------------------------------------- |
dd520bf3 | 44 | I2C0 0x50 M24256-BWMN6P Board EEPROM 2 U64 |
2ad6b513 | 45 | |
dd520bf3 WD |
46 | I2C1 0x20 PCF8574 I2C Expander 0 U8 |
47 | I2C1 0x21 PCF8574 I2C Expander 0 U10 | |
48 | I2C1 0x38 PCF8574A I2C Expander 0 U8 | |
49 | I2C1 0x39 PCF8574A I2C Expander 0 U10 | |
50 | I2C1 0x51 (DDR) DDR EEPROM 1 U1 | |
51 | I2C1 0x68 DS1339 RTC 1 U68 | |
2ad6b513 TT |
52 | |
53 | Note that a given board has *either* a pair of 8574s or a pair of 8574As. | |
54 | */ | |
55 | ||
56 | #ifndef __CONFIG_H | |
57 | #define __CONFIG_H | |
58 | ||
14d0a02a | 59 | #if (CONFIG_SYS_TEXT_BASE == 0xFE000000) |
6d0f6bcf | 60 | #define CONFIG_SYS_LOWBOOT |
7a78f148 | 61 | #endif |
2ad6b513 TT |
62 | |
63 | /* | |
64 | * High Level Configuration Options | |
65 | */ | |
1a2e203b | 66 | #define CONFIG_MPC83xx 1 |
2c7920af | 67 | #define CONFIG_MPC834x /* MPC834x family (8343, 8347, 8349) */ |
2ad6b513 TT |
68 | #define CONFIG_MPC8349 /* MPC8349 specific */ |
69 | ||
2ae18241 WD |
70 | #ifndef CONFIG_SYS_TEXT_BASE |
71 | #define CONFIG_SYS_TEXT_BASE 0xFEF00000 | |
72 | #endif | |
73 | ||
6d0f6bcf | 74 | #define CONFIG_SYS_IMMR 0xE0000000 /* The IMMR is relocated to here */ |
7a78f148 | 75 | |
89c7784e TT |
76 | #define CONFIG_MISC_INIT_F |
77 | #define CONFIG_MISC_INIT_R | |
7a78f148 | 78 | |
89c7784e TT |
79 | /* |
80 | * On-board devices | |
81 | */ | |
2ad6b513 | 82 | |
7a78f148 | 83 | #ifdef CONFIG_MPC8349ITX |
2ad6b513 | 84 | #define CONFIG_COMPACT_FLASH /* The CF card interface on the back of the board */ |
89c7784e | 85 | #define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ |
c9e34fe2 | 86 | #define CONFIG_SATA_SIL3114 /* SIL3114 SATA controller */ |
c31e1326 | 87 | #define CONFIG_SYS_USB_HOST /* use the EHCI USB controller */ |
7a78f148 | 88 | #endif |
2ad6b513 | 89 | |
7a78f148 TT |
90 | #define CONFIG_PCI |
91 | #define CONFIG_RTC_DS1337 | |
2ad6b513 | 92 | #define CONFIG_HARD_I2C |
7a78f148 | 93 | #define CONFIG_TSEC_ENET /* TSEC Ethernet support */ |
2ad6b513 | 94 | |
7a78f148 TT |
95 | /* |
96 | * Device configurations | |
97 | */ | |
98 | ||
99 | /* I2C */ | |
2ad6b513 TT |
100 | #ifdef CONFIG_HARD_I2C |
101 | ||
be5e6181 | 102 | #define CONFIG_FSL_I2C |
2ad6b513 | 103 | #define CONFIG_I2C_MULTI_BUS |
6d0f6bcf JCPV |
104 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
105 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
106 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* The I2C bus for SPD */ | |
b7be63ab | 107 | #define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */ |
6d0f6bcf JCPV |
108 | |
109 | #define CONFIG_SYS_I2C_8574_ADDR1 0x20 /* I2C1, PCF8574 */ | |
110 | #define CONFIG_SYS_I2C_8574_ADDR2 0x21 /* I2C1, PCF8574 */ | |
111 | #define CONFIG_SYS_I2C_8574A_ADDR1 0x38 /* I2C1, PCF8574A */ | |
112 | #define CONFIG_SYS_I2C_8574A_ADDR2 0x39 /* I2C1, PCF8574A */ | |
113 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C0, Board EEPROM */ | |
114 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* I2C1, DS1339 RTC*/ | |
be5e6181 | 115 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C1, DDR */ |
2ad6b513 | 116 | |
6d0f6bcf JCPV |
117 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
118 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
2ad6b513 TT |
119 | |
120 | /* Don't probe these addresses: */ | |
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_I2C_NOPROBES {{1, CONFIG_SYS_I2C_8574_ADDR1}, \ |
122 | {1, CONFIG_SYS_I2C_8574_ADDR2}, \ | |
123 | {1, CONFIG_SYS_I2C_8574A_ADDR1}, \ | |
124 | {1, CONFIG_SYS_I2C_8574A_ADDR2}} | |
2ad6b513 TT |
125 | /* Bit definitions for the 8574[A] I2C expander */ |
126 | #define I2C_8574_REVISION 0x03 /* Board revision, 00=0.0, 01=0.1, 10=1.0 */ | |
127 | #define I2C_8574_CF 0x08 /* 1=Compact flash absent, 0=present */ | |
128 | #define I2C_8574_MPCICLKRN 0x10 /* MiniPCI Clk Run */ | |
129 | #define I2C_8574_PCI66 0x20 /* 0=33MHz PCI, 1=66MHz PCI */ | |
130 | #define I2C_8574_FLASHSIDE 0x40 /* 0=Reset vector from U4, 1=from U7*/ | |
131 | ||
132 | #undef CONFIG_SOFT_I2C | |
133 | ||
134 | #endif | |
135 | ||
7a78f148 TT |
136 | /* Compact Flash */ |
137 | #ifdef CONFIG_COMPACT_FLASH | |
2ad6b513 | 138 | |
6d0f6bcf JCPV |
139 | #define CONFIG_SYS_IDE_MAXBUS 1 |
140 | #define CONFIG_SYS_IDE_MAXDEVICE 1 | |
2ad6b513 | 141 | |
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 |
143 | #define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_CF_BASE | |
144 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 | |
145 | #define CONFIG_SYS_ATA_REG_OFFSET 0 | |
146 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0200 | |
147 | #define CONFIG_SYS_ATA_STRIDE 2 | |
2ad6b513 | 148 | |
7a78f148 | 149 | #define ATA_RESET_TIME 1 /* If a CF card is not inserted, time out quickly */ |
2ad6b513 | 150 | |
c9e34fe2 VG |
151 | #endif |
152 | ||
153 | /* | |
154 | * SATA | |
155 | */ | |
156 | #ifdef CONFIG_SATA_SIL3114 | |
157 | ||
158 | #define CONFIG_SYS_SATA_MAX_DEVICE 4 | |
159 | #define CONFIG_LIBATA | |
160 | #define CONFIG_LBA48 | |
2ad6b513 | 161 | |
7a78f148 | 162 | #endif |
2ad6b513 | 163 | |
c31e1326 VG |
164 | #ifdef CONFIG_SYS_USB_HOST |
165 | /* | |
166 | * Support USB | |
167 | */ | |
168 | #define CONFIG_CMD_USB | |
169 | #define CONFIG_USB_STORAGE | |
170 | #define CONFIG_USB_EHCI | |
171 | #define CONFIG_USB_EHCI_FSL | |
172 | ||
173 | /* Current USB implementation supports the only USB controller, | |
174 | * so we have to choose between the MPH or the DR ones */ | |
175 | #if 1 | |
176 | #define CONFIG_HAS_FSL_MPH_USB | |
177 | #else | |
178 | #define CONFIG_HAS_FSL_DR_USB | |
179 | #endif | |
180 | ||
181 | #endif | |
182 | ||
2ad6b513 | 183 | /* |
7a78f148 | 184 | * DDR Setup |
2ad6b513 | 185 | */ |
6d0f6bcf JCPV |
186 | #define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory*/ |
187 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
188 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
189 | #define CONFIG_SYS_83XX_DDR_USES_CS0 | |
190 | #define CONFIG_SYS_MEMTEST_START 0x1000 /* memtest region */ | |
191 | #define CONFIG_SYS_MEMTEST_END 0x2000 | |
192 | ||
193 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN | \ | |
507e2d79 | 194 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_075) |
f64702b7 | 195 | |
b7be63ab VG |
196 | #define CONFIG_VERY_BIG_RAM |
197 | #define CONFIG_MAX_MEM_MAPPED ((phys_size_t)256 << 20) | |
198 | ||
7a78f148 TT |
199 | #ifdef CONFIG_HARD_I2C |
200 | #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ | |
201 | #endif | |
202 | ||
203 | #ifndef CONFIG_SPD_EEPROM /* No SPD? Then manually set up DDR parameters */ | |
6d0f6bcf JCPV |
204 | #define CONFIG_SYS_DDR_SIZE 256 /* Mb */ |
205 | #define CONFIG_SYS_DDR_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) | |
2ad6b513 | 206 | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_DDR_TIMING_1 0x26242321 |
208 | #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45, may need tuning */ | |
2ad6b513 TT |
209 | #endif |
210 | ||
7a78f148 TT |
211 | /* |
212 | *Flash on the Local Bus | |
213 | */ | |
214 | ||
6d0f6bcf | 215 | #define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ |
00b1883a | 216 | #define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ |
6d0f6bcf JCPV |
217 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* start of FLASH */ |
218 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
219 | #define CONFIG_SYS_MAX_FLASH_SECT 135 /* 127 64KB sectors + 8 8KB sectors per device */ | |
220 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
221 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
222 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT | |
7a78f148 TT |
223 | |
224 | /* The ITX has two flash chips, but the ITX-GP has only one. To support both | |
225 | boards, we say we have two, but don't display a message if we find only one. */ | |
6d0f6bcf JCPV |
226 | #define CONFIG_SYS_FLASH_QUIET_TEST |
227 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ | |
228 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x800000} | |
229 | #define CONFIG_SYS_FLASH_SIZE 16 /* FLASH size in MB */ | |
230 | #define CONFIG_SYS_FLASH_SIZE_SHIFT 4 /* log2 of the above value */ | |
231 | #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ | |
7a78f148 | 232 | |
89c7784e TT |
233 | /* Vitesse 7385 */ |
234 | ||
235 | #ifdef CONFIG_VSC7385_ENET | |
236 | ||
237 | #define CONFIG_TSEC2 | |
238 | ||
239 | /* The flash address and size of the VSC7385 firmware image */ | |
240 | #define CONFIG_VSC7385_IMAGE 0xFEFFE000 | |
241 | #define CONFIG_VSC7385_IMAGE_SIZE 8192 | |
242 | ||
243 | #endif | |
244 | ||
7a78f148 TT |
245 | /* |
246 | * BRx, ORx, LBLAWBARx, and LBLAWARx | |
247 | */ | |
248 | ||
249 | /* Flash */ | |
2ad6b513 | 250 | |
6d0f6bcf JCPV |
251 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) |
252 | #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ | |
f9023afb | 253 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ |
2ad6b513 | 254 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) |
6d0f6bcf JCPV |
255 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
256 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) | |
2ad6b513 | 257 | |
7a78f148 | 258 | /* Vitesse 7385 */ |
2ad6b513 | 259 | |
6d0f6bcf | 260 | #define CONFIG_SYS_VSC7385_BASE 0xF8000000 |
2ad6b513 | 261 | |
89c7784e TT |
262 | #ifdef CONFIG_VSC7385_ENET |
263 | ||
6d0f6bcf JCPV |
264 | #define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_VSC7385_BASE | BR_PS_8 | BR_V) |
265 | #define CONFIG_SYS_OR1_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \ | |
7a78f148 TT |
266 | OR_GPCM_SCY_15 | OR_GPCM_SETA | OR_GPCM_TRLX | \ |
267 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
2ad6b513 | 268 | |
6d0f6bcf JCPV |
269 | #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_VSC7385_BASE |
270 | #define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) | |
2ad6b513 | 271 | |
7a78f148 | 272 | #endif |
2ad6b513 | 273 | |
7a78f148 TT |
274 | /* LED */ |
275 | ||
6d0f6bcf JCPV |
276 | #define CONFIG_SYS_LED_BASE 0xF9000000 |
277 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_LED_BASE | BR_PS_8 | BR_V) | |
278 | #define CONFIG_SYS_OR2_PRELIM (OR_AM_2MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \ | |
7a78f148 TT |
279 | OR_GPCM_XACS | OR_GPCM_SCY_9 | OR_GPCM_TRLX | \ |
280 | OR_GPCM_EHTR | OR_GPCM_EAD) | |
281 | ||
282 | /* Compact Flash */ | |
2ad6b513 TT |
283 | |
284 | #ifdef CONFIG_COMPACT_FLASH | |
285 | ||
6d0f6bcf | 286 | #define CONFIG_SYS_CF_BASE 0xF0000000 |
2ad6b513 | 287 | |
6d0f6bcf JCPV |
288 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_CF_BASE | BR_PS_16 | BR_MS_UPMA | BR_V) |
289 | #define CONFIG_SYS_OR3_PRELIM (OR_UPM_AM | OR_UPM_BI) | |
2ad6b513 | 290 | |
6d0f6bcf JCPV |
291 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_CF_BASE |
292 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_64KB) | |
2ad6b513 TT |
293 | |
294 | #endif | |
295 | ||
7a78f148 TT |
296 | /* |
297 | * U-Boot memory configuration | |
298 | */ | |
14d0a02a | 299 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
2ad6b513 | 300 | |
6d0f6bcf JCPV |
301 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
302 | #define CONFIG_SYS_RAMBOOT | |
2ad6b513 | 303 | #else |
6d0f6bcf | 304 | #undef CONFIG_SYS_RAMBOOT |
2ad6b513 TT |
305 | #endif |
306 | ||
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_INIT_RAM_LOCK |
308 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
553f0982 | 309 | #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ |
2ad6b513 | 310 | |
25ddd1fb | 311 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 312 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
2ad6b513 | 313 | |
6d0f6bcf | 314 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
4a9932a4 | 315 | #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ |
6d0f6bcf | 316 | #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ |
2ad6b513 TT |
317 | |
318 | /* | |
319 | * Local Bus LCRR and LBCR regs | |
320 | * LCRR: DLL bypass, Clock divider is 4 | |
321 | * External Local Bus rate is | |
322 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
323 | */ | |
c7190f02 KP |
324 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
325 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 326 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
2ad6b513 | 327 | |
6d0f6bcf JCPV |
328 | #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ |
329 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32*/ | |
2ad6b513 | 330 | |
2ad6b513 TT |
331 | /* |
332 | * Serial Port | |
333 | */ | |
334 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_NS16550 |
336 | #define CONFIG_SYS_NS16550_SERIAL | |
337 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
338 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
2ad6b513 | 339 | |
6d0f6bcf | 340 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
7a78f148 TT |
341 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
342 | ||
8a364f09 | 343 | #define CONFIG_CONSOLE ttyS0 |
7a78f148 | 344 | #define CONFIG_BAUDRATE 115200 |
2ad6b513 | 345 | |
6d0f6bcf JCPV |
346 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
347 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
2ad6b513 | 348 | |
bf0b542d | 349 | /* pass open firmware flat tree */ |
35cc4e48 | 350 | #define CONFIG_OF_LIBFDT 1 |
5b8bc606 KP |
351 | #define CONFIG_OF_BOARD_SETUP 1 |
352 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
2ad6b513 | 353 | |
7a78f148 TT |
354 | /* |
355 | * PCI | |
356 | */ | |
2ad6b513 TT |
357 | #ifdef CONFIG_PCI |
358 | ||
359 | #define CONFIG_MPC83XX_PCI2 | |
360 | ||
361 | /* | |
362 | * General PCI | |
363 | * Addresses are mapped 1-1. | |
364 | */ | |
6d0f6bcf JCPV |
365 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
366 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
367 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ | |
368 | #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
369 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
370 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */ | |
371 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
372 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
373 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
374 | |
375 | #ifdef CONFIG_MPC83XX_PCI2 | |
6d0f6bcf JCPV |
376 | #define CONFIG_SYS_PCI2_MEM_BASE (CONFIG_SYS_PCI1_MMIO_BASE + CONFIG_SYS_PCI1_MMIO_SIZE) |
377 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
378 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x10000000 /* 256M */ | |
379 | #define CONFIG_SYS_PCI2_MMIO_BASE (CONFIG_SYS_PCI2_MEM_BASE + CONFIG_SYS_PCI2_MEM_SIZE) | |
380 | #define CONFIG_SYS_PCI2_MMIO_PHYS CONFIG_SYS_PCI2_MMIO_BASE | |
381 | #define CONFIG_SYS_PCI2_MMIO_SIZE 0x10000000 /* 256M */ | |
382 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
383 | #define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS + CONFIG_SYS_PCI1_IO_SIZE) | |
384 | #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
2ad6b513 TT |
385 | #endif |
386 | ||
dd520bf3 | 387 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
2ad6b513 | 388 | |
2ad6b513 TT |
389 | #ifndef CONFIG_PCI_PNP |
390 | #define PCI_ENET0_IOADDR 0x00000000 | |
6d0f6bcf | 391 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI2_MEM_BASE |
2ad6b513 TT |
392 | #define PCI_IDSEL_NUMBER 0x0f /* IDSEL = AD15 */ |
393 | #endif | |
394 | ||
395 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
396 | ||
397 | #endif | |
398 | ||
2ae18241 WD |
399 | #define CONFIG_PCI_66M |
400 | #ifdef CONFIG_PCI_66M | |
7a78f148 TT |
401 | #define CONFIG_83XX_CLKIN 66666666 /* in Hz */ |
402 | #else | |
403 | #define CONFIG_83XX_CLKIN 33333333 /* in Hz */ | |
404 | #endif | |
405 | ||
2ad6b513 TT |
406 | /* TSEC */ |
407 | ||
408 | #ifdef CONFIG_TSEC_ENET | |
409 | ||
2ad6b513 | 410 | #define CONFIG_MII |
659e2f67 | 411 | #define CONFIG_PHY_GIGE /* In case CONFIG_CMD_MII is specified */ |
2ad6b513 | 412 | |
255a3577 | 413 | #define CONFIG_TSEC1 |
2ad6b513 | 414 | |
255a3577 | 415 | #ifdef CONFIG_TSEC1 |
10327dc5 | 416 | #define CONFIG_HAS_ETH0 |
255a3577 | 417 | #define CONFIG_TSEC1_NAME "TSEC0" |
6d0f6bcf | 418 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
dd520bf3 | 419 | #define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */ |
2ad6b513 | 420 | #define TSEC1_PHYIDX 0 |
3a79013e | 421 | #define TSEC1_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
422 | #endif |
423 | ||
255a3577 | 424 | #ifdef CONFIG_TSEC2 |
7a78f148 | 425 | #define CONFIG_HAS_ETH1 |
255a3577 | 426 | #define CONFIG_TSEC2_NAME "TSEC1" |
6d0f6bcf | 427 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
89c7784e | 428 | |
2ad6b513 TT |
429 | #define TSEC2_PHY_ADDR 4 |
430 | #define TSEC2_PHYIDX 0 | |
3a79013e | 431 | #define TSEC2_FLAGS TSEC_GIGABIT |
2ad6b513 TT |
432 | #endif |
433 | ||
434 | #define CONFIG_ETHPRIME "Freescale TSEC" | |
435 | ||
436 | #endif | |
437 | ||
2ad6b513 TT |
438 | /* |
439 | * Environment | |
440 | */ | |
7a78f148 TT |
441 | #define CONFIG_ENV_OVERWRITE |
442 | ||
6d0f6bcf | 443 | #ifndef CONFIG_SYS_RAMBOOT |
5a1aceb0 | 444 | #define CONFIG_ENV_IS_IN_FLASH |
6d0f6bcf | 445 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
446 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for environment */ |
447 | #define CONFIG_ENV_SIZE 0x2000 | |
2ad6b513 | 448 | #else |
6d0f6bcf | 449 | #define CONFIG_SYS_NO_FLASH /* Flash is not usable now */ |
00b1883a | 450 | #undef CONFIG_FLASH_CFI_DRIVER |
93f6d725 | 451 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
6d0f6bcf | 452 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 453 | #define CONFIG_ENV_SIZE 0x2000 |
2ad6b513 TT |
454 | #endif |
455 | ||
456 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
6d0f6bcf | 457 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ |
2ad6b513 | 458 | |
659e2f67 JL |
459 | /* |
460 | * BOOTP options | |
461 | */ | |
462 | #define CONFIG_BOOTP_BOOTFILESIZE | |
463 | #define CONFIG_BOOTP_BOOTPATH | |
464 | #define CONFIG_BOOTP_GATEWAY | |
465 | #define CONFIG_BOOTP_HOSTNAME | |
466 | ||
467 | ||
8ea5499a JL |
468 | /* |
469 | * Command line configuration. | |
470 | */ | |
471 | #include <config_cmd_default.h> | |
472 | ||
473 | #define CONFIG_CMD_CACHE | |
474 | #define CONFIG_CMD_DATE | |
475 | #define CONFIG_CMD_IRQ | |
476 | #define CONFIG_CMD_NET | |
477 | #define CONFIG_CMD_PING | |
b7be63ab | 478 | #define CONFIG_CMD_DHCP |
8ea5499a | 479 | #define CONFIG_CMD_SDRAM |
2ad6b513 | 480 | |
c31e1326 VG |
481 | #if defined(CONFIG_COMPACT_FLASH) || defined(CONFIG_SATA_SIL3114) \ |
482 | || defined(CONFIG_USB_STORAGE) | |
c9e34fe2 VG |
483 | #define CONFIG_DOS_PARTITION |
484 | #define CONFIG_CMD_FAT | |
c31e1326 | 485 | #define CONFIG_SUPPORT_VFAT |
c9e34fe2 VG |
486 | #endif |
487 | ||
2ad6b513 | 488 | #ifdef CONFIG_COMPACT_FLASH |
8ea5499a | 489 | #define CONFIG_CMD_IDE |
c9e34fe2 VG |
490 | #endif |
491 | ||
492 | #ifdef CONFIG_SATA_SIL3114 | |
493 | #define CONFIG_CMD_SATA | |
c31e1326 VG |
494 | #endif |
495 | ||
496 | #if defined(CONFIG_SATA_SIL3114) || defined(CONFIG_USB_STORAGE) | |
c9e34fe2 | 497 | #define CONFIG_CMD_EXT2 |
2ad6b513 TT |
498 | #endif |
499 | ||
500 | #ifdef CONFIG_PCI | |
8ea5499a | 501 | #define CONFIG_CMD_PCI |
2ad6b513 TT |
502 | #endif |
503 | ||
504 | #ifdef CONFIG_HARD_I2C | |
8ea5499a | 505 | #define CONFIG_CMD_I2C |
2ad6b513 TT |
506 | #endif |
507 | ||
2ad6b513 | 508 | /* Watchdog */ |
2ad6b513 | 509 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
2ad6b513 TT |
510 | |
511 | /* | |
512 | * Miscellaneous configurable options | |
513 | */ | |
6d0f6bcf | 514 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
a059e90e KP |
515 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
516 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
6d0f6bcf JCPV |
517 | #define CONFIG_SYS_HUSH_PARSER /* Use the HUSH parser */ |
518 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
7a78f148 | 519 | |
6d0f6bcf | 520 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
05f91a65 | 521 | #define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ |
7a78f148 TT |
522 | |
523 | #ifdef CONFIG_MPC8349ITX | |
6d0f6bcf | 524 | #define CONFIG_SYS_PROMPT "MPC8349E-mITX> " /* Monitor Command Prompt */ |
7a78f148 | 525 | #else |
6d0f6bcf | 526 | #define CONFIG_SYS_PROMPT "MPC8349E-mITX-GP> " /* Monitor Command Prompt */ |
7a78f148 | 527 | #endif |
2ad6b513 | 528 | |
8ea5499a | 529 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 530 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
2ad6b513 | 531 | #else |
6d0f6bcf | 532 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
2ad6b513 TT |
533 | #endif |
534 | ||
6d0f6bcf JCPV |
535 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
536 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
537 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
538 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
2ad6b513 TT |
539 | |
540 | /* | |
541 | * For booting Linux, the board info and command line data | |
9f530d59 | 542 | * have to be in the first 256 MB of memory, since this is |
2ad6b513 TT |
543 | * the maximum mapped by the Linux kernel during initialization. |
544 | */ | |
9f530d59 | 545 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
2ad6b513 | 546 | |
6d0f6bcf | 547 | #define CONFIG_SYS_HRCW_LOW (\ |
2ad6b513 TT |
548 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ |
549 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
550 | HRCWL_CSB_TO_CLKIN_4X1 |\ | |
551 | HRCWL_VCO_1X2 |\ | |
552 | HRCWL_CORE_TO_CSB_2X1) | |
553 | ||
6d0f6bcf JCPV |
554 | #ifdef CONFIG_SYS_LOWBOOT |
555 | #define CONFIG_SYS_HRCW_HIGH (\ | |
2ad6b513 | 556 | HRCWH_PCI_HOST |\ |
7a78f148 | 557 | HRCWH_32_BIT_PCI |\ |
2ad6b513 | 558 | HRCWH_PCI1_ARBITER_ENABLE |\ |
7a78f148 | 559 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
560 | HRCWH_CORE_ENABLE |\ |
561 | HRCWH_FROM_0X00000100 |\ | |
562 | HRCWH_BOOTSEQ_DISABLE |\ | |
563 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
564 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
565 | HRCWH_TSEC1M_IN_GMII |\ | |
566 | HRCWH_TSEC2M_IN_GMII ) | |
567 | #else | |
6d0f6bcf | 568 | #define CONFIG_SYS_HRCW_HIGH (\ |
2ad6b513 TT |
569 | HRCWH_PCI_HOST |\ |
570 | HRCWH_32_BIT_PCI |\ | |
571 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
7a78f148 | 572 | HRCWH_PCI2_ARBITER_ENABLE |\ |
2ad6b513 TT |
573 | HRCWH_CORE_ENABLE |\ |
574 | HRCWH_FROM_0XFFF00100 |\ | |
575 | HRCWH_BOOTSEQ_DISABLE |\ | |
576 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
577 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
578 | HRCWH_TSEC1M_IN_GMII |\ | |
579 | HRCWH_TSEC2M_IN_GMII ) | |
580 | #endif | |
581 | ||
7a78f148 TT |
582 | /* |
583 | * System performance | |
584 | */ | |
6d0f6bcf JCPV |
585 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
586 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
587 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ | |
588 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
589 | #define CONFIG_SYS_SCCR_TSEC1CM 1 /* TSEC1 clock mode (0-3) */ | |
590 | #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ | |
c31e1326 VG |
591 | #define CONFIG_SYS_SCCR_USBMPHCM 3 /* USB MPH controller's clock */ |
592 | #define CONFIG_SYS_SCCR_USBDRCM 0 /* USB DR controller's clock */ | |
2ad6b513 | 593 | |
7a78f148 TT |
594 | /* |
595 | * System IO Config | |
596 | */ | |
6d0f6bcf | 597 | #define CONFIG_SYS_SICRH SICRH_TSOBI1 /* Needed for gigabit to work on TSEC 1 */ |
c31e1326 | 598 | #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1) /* USB DR as device + USB MPH as host */ |
2ad6b513 | 599 | |
1a2e203b KP |
600 | #define CONFIG_SYS_HID0_INIT 0x00000000 |
601 | #define CONFIG_SYS_HID0_FINAL HID0_ENABLE_INSTRUCTION_CACHE | |
2ad6b513 | 602 | |
6d0f6bcf | 603 | #define CONFIG_SYS_HID2 HID2_HBE |
31d82672 | 604 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
2ad6b513 | 605 | |
7a78f148 | 606 | /* DDR */ |
6d0f6bcf JCPV |
607 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
608 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
2ad6b513 | 609 | |
7a78f148 | 610 | /* PCI */ |
2ad6b513 | 611 | #ifdef CONFIG_PCI |
6d0f6bcf JCPV |
612 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
613 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
614 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
615 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
2ad6b513 | 616 | #else |
6d0f6bcf JCPV |
617 | #define CONFIG_SYS_IBAT1L 0 |
618 | #define CONFIG_SYS_IBAT1U 0 | |
619 | #define CONFIG_SYS_IBAT2L 0 | |
620 | #define CONFIG_SYS_IBAT2U 0 | |
2ad6b513 TT |
621 | #endif |
622 | ||
623 | #ifdef CONFIG_MPC83XX_PCI2 | |
6d0f6bcf JCPV |
624 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI2_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
625 | #define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI2_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
626 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCI2_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
627 | #define CONFIG_SYS_IBAT4U (CONFIG_SYS_PCI2_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
2ad6b513 | 628 | #else |
6d0f6bcf JCPV |
629 | #define CONFIG_SYS_IBAT3L 0 |
630 | #define CONFIG_SYS_IBAT3U 0 | |
631 | #define CONFIG_SYS_IBAT4L 0 | |
632 | #define CONFIG_SYS_IBAT4U 0 | |
2ad6b513 TT |
633 | #endif |
634 | ||
635 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
6d0f6bcf JCPV |
636 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
637 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) | |
2ad6b513 TT |
638 | |
639 | /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ | |
c1230980 SW |
640 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ |
641 | BATL_GUARDEDSTORAGE) | |
6d0f6bcf JCPV |
642 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
643 | ||
644 | #define CONFIG_SYS_IBAT7L 0 | |
645 | #define CONFIG_SYS_IBAT7U 0 | |
646 | ||
647 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
648 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
649 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
650 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
651 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
652 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
653 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
654 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
655 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
656 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
657 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
658 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
659 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
660 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
661 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
662 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
2ad6b513 | 663 | |
8ea5499a | 664 | #if defined(CONFIG_CMD_KGDB) |
2ad6b513 TT |
665 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ |
666 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
667 | #endif | |
668 | ||
669 | ||
670 | /* | |
671 | * Environment Configuration | |
672 | */ | |
673 | #define CONFIG_ENV_OVERWRITE | |
674 | ||
98883332 | 675 | #define CONFIG_NETDEV eth0 |
2ad6b513 | 676 | |
7a78f148 | 677 | #ifdef CONFIG_MPC8349ITX |
2ad6b513 | 678 | #define CONFIG_HOSTNAME mpc8349emitx |
7a78f148 TT |
679 | #else |
680 | #define CONFIG_HOSTNAME mpc8349emitxgp | |
be5e6181 TT |
681 | #endif |
682 | ||
7a78f148 | 683 | /* Default path and filenames */ |
8b3637c6 | 684 | #define CONFIG_ROOTPATH "/nfsroot/rootfs" |
b3f44c21 | 685 | #define CONFIG_BOOTFILE "uImage" |
7a78f148 | 686 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
2ad6b513 | 687 | |
7a78f148 TT |
688 | #ifdef CONFIG_MPC8349ITX |
689 | #define CONFIG_FDTFILE mpc8349emitx.dtb | |
2ad6b513 | 690 | #else |
7a78f148 | 691 | #define CONFIG_FDTFILE mpc8349emitxgp.dtb |
2ad6b513 TT |
692 | #endif |
693 | ||
05f91a65 | 694 | #define CONFIG_BOOTDELAY 6 |
7a78f148 | 695 | |
2ad6b513 TT |
696 | #define XMK_STR(x) #x |
697 | #define MK_STR(x) XMK_STR(x) | |
698 | ||
98883332 TT |
699 | #define CONFIG_BOOTARGS \ |
700 | "root=/dev/nfs rw" \ | |
8b3637c6 | 701 | " nfsroot=" MK_STR(CONFIG_SERVERIP) ":" CONFIG_ROOTPATH \ |
53677ef1 | 702 | " ip=" MK_STR(CONFIG_IPADDR) ":" MK_STR(CONFIG_SERVERIP) ":" \ |
98883332 TT |
703 | MK_STR(CONFIG_GATEWAYIP) ":" MK_STR(CONFIG_NETMASK) ":" \ |
704 | MK_STR(CONFIG_HOSTNAME) ":" MK_STR(CONFIG_NETDEV) ":off" \ | |
8a364f09 | 705 | " console=" MK_STR(CONFIG_CONSOLE) "," MK_STR(CONFIG_BAUDRATE) |
98883332 | 706 | |
dd520bf3 | 707 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
53677ef1 WD |
708 | "console=" MK_STR(CONFIG_CONSOLE) "\0" \ |
709 | "netdev=" MK_STR(CONFIG_NETDEV) "\0" \ | |
710 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
711 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
14d0a02a WD |
712 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
713 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
714 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
715 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
716 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
05f91a65 | 717 | "fdtaddr=780000\0" \ |
7a78f148 | 718 | "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" |
bf0b542d | 719 | |
dd520bf3 | 720 | #define CONFIG_NFSBOOTCOMMAND \ |
7a78f148 TT |
721 | "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath" \ |
722 | " ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
723 | " console=$console,$baudrate $othbootargs; " \ | |
724 | "tftp $loadaddr $bootfile;" \ | |
725 | "tftp $fdtaddr $fdtfile;" \ | |
726 | "bootm $loadaddr - $fdtaddr" | |
bf0b542d | 727 | |
dd520bf3 | 728 | #define CONFIG_RAMBOOTCOMMAND \ |
7a78f148 TT |
729 | "setenv bootargs root=/dev/ram rw" \ |
730 | " console=$console,$baudrate $othbootargs; " \ | |
731 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
732 | "tftp $loadaddr $bootfile;" \ | |
733 | "tftp $fdtaddr $fdtfile;" \ | |
734 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
2ad6b513 TT |
735 | |
736 | #undef MK_STR | |
737 | #undef XMK_STR | |
738 | ||
739 | #endif |