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i2c, soft-i2c: switch to new multibus/multiadapter support
[people/ms/u-boot.git] / include / configs / MPC8360ERDK.h
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1/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
5 * Copyright (C) 2007 Logic Product Development, Inc.
6 * Peter Barada <peterb@logicpd.com>
7 *
8 * Copyright (C) 2007 MontaVista Software, Inc.
9 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 *
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
15 */
16
17#ifndef __CONFIG_H
18#define __CONFIG_H
19
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20/*
21 * High Level Configuration Options
22 */
23#define CONFIG_E300 1 /* E300 family */
24#define CONFIG_QE 1 /* Has QE */
0f898604 25#define CONFIG_MPC83xx 1 /* MPC83xx family */
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26#define CONFIG_MPC8360 1 /* MPC8360 CPU specific */
27#define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */
28
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29#define CONFIG_SYS_TEXT_BASE 0xFF800000
30
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31/*
32 * System Clock Setup
33 */
34#ifdef CONFIG_CLKIN_33MHZ
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35#define CONFIG_83XX_CLKIN 33333333
36#define CONFIG_SYS_CLK_FREQ 33333333
2ae18241 37#define CONFIG_PCI_33M 1
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38#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
39#else
40#define CONFIG_83XX_CLKIN 66000000
41#define CONFIG_SYS_CLK_FREQ 66000000
2ae18241 42#define CONFIG_PCI_66M 1
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43#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
44#endif /* CONFIG_CLKIN_33MHZ */
45
46/*
47 * Hardware Reset Configuration Word
48 */
6d0f6bcf 49#define CONFIG_SYS_HRCW_LOW (\
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50 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
51 HRCWL_DDR_TO_SCB_CLK_1X1 |\
52 HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
53 HRCWL_CORE_TO_CSB_2X1 |\
54 HRCWL_CE_TO_PLL_1X15)
55
6d0f6bcf 56#define CONFIG_SYS_HRCW_HIGH (\
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57 HRCWH_PCI_HOST |\
58 HRCWH_PCI1_ARBITER_ENABLE |\
59 HRCWH_PCICKDRV_ENABLE |\
60 HRCWH_CORE_ENABLE |\
61 HRCWH_FROM_0X00000100 |\
62 HRCWH_BOOTSEQ_DISABLE |\
63 HRCWH_SW_WATCHDOG_DISABLE |\
64 HRCWH_ROM_LOC_LOCAL_16BIT |\
65 HRCWH_SECONDARY_DDR_DISABLE |\
66 HRCWH_BIG_ENDIAN |\
67 HRCWH_LALE_EARLY)
68
69/*
70 * System IO Config
71 */
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72#define CONFIG_SYS_SICRH 0x00000000
73#define CONFIG_SYS_SICRL 0x40000000
fab6f556 74
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75#define CONFIG_BOARD_EARLY_INIT_R
76
77/*
78 * IMMR new address
79 */
6d0f6bcf 80#define CONFIG_SYS_IMMR 0xE0000000
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81
82/*
83 * DDR Setup
84 */
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85#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
86#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
87#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
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88#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
89 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
fab6f556 90
6d0f6bcf 91#define CONFIG_SYS_83XX_DDR_USES_CS0
fab6f556 92
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93#define CONFIG_DDR_ECC /* support DDR ECC function */
94#define CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
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95
96/*
97 * DDRCDR - DDR Control Driver Register
98 */
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99#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
100 | DDRCDR_ODT \
101 | DDRCDR_Q_DRN)
102 /* 0x80080001 */
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103
104#undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */
105
106/*
107 * Manually set up DDR parameters
108 */
109#define CONFIG_DDR_II
6d0f6bcf 110#define CONFIG_SYS_DDR_SIZE 256 /* MB */
2fef4020 111#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
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112#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
113 | CSCONFIG_ROW_BIT_13 \
114 | CSCONFIG_COL_BIT_10 \
2fef4020 115 | CSCONFIG_ODT_WR_ONLY_CURRENT)
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116#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
117 | SDRAM_CFG_ECC_EN)
6d0f6bcf 118#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
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119#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
120#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
121 | (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
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122#define CONFIG_SYS_DDR_MODE 0x47800432
123#define CONFIG_SYS_DDR_MODE2 0x8000c000
d892b2db 124
6d0f6bcf 125#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
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126 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
127 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
128 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
129 (0 << TIMING_CFG0_WWT_SHIFT) | \
130 (0 << TIMING_CFG0_RRT_SHIFT) | \
131 (0 << TIMING_CFG0_WRT_SHIFT) | \
132 (0 << TIMING_CFG0_RWT_SHIFT))
133
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134#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
135 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
136 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
137 (3 << TIMING_CFG1_WRREC_SHIFT) | \
d892b2db 138 (10 << TIMING_CFG1_REFREC_SHIFT) | \
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139 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
140 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
141 (3 << TIMING_CFG1_PRETOACT_SHIFT))
d892b2db 142
6d0f6bcf 143#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
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144 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
145 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
146 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
147 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
148 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
149 (0 << TIMING_CFG2_CPO_SHIFT))
150
6d0f6bcf 151#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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152
153/*
154 * Memory test
155 */
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156#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
157#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest region */
158#define CONFIG_SYS_MEMTEST_END 0x00100000
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159
160/*
161 * The reserved memory
162 */
14d0a02a 163#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
6d0f6bcf 164#define CONFIG_SYS_FLASH_BASE 0xFF800000 /* FLASH base address */
fab6f556 165
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166#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
167#define CONFIG_SYS_RAMBOOT
fab6f556 168#else
6d0f6bcf 169#undef CONFIG_SYS_RAMBOOT
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170#endif
171
9a986550 172#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
c8a90646 173#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */
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174
175/*
176 * Initial RAM Base Address Setup
177 */
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178#define CONFIG_SYS_INIT_RAM_LOCK 1
179#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
553f0982 180#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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181#define CONFIG_SYS_GBL_DATA_OFFSET \
182 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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183
184/*
185 * Local Bus Configuration & Clock Setup
186 */
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187#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
188#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
9a986550 189#define CONFIG_SYS_LBC_LBCR 0x00000000
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190
191/*
192 * FLASH on the Local Bus
193 */
6d0f6bcf 194#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
9a986550 195#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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196#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
197#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use intel Flash protection. */
fab6f556 198
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199 /* Window base at flash base */
200#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982 201#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
fab6f556 202
9a986550 203#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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204 | BR_PS_16 /* 16 bit port */ \
205 | BR_MS_GPCM /* MSEL = GPCM */ \
206 | BR_V) /* valid */
207#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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208 | OR_UPM_XAM \
209 | OR_GPCM_CSNT \
210 | OR_GPCM_ACS_DIV2 \
211 | OR_GPCM_XACS \
212 | OR_GPCM_SCY_15 \
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213 | OR_GPCM_TRLX_SET \
214 | OR_GPCM_EHTR_SET \
9a986550 215 | OR_GPCM_EAD)
fab6f556 216
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217#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
218#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
fab6f556 219
6d0f6bcf 220#undef CONFIG_SYS_FLASH_CHECKSUM
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221
222/*
223 * NAND flash on the local bus
224 */
6d0f6bcf 225#define CONFIG_SYS_NAND_BASE 0x60000000
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226#define CONFIG_CMD_NAND 1
227#define CONFIG_NAND_FSL_UPM 1
6d0f6bcf 228#define CONFIG_SYS_MAX_NAND_DEVICE 1
7ad95949 229#define CONFIG_MTD_NAND_VERIFY_WRITE
fab6f556 230
6d0f6bcf 231#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
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232/*
233 * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB
234 * ... What's correct?
235 */
236#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
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237
238/* Port size 8 bit, UPMA */
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239#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
240 | BR_PS_8 \
241 | BR_MS_UPMA \
242 | BR_V)
243 /* 0x60000881 */
244#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
245 /* 0xFC000001 */
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246
247/*
248 * Fujitsu MB86277 (MINT) graphics controller
249 */
6d0f6bcf 250#define CONFIG_SYS_VIDEO_BASE 0x70000000
fab6f556 251
6d0f6bcf 252#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
7d6a0982 253#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
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254
255/* Port size 32 bit, UPMB */
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256#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
257 | BR_PS_32 \
258 | BR_MS_UPMB \
259 | BR_V)
260 /* 0x000018a1 */
261#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
262 /* 0xFC000001 */
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263
264/*
265 * Serial Port
266 */
267#define CONFIG_CONS_INDEX 1
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268#define CONFIG_SYS_NS16550
269#define CONFIG_SYS_NS16550_SERIAL
270#define CONFIG_SYS_NS16550_REG_SIZE 1
271#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
fab6f556 272
6d0f6bcf 273#define CONFIG_SYS_BAUDRATE_TABLE \
9a986550 274 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
fab6f556 275
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276#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
277#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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278
279#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
9a986550 280#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
fab6f556 281/* Use the HUSH parser */
6d0f6bcf 282#define CONFIG_SYS_HUSH_PARSER
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283
284/* Pass open firmware flat tree */
285#define CONFIG_OF_LIBFDT 1
286#define CONFIG_OF_BOARD_SETUP 1
3a0cfdd5 287#define CONFIG_OF_STDOUT_VIA_ALIAS
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288
289/* I2C */
290#define CONFIG_HARD_I2C /* I2C with hardware support */
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291#define CONFIG_FSL_I2C
292#define CONFIG_I2C_MULTI_BUS
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293#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
294#define CONFIG_SYS_I2C_SLAVE 0x7F
9a986550 295#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */
6d0f6bcf 296#define CONFIG_SYS_I2C_OFFSET 0x3000
9a986550 297#define CONFIG_SYS_I2C2_OFFSET 0x3100
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298
299/*
300 * General PCI
301 * Addresses are mapped 1-1.
302 */
303#define CONFIG_PCI
fab6f556 304
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305#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
306#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
307#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
308#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
309#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
310#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
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311#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
312#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
313#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
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314
315#ifdef CONFIG_PCI
842033e6 316#define CONFIG_PCI_INDIRECT_BRIDGE
fab6f556 317
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318#define CONFIG_PCI_PNP /* do pci plug-and-play */
319
320#undef CONFIG_EEPRO100
321#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf 322#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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323
324#endif /* CONFIG_PCI */
325
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326/*
327 * QE UEC ethernet configuration
328 */
329#define CONFIG_UEC_ETH
78b7a8ef 330#define CONFIG_ETHPRIME "UEC0"
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331
332#define CONFIG_UEC_ETH1 /* GETH1 */
333
334#ifdef CONFIG_UEC_ETH1
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335#define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */
336#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
337#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
338#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
339#define CONFIG_SYS_UEC1_PHY_ADDR 2
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340#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
341#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
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342#endif
343
344#define CONFIG_UEC_ETH2 /* GETH2 */
345
346#ifdef CONFIG_UEC_ETH2
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347#define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */
348#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
349#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
350#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
351#define CONFIG_SYS_UEC2_PHY_ADDR 4
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352#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
353#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
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354#endif
355
356/*
357 * Environment
358 */
359
6d0f6bcf 360#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0 361#define CONFIG_ENV_IS_IN_FLASH 1
9a986550 362#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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363#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
364#define CONFIG_ENV_SIZE 0x20000
6d0f6bcf 365#else /* CONFIG_SYS_RAMBOOT */
9a986550 366#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725 367#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf 368#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586 369#define CONFIG_ENV_SIZE 0x2000
6d0f6bcf 370#endif /* CONFIG_SYS_RAMBOOT */
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371
372#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 373#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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374
375/*
376 * BOOTP options
377 */
378#define CONFIG_BOOTP_BOOTFILESIZE
379#define CONFIG_BOOTP_BOOTPATH
380#define CONFIG_BOOTP_GATEWAY
381#define CONFIG_BOOTP_HOSTNAME
382
383
384/*
385 * Command line configuration.
386 */
387#include <config_cmd_default.h>
388
389#define CONFIG_CMD_PING
390#define CONFIG_CMD_I2C
391#define CONFIG_CMD_ASKENV
3419eb62 392#define CONFIG_CMD_DHCP
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393
394#if defined(CONFIG_PCI)
395#define CONFIG_CMD_PCI
396#endif
397
6d0f6bcf 398#if defined(CONFIG_SYS_RAMBOOT)
bdab39d3 399#undef CONFIG_CMD_SAVEENV
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400#undef CONFIG_CMD_LOADS
401#endif
402
403#undef CONFIG_WATCHDOG /* watchdog disabled */
404
405/*
406 * Miscellaneous configurable options
407 */
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408#define CONFIG_SYS_LONGHELP /* undef to save memory */
409#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
410#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
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411
412#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 413 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
fab6f556 414#else
6d0f6bcf 415 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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416#endif
417
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418 /* Print Buffer Size */
419#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
420#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
421 /* Boot Argument Buffer Size */
422#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
423#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
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424
425/*
426 * For booting Linux, the board info and command line data
9f530d59 427 * have to be in the first 256 MB of memory, since this is
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428 * the maximum mapped by the Linux kernel during initialization.
429 */
9a986550 430#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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431
432/*
433 * Core HID Setup
434 */
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435#define CONFIG_SYS_HID0_INIT 0x000000000
436#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
437 HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf 438#define CONFIG_SYS_HID2 HID2_HBE
fab6f556 439
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440/*
441 * MMU Setup
442 */
443
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444#define CONFIG_HIGH_BATS 1 /* High BATs supported */
445
fab6f556 446/* DDR: cache cacheable */
9a986550 447#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
72cd4087 448 | BATL_PP_RW \
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449 | BATL_MEMCOHERENCE)
450#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
451 | BATU_BL_256M \
452 | BATU_VS \
453 | BATU_VP)
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454#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
455#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
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456
457/* IMMRBAR & PCI IO: cache-inhibit and guarded */
9a986550 458#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
72cd4087 459 | BATL_PP_RW \
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460 | BATL_CACHEINHIBIT \
461 | BATL_GUARDEDSTORAGE)
462#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
463 | BATU_BL_4M \
464 | BATU_VS \
465 | BATU_VP)
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466#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
467#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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468
469/* NAND: cache-inhibit and guarded */
9a986550 470#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
72cd4087 471 | BATL_PP_RW \
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472 | BATL_CACHEINHIBIT \
473 | BATL_GUARDEDSTORAGE)
474#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
475 | BATU_BL_64M \
476 | BATU_VS \
477 | BATU_VP)
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478#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
479#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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480
481/* FLASH: icache cacheable, but dcache-inhibit and guarded */
9a986550 482#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
72cd4087 483 | BATL_PP_RW \
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484 | BATL_MEMCOHERENCE)
485#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
486 | BATU_BL_32M \
487 | BATU_VS \
488 | BATU_VP)
489#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
72cd4087 490 | BATL_PP_RW \
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491 | BATL_CACHEINHIBIT \
492 | BATL_GUARDEDSTORAGE)
6d0f6bcf 493#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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494
495/* Stack in dcache: cacheable, no memory coherence */
9a986550 496#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
72cd4087 497 | BATL_PP_RW)
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498#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
499 | BATU_BL_128K \
500 | BATU_VS \
501 | BATU_VP)
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502#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
503#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
fab6f556 504
9a986550 505#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
72cd4087 506 | BATL_PP_RW \
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507 | BATL_CACHEINHIBIT \
508 | BATL_GUARDEDSTORAGE)
509#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
510 | BATU_BL_64M \
511 | BATU_VS \
512 | BATU_VP)
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513#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
514#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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515
516#ifdef CONFIG_PCI
517/* PCI MEM space: cacheable */
9a986550 518#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
72cd4087 519 | BATL_PP_RW \
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520 | BATL_MEMCOHERENCE)
521#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
522 | BATU_BL_256M \
523 | BATU_VS \
524 | BATU_VP)
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525#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
526#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
fab6f556 527/* PCI MMIO space: cache-inhibit and guarded */
9a986550 528#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
72cd4087 529 | BATL_PP_RW \
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530 | BATL_CACHEINHIBIT \
531 | BATL_GUARDEDSTORAGE)
532#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
533 | BATU_BL_256M \
534 | BATU_VS \
535 | BATU_VP)
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536#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
537#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
fab6f556 538#else /* CONFIG_PCI */
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539#define CONFIG_SYS_IBAT6L (0)
540#define CONFIG_SYS_IBAT6U (0)
541#define CONFIG_SYS_IBAT7L (0)
542#define CONFIG_SYS_IBAT7U (0)
543#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
544#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
545#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
546#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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547#endif /* CONFIG_PCI */
548
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549#if defined(CONFIG_CMD_KGDB)
550#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
551#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
552#endif
553
554/*
555 * Environment Configuration
556 */
557#define CONFIG_ENV_OVERWRITE
558
559#if defined(CONFIG_UEC_ETH)
560#define CONFIG_HAS_ETH0
561#define CONFIG_HAS_ETH1
562#define CONFIG_HAS_ETH2
563#define CONFIG_HAS_ETH3
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564#endif
565
566#define CONFIG_BAUDRATE 115200
567
568#define CONFIG_LOADADDR a00000
569#define CONFIG_HOSTNAME mpc8360erdk
b3f44c21 570#define CONFIG_BOOTFILE "uImage"
fab6f556 571
8b3637c6 572#define CONFIG_ROOTPATH "/nfsroot/"
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573
574#define CONFIG_BOOTDELAY 2 /* -1 disables auto-boot */
575#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
576
577#define CONFIG_EXTRA_ENV_SETTINGS \
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578 "netdev=eth0\0" \
579 "consoledev=ttyS0\0" \
580 "loadaddr=a00000\0" \
581 "fdtaddr=900000\0" \
582 "fdtfile=mpc836x_rdk.dtb\0" \
583 "fsfile=fs\0" \
584 "ubootfile=u-boot.bin\0" \
585 "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
586 "-(rootfs)\0" \
587 "setbootargs=setenv bootargs console=$consoledev,$baudrate " \
588 "$mtdparts panic=1\0" \
589 "adddhcpargs=setenv bootargs $bootargs ip=on\0" \
590 "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
591 "$gatewayip:$netmask:$hostname:$netdev:off " \
592 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
593 "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
594 "rootfstype=jffs2 rw\0" \
595 "tftp_get_uboot=tftp 100000 $ubootfile\0" \
596 "tftp_get_kernel=tftp $loadaddr $bootfile\0" \
597 "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
598 "tftp_get_fs=tftp c00000 $fsfile\0" \
599 "nand_erase_kernel=nand erase 0 400000\0" \
600 "nand_erase_dtb=nand erase 400000 20000\0" \
601 "nand_erase_fs=nand erase 420000 3be0000\0" \
602 "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
603 "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
604 "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
605 "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
606 "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
607 "nor_reflash=protect off ff800000 ff87ffff ; " \
608 "erase ff800000 ff87ffff ; " \
609 "cp.b 100000 ff800000 $filesize\0" \
610 "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
611 "nand_write_kernel\0" \
612 "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
613 "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
614 "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
615 "nand_reflash_fs\0" \
616 "boot_m=bootm $loadaddr - $fdtaddr\0" \
617 "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
618 "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
619 "boot_m\0" \
620 "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
621 "boot_m\0" \
622 ""
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623
624#define CONFIG_BOOTCOMMAND "run dhcpboot"
625
626#endif /* __CONFIG_H */