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Kconfig: Move CONFIG_FIT and related options to Kconfig
[people/ms/u-boot.git] / include / configs / MPC837XEMDS.h
CommitLineData
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1/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
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6 */
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
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11#define CONFIG_DISPLAY_BOARDINFO
12
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13/*
14 * High Level Configuration Options
15 */
16#define CONFIG_E300 1 /* E300 family */
2c7920af 17#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
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18#define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */
19
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20#define CONFIG_SYS_TEXT_BASE 0xFE000000
21
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22/*
23 * System Clock Setup
24 */
25#ifdef CONFIG_PCISLAVE
26#define CONFIG_83XX_PCICLK 66000000 /* in HZ */
27#else
28#define CONFIG_83XX_CLKIN 66000000 /* in Hz */
29#endif
30
31#ifndef CONFIG_SYS_CLK_FREQ
32#define CONFIG_SYS_CLK_FREQ 66000000
33#endif
34
35/*
36 * Hardware Reset Configuration Word
37 * if CLKIN is 66MHz, then
38 * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz
39 */
6d0f6bcf 40#define CONFIG_SYS_HRCW_LOW (\
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41 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
42 HRCWL_DDR_TO_SCB_CLK_1X1 |\
43 HRCWL_SVCOD_DIV_2 |\
44 HRCWL_CSB_TO_CLKIN_6X1 |\
45 HRCWL_CORE_TO_CSB_1_5X1)
46
47#ifdef CONFIG_PCISLAVE
6d0f6bcf 48#define CONFIG_SYS_HRCW_HIGH (\
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49 HRCWH_PCI_AGENT |\
50 HRCWH_PCI1_ARBITER_DISABLE |\
51 HRCWH_CORE_ENABLE |\
52 HRCWH_FROM_0XFFF00100 |\
53 HRCWH_BOOTSEQ_DISABLE |\
54 HRCWH_SW_WATCHDOG_DISABLE |\
55 HRCWH_ROM_LOC_LOCAL_16BIT |\
56 HRCWH_RL_EXT_LEGACY |\
57 HRCWH_TSEC1M_IN_RGMII |\
58 HRCWH_TSEC2M_IN_RGMII |\
59 HRCWH_BIG_ENDIAN |\
60 HRCWH_LDP_CLEAR)
61#else
6d0f6bcf 62#define CONFIG_SYS_HRCW_HIGH (\
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63 HRCWH_PCI_HOST |\
64 HRCWH_PCI1_ARBITER_ENABLE |\
65 HRCWH_CORE_ENABLE |\
66 HRCWH_FROM_0X00000100 |\
67 HRCWH_BOOTSEQ_DISABLE |\
68 HRCWH_SW_WATCHDOG_DISABLE |\
69 HRCWH_ROM_LOC_LOCAL_16BIT |\
70 HRCWH_RL_EXT_LEGACY |\
71 HRCWH_TSEC1M_IN_RGMII |\
72 HRCWH_TSEC2M_IN_RGMII |\
73 HRCWH_BIG_ENDIAN |\
74 HRCWH_LDP_CLEAR)
75#endif
76
bd4458cb 77/* Arbiter Configuration Register */
6d0f6bcf 78#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */
8d85808f 79#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */
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80
81/* System Priority Control Register */
8d85808f 82#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */
bd4458cb 83
19580e66 84/*
bd4458cb 85 * IP blocks clock configuration
19580e66 86 */
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87#define CONFIG_SYS_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */
88#define CONFIG_SYS_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */
8d85808f 89#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* CSB:SATA[0:3] = 2:1 */
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90
91/*
92 * System IO Config
93 */
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94#define CONFIG_SYS_SICRH 0x00000000
95#define CONFIG_SYS_SICRL 0x00000000
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96
97/*
98 * Output Buffer Impedance
99 */
6d0f6bcf 100#define CONFIG_SYS_OBIR 0x31100000
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101
102#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
103#define CONFIG_BOARD_EARLY_INIT_R
c78c6783 104#define CONFIG_HWCONFIG
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105
106/*
107 * IMMR new address
108 */
6d0f6bcf 109#define CONFIG_SYS_IMMR 0xE0000000
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110
111/*
112 * DDR Setup
113 */
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114#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
115#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
116#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
117#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
118#define CONFIG_SYS_83XX_DDR_USES_CS0
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119#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
120 | DDRCDR_ODT \
121 | DDRCDR_Q_DRN)
122 /* 0x80080001 */ /* ODT 150ohm on SoC */
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123
124#undef CONFIG_DDR_ECC /* support DDR ECC function */
125#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
126
127#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
128#define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
129
130#if defined(CONFIG_SPD_EEPROM)
131#define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */
132#else
133/*
134 * Manually set up DDR parameters
7e74d63d 135 * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM
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136 * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5
137 */
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138#define CONFIG_SYS_DDR_SIZE 512 /* MB */
139#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
8d85808f 140#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
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141 | CSCONFIG_ODT_RD_NEVER /* ODT_RD to none */ \
142 | CSCONFIG_ODT_WR_ONLY_CURRENT /* ODT_WR to CSn */ \
143 | CSCONFIG_ROW_BIT_14 \
144 | CSCONFIG_COL_BIT_10)
145 /* 0x80010202 */
6d0f6bcf 146#define CONFIG_SYS_DDR_TIMING_3 0x00000000
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147#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
148 | (0 << TIMING_CFG0_WRT_SHIFT) \
149 | (0 << TIMING_CFG0_RRT_SHIFT) \
150 | (0 << TIMING_CFG0_WWT_SHIFT) \
151 | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
152 | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
153 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
154 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
19580e66 155 /* 0x00620802 */
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156#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
157 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
158 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
159 | (5 << TIMING_CFG1_CASLAT_SHIFT) \
160 | (13 << TIMING_CFG1_REFREC_SHIFT) \
161 | (3 << TIMING_CFG1_WRREC_SHIFT) \
162 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
163 | (2 << TIMING_CFG1_WRTORD_SHIFT))
19580e66 164 /* 0x3935d322 */
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165#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
166 | (6 << TIMING_CFG2_CPO_SHIFT) \
167 | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
168 | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
169 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
170 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
171 | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
7e74d63d 172 /* 0x131088c8 */
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173#define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
174 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
19580e66 175 /* 0x03E00100 */
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176#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
177#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
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178#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
179 | (0x1432 << SDRAM_MODE_SD_SHIFT))
7e74d63d 180 /* ODT 150ohm CL=3, AL=1 on SDRAM */
8d85808f 181#define CONFIG_SYS_DDR_MODE2 0x00000000
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182#endif
183
184/*
185 * Memory test
186 */
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187#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
188#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
189#define CONFIG_SYS_MEMTEST_END 0x00140000
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190
191/*
192 * The reserved memory
193 */
14d0a02a 194#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
19580e66 195
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196#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
197#define CONFIG_SYS_RAMBOOT
19580e66 198#else
6d0f6bcf 199#undef CONFIG_SYS_RAMBOOT
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200#endif
201
6d0f6bcf 202/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
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203#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
204#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
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205
206/*
207 * Initial RAM Base Address Setup
208 */
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209#define CONFIG_SYS_INIT_RAM_LOCK 1
210#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
553f0982 211#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
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212#define CONFIG_SYS_GBL_DATA_OFFSET \
213 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
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214
215/*
216 * Local Bus Configuration & Clock Setup
217 */
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218#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
219#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
6d0f6bcf 220#define CONFIG_SYS_LBC_LBCR 0x00000000
0914f483 221#define CONFIG_FSL_ELBC 1
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222
223/*
224 * FLASH on the Local Bus
225 */
8d85808f 226#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
00b1883a 227#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
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228#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
229#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
230#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
19580e66 231
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232 /* Window base at flash base */
233#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
7d6a0982 234#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
19580e66 235
8d85808f 236#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
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237 | BR_PS_16 /* 16 bit port */ \
238 | BR_MS_GPCM /* MSEL = GPCM */ \
239 | BR_V) /* valid */
240#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
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241 | OR_UPM_XAM \
242 | OR_GPCM_CSNT \
f9023afb 243 | OR_GPCM_ACS_DIV2 \
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244 | OR_GPCM_XACS \
245 | OR_GPCM_SCY_15 \
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246 | OR_GPCM_TRLX_SET \
247 | OR_GPCM_EHTR_SET \
8d85808f 248 | OR_GPCM_EAD)
ded08317 249 /* 0xFE000FF7 */
19580e66 250
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251#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
252#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
19580e66 253
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254#undef CONFIG_SYS_FLASH_CHECKSUM
255#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
256#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
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257
258/*
259 * BCSR on the Local Bus
260 */
6d0f6bcf 261#define CONFIG_SYS_BCSR 0xF8000000
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262 /* Access window base at BCSR base */
263#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
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264#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
265
266#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR \
267 | BR_PS_8 \
268 | BR_MS_GPCM \
269 | BR_V)
270 /* 0xF8000801 */
271#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \
272 | OR_GPCM_XAM \
273 | OR_GPCM_CSNT \
274 | OR_GPCM_XACS \
275 | OR_GPCM_SCY_15 \
276 | OR_GPCM_TRLX_SET \
277 | OR_GPCM_EHTR_SET \
278 | OR_GPCM_EAD)
279 /* 0xFFFFE9F7 */
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280
281/*
282 * NAND Flash on the Local Bus
283 */
b3379f3f 284#define CONFIG_CMD_NAND 1
b3379f3f 285#define CONFIG_SYS_MAX_NAND_DEVICE 1
8d85808f 286#define CONFIG_NAND_FSL_ELBC 1
b3379f3f 287
7d6a0982 288#define CONFIG_SYS_NAND_BASE 0xE0600000
8d85808f 289#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
7d6a0982 290 | BR_DECC_CHK_GEN /* Use HW ECC */ \
8d85808f 291 | BR_PS_8 /* 8 bit port */ \
19580e66 292 | BR_MS_FCM /* MSEL = FCM */ \
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293 | BR_V) /* valid */
294#define CONFIG_SYS_OR3_PRELIM (OR_AM_32KB \
b3379f3f 295 | OR_FCM_BCTLD \
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296 | OR_FCM_CST \
297 | OR_FCM_CHT \
298 | OR_FCM_SCY_1 \
b3379f3f 299 | OR_FCM_RST \
19580e66 300 | OR_FCM_TRLX \
8d85808f 301 | OR_FCM_EHTR)
b3379f3f 302 /* 0xFFFF919E */
19580e66 303
6d0f6bcf 304#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
7d6a0982 305#define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
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306
307/*
308 * Serial Port
309 */
310#define CONFIG_CONS_INDEX 1
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311#define CONFIG_SYS_NS16550_SERIAL
312#define CONFIG_SYS_NS16550_REG_SIZE 1
313#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
19580e66 314
6d0f6bcf 315#define CONFIG_SYS_BAUDRATE_TABLE \
8d85808f 316 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
19580e66 317
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318#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
319#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
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320
321/* Use the HUSH parser */
6d0f6bcf 322#define CONFIG_SYS_HUSH_PARSER
19580e66 323
19580e66 324/* I2C */
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325#define CONFIG_SYS_I2C
326#define CONFIG_SYS_I2C_FSL
327#define CONFIG_SYS_FSL_I2C_SPEED 400000
328#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
329#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
330#define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} }
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331
332/*
333 * Config on-board RTC
334 */
335#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
6d0f6bcf 336#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
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337
338/*
339 * General PCI
340 * Addresses are mapped 1-1.
341 */
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342#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
343#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
344#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
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345#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
346#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
347#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
348#define CONFIG_SYS_PCI_IO_BASE 0x00000000
349#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
350#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
19580e66 351
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352#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
353#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
354#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
19580e66 355
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356#define CONFIG_SYS_PCIE1_BASE 0xA0000000
357#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
358#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
359#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
360#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
361#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
362#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
363#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
364#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
365
366#define CONFIG_SYS_PCIE2_BASE 0xC0000000
367#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
368#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
369#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
370#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
371#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
372#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
373#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
374#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
375
19580e66 376#ifdef CONFIG_PCI
842033e6 377#define CONFIG_PCI_INDIRECT_BRIDGE
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378#ifndef __ASSEMBLY__
379extern int board_pci_host_broken(void);
380#endif
be9b56df 381#define CONFIG_PCIE
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382#define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */
383
3bf1be3c 384#define CONFIG_HAS_FSL_DR_USB 1 /* fixup device tree for the DR USB */
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385#define CONFIG_CMD_USB
386#define CONFIG_USB_STORAGE
387#define CONFIG_USB_EHCI
388#define CONFIG_USB_EHCI_FSL
389#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
3bf1be3c 390
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391#define CONFIG_PCI_PNP /* do pci plug-and-play */
392
393#undef CONFIG_EEPRO100
394#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf 395#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
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396#endif /* CONFIG_PCI */
397
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398/*
399 * TSEC
400 */
401#define CONFIG_TSEC_ENET /* TSEC ethernet support */
6d0f6bcf 402#define CONFIG_SYS_TSEC1_OFFSET 0x24000
8d85808f 403#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
6d0f6bcf 404#define CONFIG_SYS_TSEC2_OFFSET 0x25000
8d85808f 405#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET)
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406
407/*
408 * TSEC ethernet configuration
409 */
410#define CONFIG_MII 1 /* MII PHY management */
411#define CONFIG_TSEC1 1
412#define CONFIG_TSEC1_NAME "eTSEC0"
413#define CONFIG_TSEC2 1
414#define CONFIG_TSEC2_NAME "eTSEC1"
415#define TSEC1_PHY_ADDR 2
416#define TSEC2_PHY_ADDR 3
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417#define TSEC1_PHY_ADDR_SGMII 8
418#define TSEC2_PHY_ADDR_SGMII 4
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419#define TSEC1_PHYIDX 0
420#define TSEC2_PHYIDX 0
421#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
422#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
423
424/* Options are: TSEC[0-1] */
425#define CONFIG_ETHPRIME "eTSEC1"
426
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427/* SERDES */
428#define CONFIG_FSL_SERDES
429#define CONFIG_FSL_SERDES1 0xe3000
430#define CONFIG_FSL_SERDES2 0xe3100
431
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432/*
433 * SATA
434 */
435#define CONFIG_LIBATA
436#define CONFIG_FSL_SATA
437
6d0f6bcf 438#define CONFIG_SYS_SATA_MAX_DEVICE 2
2eeb3e4f 439#define CONFIG_SATA1
6d0f6bcf 440#define CONFIG_SYS_SATA1_OFFSET 0x18000
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441#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
442#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
2eeb3e4f 443#define CONFIG_SATA2
6d0f6bcf 444#define CONFIG_SYS_SATA2_OFFSET 0x19000
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445#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
446#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
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447
448#ifdef CONFIG_FSL_SATA
449#define CONFIG_LBA48
450#define CONFIG_CMD_SATA
451#define CONFIG_DOS_PARTITION
452#define CONFIG_CMD_EXT2
453#endif
454
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455/*
456 * Environment
457 */
6d0f6bcf 458#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0 459 #define CONFIG_ENV_IS_IN_FLASH 1
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460 #define CONFIG_ENV_ADDR \
461 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
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462 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
463 #define CONFIG_ENV_SIZE 0x2000
19580e66 464#else
8d85808f 465 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725 466 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf 467 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586 468 #define CONFIG_ENV_SIZE 0x2000
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469#endif
470
471#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf 472#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
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473
474/*
475 * BOOTP options
476 */
477#define CONFIG_BOOTP_BOOTFILESIZE
478#define CONFIG_BOOTP_BOOTPATH
479#define CONFIG_BOOTP_GATEWAY
480#define CONFIG_BOOTP_HOSTNAME
481
482
483/*
484 * Command line configuration.
485 */
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486#define CONFIG_CMD_PING
487#define CONFIG_CMD_I2C
488#define CONFIG_CMD_MII
489#define CONFIG_CMD_DATE
490
491#if defined(CONFIG_PCI)
492 #define CONFIG_CMD_PCI
493#endif
494
19580e66 495#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
a059e90e 496#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
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497
498#undef CONFIG_WATCHDOG /* watchdog disabled */
499
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500#define CONFIG_MMC 1
501
502#ifdef CONFIG_MMC
503#define CONFIG_FSL_ESDHC
a6da8b81 504#define CONFIG_FSL_ESDHC_PIN_MUX
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505#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
506#define CONFIG_CMD_MMC
507#define CONFIG_GENERIC_MMC
508#define CONFIG_CMD_EXT2
509#define CONFIG_CMD_FAT
510#define CONFIG_DOS_PARTITION
511#endif
512
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513/*
514 * Miscellaneous configurable options
515 */
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516#define CONFIG_SYS_LONGHELP /* undef to save memory */
517#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
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518
519#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 520 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
19580e66 521#else
6d0f6bcf 522 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
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523#endif
524
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525 /* Print Buffer Size */
526#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
527#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
528 /* Boot Argument Buffer Size */
529#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
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530
531/*
532 * For booting Linux, the board info and command line data
9f530d59 533 * have to be in the first 256 MB of memory, since this is
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534 * the maximum mapped by the Linux kernel during initialization.
535 */
8d85808f 536#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
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537
538/*
539 * Core HID Setup
540 */
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541#define CONFIG_SYS_HID0_INIT 0x000000000
542#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
543 HID0_ENABLE_INSTRUCTION_CACHE)
6d0f6bcf 544#define CONFIG_SYS_HID2 HID2_HBE
19580e66 545
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546/*
547 * MMU Setup
548 */
31d82672 549#define CONFIG_HIGH_BATS 1 /* High BATs supported */
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550
551/* DDR: cache cacheable */
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552#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
553#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
19580e66 554
8d85808f 555#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
72cd4087 556 | BATL_PP_RW \
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557 | BATL_MEMCOHERENCE)
558#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
559 | BATU_BL_256M \
560 | BATU_VS \
561 | BATU_VP)
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562#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
563#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
19580e66 564
8d85808f 565#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
72cd4087 566 | BATL_PP_RW \
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567 | BATL_MEMCOHERENCE)
568#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
569 | BATU_BL_256M \
570 | BATU_VS \
571 | BATU_VP)
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572#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
573#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
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574
575/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
8d85808f 576#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
72cd4087 577 | BATL_PP_RW \
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578 | BATL_CACHEINHIBIT \
579 | BATL_GUARDEDSTORAGE)
580#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
581 | BATU_BL_8M \
582 | BATU_VS \
583 | BATU_VP)
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584#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
585#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
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586
587/* BCSR: cache-inhibit and guarded */
8d85808f 588#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
72cd4087 589 | BATL_PP_RW \
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590 | BATL_CACHEINHIBIT \
591 | BATL_GUARDEDSTORAGE)
592#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
593 | BATU_BL_128K \
594 | BATU_VS \
595 | BATU_VP)
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596#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
597#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
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598
599/* FLASH: icache cacheable, but dcache-inhibit and guarded */
8d85808f 600#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
72cd4087 601 | BATL_PP_RW \
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602 | BATL_MEMCOHERENCE)
603#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
604 | BATU_BL_32M \
605 | BATU_VS \
606 | BATU_VP)
607#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
72cd4087 608 | BATL_PP_RW \
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609 | BATL_CACHEINHIBIT \
610 | BATL_GUARDEDSTORAGE)
6d0f6bcf 611#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
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612
613/* Stack in dcache: cacheable, no memory coherence */
72cd4087 614#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
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615#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
616 | BATU_BL_128K \
617 | BATU_VS \
618 | BATU_VP)
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619#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
620#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
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621
622#ifdef CONFIG_PCI
623/* PCI MEM space: cacheable */
8d85808f 624#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
72cd4087 625 | BATL_PP_RW \
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626 | BATL_MEMCOHERENCE)
627#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
628 | BATU_BL_256M \
629 | BATU_VS \
630 | BATU_VP)
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631#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
632#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
19580e66 633/* PCI MMIO space: cache-inhibit and guarded */
8d85808f 634#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
72cd4087 635 | BATL_PP_RW \
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636 | BATL_CACHEINHIBIT \
637 | BATL_GUARDEDSTORAGE)
638#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
639 | BATU_BL_256M \
640 | BATU_VS \
641 | BATU_VP)
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642#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
643#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
19580e66 644#else
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645#define CONFIG_SYS_IBAT6L (0)
646#define CONFIG_SYS_IBAT6U (0)
647#define CONFIG_SYS_IBAT7L (0)
648#define CONFIG_SYS_IBAT7U (0)
649#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
650#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
651#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
652#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
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653#endif
654
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655#if defined(CONFIG_CMD_KGDB)
656#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
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657#endif
658
659/*
660 * Environment Configuration
661 */
662
663#define CONFIG_ENV_OVERWRITE
664
665#if defined(CONFIG_TSEC_ENET)
666#define CONFIG_HAS_ETH0
19580e66 667#define CONFIG_HAS_ETH1
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668#endif
669
670#define CONFIG_BAUDRATE 115200
671
79f516bc 672#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
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673
674#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
675#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
676
677#define CONFIG_EXTRA_ENV_SETTINGS \
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678 "netdev=eth0\0" \
679 "consoledev=ttyS0\0" \
680 "ramdiskaddr=1000000\0" \
681 "ramdiskfile=ramfs.83xx\0" \
682 "fdtaddr=780000\0" \
683 "fdtfile=mpc8379_mds.dtb\0" \
684 ""
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685
686#define CONFIG_NFSBOOTCOMMAND \
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687 "setenv bootargs root=/dev/nfs rw " \
688 "nfsroot=$serverip:$rootpath " \
689 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
690 "$netdev:off " \
691 "console=$consoledev,$baudrate $othbootargs;" \
692 "tftp $loadaddr $bootfile;" \
693 "tftp $fdtaddr $fdtfile;" \
694 "bootm $loadaddr - $fdtaddr"
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695
696#define CONFIG_RAMBOOTCOMMAND \
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697 "setenv bootargs root=/dev/ram rw " \
698 "console=$consoledev,$baudrate $othbootargs;" \
699 "tftp $ramdiskaddr $ramdiskfile;" \
700 "tftp $loadaddr $bootfile;" \
701 "tftp $fdtaddr $fdtfile;" \
702 "bootm $loadaddr $ramdiskaddr $fdtaddr"
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703
704
705#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
706
707#endif /* __CONFIG_H */