projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 19580e66 DL |
1 | /* |
| 2 | * Copyright (C) 2007 Freescale Semiconductor, Inc. | |
| 3 | * Dave Liu <daveliu@freescale.com> | |
| 4 | * | |
| 5 | * This program is free software; you can redistribute it and/or | |
| 6 | * modify it under the terms of the GNU General Public License as | |
| 7 | * published by the Free Software Foundation; either version 2 of | |
| 8 | * the License, or (at your option) any later version. | |
| 9 | * | |
| 10 | * This program is distributed in the hope that it will be useful, | |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 13 | * GNU General Public License for more details. | |
| 14 | * | |
| 15 | * You should have received a copy of the GNU General Public License | |
| 16 | * along with this program; if not, write to the Free Software | |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 18 | * MA 02111-1307 USA | |
| 19 | */ | |
| 20 | ||
| 21 | #ifndef __CONFIG_H | |
| 22 | #define __CONFIG_H | |
| 23 | ||
| 24 | #undef DEBUG | |
| 25 | ||
| 26 | /* | |
| 27 | * High Level Configuration Options | |
| 28 | */ | |
| 29 | #define CONFIG_E300 1 /* E300 family */ | |
| 30 | #define CONFIG_MPC83XX 1 /* MPC83XX family */ | |
| 31 | #define CONFIG_MPC837X 1 /* MPC837X CPU specific */ | |
| 32 | #define CONFIG_MPC837XEMDS 1 /* MPC837XEMDS board specific */ | |
| 33 | ||
| 34 | /* | |
| 35 | * System Clock Setup | |
| 36 | */ | |
| 37 | #ifdef CONFIG_PCISLAVE | |
| 38 | #define CONFIG_83XX_PCICLK 66000000 /* in HZ */ | |
| 39 | #else | |
| 40 | #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ | |
| 41 | #endif | |
| 42 | ||
| 43 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 44 | #define CONFIG_SYS_CLK_FREQ 66000000 | |
| 45 | #endif | |
| 46 | ||
| 47 | /* | |
| 48 | * Hardware Reset Configuration Word | |
| 49 | * if CLKIN is 66MHz, then | |
| 50 | * CSB = 396MHz, CORE = 594MHz, DDRC = 396MHz, LBC = 396MHz | |
| 51 | */ | |
| 52 | #define CFG_HRCW_LOW (\ | |
| 53 | HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ | |
| 54 | HRCWL_DDR_TO_SCB_CLK_1X1 |\ | |
| 55 | HRCWL_SVCOD_DIV_2 |\ | |
| 56 | HRCWL_CSB_TO_CLKIN_6X1 |\ | |
| 57 | HRCWL_CORE_TO_CSB_1_5X1) | |
| 58 | ||
| 59 | #ifdef CONFIG_PCISLAVE | |
| 60 | #define CFG_HRCW_HIGH (\ | |
| 61 | HRCWH_PCI_AGENT |\ | |
| 62 | HRCWH_PCI1_ARBITER_DISABLE |\ | |
| 63 | HRCWH_CORE_ENABLE |\ | |
| 64 | HRCWH_FROM_0XFFF00100 |\ | |
| 65 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 66 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 67 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 68 | HRCWH_RL_EXT_LEGACY |\ | |
| 69 | HRCWH_TSEC1M_IN_RGMII |\ | |
| 70 | HRCWH_TSEC2M_IN_RGMII |\ | |
| 71 | HRCWH_BIG_ENDIAN |\ | |
| 72 | HRCWH_LDP_CLEAR) | |
| 73 | #else | |
| 74 | #define CFG_HRCW_HIGH (\ | |
| 75 | HRCWH_PCI_HOST |\ | |
| 76 | HRCWH_PCI1_ARBITER_ENABLE |\ | |
| 77 | HRCWH_CORE_ENABLE |\ | |
| 78 | HRCWH_FROM_0X00000100 |\ | |
| 79 | HRCWH_BOOTSEQ_DISABLE |\ | |
| 80 | HRCWH_SW_WATCHDOG_DISABLE |\ | |
| 81 | HRCWH_ROM_LOC_LOCAL_16BIT |\ | |
| 82 | HRCWH_RL_EXT_LEGACY |\ | |
| 83 | HRCWH_TSEC1M_IN_RGMII |\ | |
| 84 | HRCWH_TSEC2M_IN_RGMII |\ | |
| 85 | HRCWH_BIG_ENDIAN |\ | |
| 86 | HRCWH_LDP_CLEAR) | |
| 87 | #endif | |
| 88 | ||
| 89 | /* | |
| 90 | * eTSEC Clock Config | |
| 91 | */ | |
| 92 | #define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ | |
| 93 | #define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ | |
| 94 | ||
| 95 | /* | |
| 96 | * System IO Config | |
| 97 | */ | |
| 98 | #define CFG_SICRH 0x00000000 | |
| 99 | #define CFG_SICRL 0x00000000 | |
| 100 | ||
| 101 | /* | |
| 102 | * Output Buffer Impedance | |
| 103 | */ | |
| 104 | #define CFG_OBIR 0x31100000 | |
| 105 | ||
| 106 | #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ | |
| 107 | #define CONFIG_BOARD_EARLY_INIT_R | |
| 108 | ||
| 109 | /* | |
| 110 | * IMMR new address | |
| 111 | */ | |
| 112 | #define CFG_IMMR 0xE0000000 | |
| 113 | ||
| 114 | /* | |
| 115 | * DDR Setup | |
| 116 | */ | |
| 117 | #define CFG_DDR_BASE 0x00000000 /* DDR is system memory */ | |
| 118 | #define CFG_SDRAM_BASE CFG_DDR_BASE | |
| 119 | #define CFG_DDR_SDRAM_BASE CFG_DDR_BASE | |
| 120 | #define CFG_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
| 121 | #define CFG_83XX_DDR_USES_CS0 | |
| 122 | #define CFG_DDRCDR_VALUE 0x80080001 /* ODT 150ohm on SoC */ | |
| 123 | ||
| 124 | #undef CONFIG_DDR_ECC /* support DDR ECC function */ | |
| 125 | #undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ | |
| 126 | ||
| 127 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 128 | #define CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ | |
| 129 | ||
| 130 | #if defined(CONFIG_SPD_EEPROM) | |
| 131 | #define SPD_EEPROM_ADDRESS 0x51 /* I2C address of DDR SODIMM SPD */ | |
| 132 | #else | |
| 133 | /* | |
| 134 | * Manually set up DDR parameters | |
| 7e74d63d | 135 | * WHITE ELECTRONIC DESIGNS - W3HG64M72EEU403PD4 SO-DIMM |
| 19580e66 DL |
136 | * consist of nine chips from SAMSUNG K4T51083QE-ZC(L)D5 |
| 137 | */ | |
| 138 | #define CFG_DDR_SIZE 512 /* MB */ | |
| 139 | #define CFG_DDR_CS0_BNDS 0x0000001f | |
| 140 | #define CFG_DDR_CS0_CONFIG ( CSCONFIG_EN \ | |
| 141 | | 0x00010000 /* ODT_WR to CSn */ \ | |
| 142 | | CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) | |
| 143 | /* 0x80010202 */ | |
| 144 | #define CFG_DDR_TIMING_3 0x00000000 | |
| 145 | #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ | |
| 146 | | ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | |
| 147 | | ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | |
| 148 | | ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | |
| 149 | | ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | |
| 150 | | ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | |
| 151 | | ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | |
| 152 | | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | |
| 153 | /* 0x00620802 */ | |
| 154 | #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ | |
| 155 | | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | |
| 156 | | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | |
| 157 | | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | |
| 158 | | (13 << TIMING_CFG1_REFREC_SHIFT ) \ | |
| 159 | | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ | |
| 160 | | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | |
| 161 | | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | |
| 162 | /* 0x3935d322 */ | |
| 7e74d63d | 163 | #define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ |
| 19580e66 DL |
164 | | ( 6 << TIMING_CFG2_CPO_SHIFT ) \ |
| 165 | | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | |
| 166 | | ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | |
| 167 | | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | |
| 168 | | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | |
| 169 | | ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | |
| 7e74d63d | 170 | /* 0x131088c8 */ |
| 19580e66 DL |
171 | #define CFG_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ |
| 172 | | ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) | |
| 173 | /* 0x03E00100 */ | |
| 174 | #define CFG_DDR_SDRAM_CFG 0x43000000 | |
| 175 | #define CFG_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ | |
| 7e74d63d | 176 | #define CFG_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ |
| 19580e66 | 177 | | ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) |
| 7e74d63d | 178 | /* ODT 150ohm CL=3, AL=1 on SDRAM */ |
| 19580e66 DL |
179 | #define CFG_DDR_MODE2 0x00000000 |
| 180 | #endif | |
| 181 | ||
| 182 | /* | |
| 183 | * Memory test | |
| 184 | */ | |
| 185 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
| 186 | #define CFG_MEMTEST_START 0x00040000 /* memtest region */ | |
| 187 | #define CFG_MEMTEST_END 0x00140000 | |
| 188 | ||
| 189 | /* | |
| 190 | * The reserved memory | |
| 191 | */ | |
| 192 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 193 | ||
| 194 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
| 195 | #define CFG_RAMBOOT | |
| 196 | #else | |
| 197 | #undef CFG_RAMBOOT | |
| 198 | #endif | |
| 199 | ||
| 921d4b19 | 200 | /* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ |
| 19580e66 DL |
201 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 202 | #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
| 203 | ||
| 204 | /* | |
| 205 | * Initial RAM Base Address Setup | |
| 206 | */ | |
| 207 | #define CFG_INIT_RAM_LOCK 1 | |
| 208 | #define CFG_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ | |
| 209 | #define CFG_INIT_RAM_END 0x1000 /* End of used area in RAM */ | |
| 210 | #define CFG_GBL_DATA_SIZE 0x100 /* num bytes initial data */ | |
| 211 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 212 | ||
| 213 | /* | |
| 214 | * Local Bus Configuration & Clock Setup | |
| 215 | */ | |
| 216 | #define CFG_LCRR (LCRR_DBYP | LCRR_CLKDIV_8) | |
| 217 | #define CFG_LBC_LBCR 0x00000000 | |
| 218 | ||
| 219 | /* | |
| 220 | * FLASH on the Local Bus | |
| 221 | */ | |
| 222 | #define CFG_FLASH_CFI /* use the Common Flash Interface */ | |
| 223 | #define CFG_FLASH_CFI_DRIVER /* use the CFI driver */ | |
| 224 | #define CFG_FLASH_BASE 0xFE000000 /* FLASH base address */ | |
| 225 | #define CFG_FLASH_SIZE 32 /* max FLASH size is 32M */ | |
| 226 | ||
| 227 | #define CFG_LBLAWBAR0_PRELIM CFG_FLASH_BASE /* Window base at flash base */ | |
| 228 | #define CFG_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ | |
| 229 | ||
| 230 | #define CFG_BR0_PRELIM (CFG_FLASH_BASE | /* Flash Base address */ \ | |
| 231 | (2 << BR_PS_SHIFT) | /* 16 bit port size */ \ | |
| 232 | BR_V) /* valid */ | |
| 233 | #define CFG_OR0_PRELIM ((~(CFG_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ | |
| 234 | OR_GPCM_CSNT | OR_GPCM_ACS_0b11 | OR_GPCM_XACS | OR_GPCM_SCY_15 | \ | |
| 235 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD) | |
| 236 | ||
| 237 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
| 238 | #define CFG_MAX_FLASH_SECT 256 /* max sectors per device */ | |
| 239 | ||
| 240 | #undef CFG_FLASH_CHECKSUM | |
| 241 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 242 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 243 | ||
| 244 | /* | |
| 245 | * BCSR on the Local Bus | |
| 246 | */ | |
| 247 | #define CFG_BCSR 0xF8000000 | |
| 248 | #define CFG_LBLAWBAR1_PRELIM CFG_BCSR /* Access window base at BCSR base */ | |
| 249 | #define CFG_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ | |
| 250 | ||
| 251 | #define CFG_BR1_PRELIM (CFG_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ | |
| 252 | #define CFG_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ | |
| 253 | ||
| 254 | /* | |
| 255 | * NAND Flash on the Local Bus | |
| 256 | */ | |
| 257 | #define CFG_NAND_BASE 0xE0600000 /* 0xE0600000 */ | |
| 258 | #define CFG_BR3_PRELIM ( CFG_NAND_BASE \ | |
| 259 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 260 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 261 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 262 | | BR_V ) /* valid */ | |
| 263 | #define CFG_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ | |
| 264 | | OR_FCM_CSCT \ | |
| 265 | | OR_FCM_CST \ | |
| 266 | | OR_FCM_CHT \ | |
| 267 | | OR_FCM_SCY_1 \ | |
| 268 | | OR_FCM_TRLX \ | |
| 269 | | OR_FCM_EHTR ) | |
| 270 | /* 0xFFFF8396 */ | |
| 271 | ||
| 272 | #define CFG_LBLAWBAR3_PRELIM CFG_NAND_BASE | |
| 273 | #define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ | |
| 274 | ||
| 275 | /* | |
| 276 | * Serial Port | |
| 277 | */ | |
| 278 | #define CONFIG_CONS_INDEX 1 | |
| 279 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 280 | #define CFG_NS16550 | |
| 281 | #define CFG_NS16550_SERIAL | |
| 282 | #define CFG_NS16550_REG_SIZE 1 | |
| 283 | #define CFG_NS16550_CLK get_bus_freq(0) | |
| 284 | ||
| 285 | #define CFG_BAUDRATE_TABLE \ | |
| 286 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
| 287 | ||
| 288 | #define CFG_NS16550_COM1 (CFG_IMMR+0x4500) | |
| 289 | #define CFG_NS16550_COM2 (CFG_IMMR+0x4600) | |
| 290 | ||
| 291 | /* Use the HUSH parser */ | |
| 292 | #define CFG_HUSH_PARSER | |
| 293 | #ifdef CFG_HUSH_PARSER | |
| 294 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 295 | #endif | |
| 296 | ||
| 297 | /* Pass open firmware flat tree */ | |
| 298 | #define CONFIG_OF_LIBFDT 1 | |
| 299 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 5b8bc606 | 300 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 |
| 19580e66 DL |
301 | |
| 302 | /* I2C */ | |
| 303 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 304 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 305 | #define CONFIG_FSL_I2C | |
| 306 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 307 | #define CFG_I2C_SLAVE 0x7F | |
| 308 | #define CFG_I2C_NOPROBES {0x51} /* Don't probe these addrs */ | |
| 309 | #define CFG_I2C_OFFSET 0x3000 | |
| 310 | #define CFG_I2C2_OFFSET 0x3100 | |
| 311 | ||
| 312 | /* | |
| 313 | * Config on-board RTC | |
| 314 | */ | |
| 315 | #define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */ | |
| 316 | #define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */ | |
| 317 | ||
| 318 | /* | |
| 319 | * General PCI | |
| 320 | * Addresses are mapped 1-1. | |
| 321 | */ | |
| 322 | #define CFG_PCI_MEM_BASE 0x80000000 | |
| 323 | #define CFG_PCI_MEM_PHYS CFG_PCI_MEM_BASE | |
| 324 | #define CFG_PCI_MEM_SIZE 0x10000000 /* 256M */ | |
| 325 | #define CFG_PCI_MMIO_BASE 0x90000000 | |
| 326 | #define CFG_PCI_MMIO_PHYS CFG_PCI_MMIO_BASE | |
| 327 | #define CFG_PCI_MMIO_SIZE 0x10000000 /* 256M */ | |
| 328 | #define CFG_PCI_IO_BASE 0xE0300000 | |
| 329 | #define CFG_PCI_IO_PHYS 0xE0300000 | |
| 330 | #define CFG_PCI_IO_SIZE 0x100000 /* 1M */ | |
| 331 | ||
| 332 | #define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE | |
| 333 | #define CFG_PCI_SLV_MEM_BUS 0x00000000 | |
| 334 | #define CFG_PCI_SLV_MEM_SIZE 0x80000000 | |
| 335 | ||
| 336 | #ifdef CONFIG_PCI | |
| 337 | #define CONFIG_83XX_GENERIC_PCI 1 /* Use generic PCI setup */ | |
| 338 | #define CONFIG_PQ_MDS_PIB 1 /* PQ MDS Platform IO Board */ | |
| 339 | ||
| 340 | #define CONFIG_NET_MULTI | |
| 341 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 342 | ||
| 343 | #undef CONFIG_EEPRO100 | |
| 344 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 345 | #define CFG_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ | |
| 346 | #endif /* CONFIG_PCI */ | |
| 347 | ||
| 348 | #ifndef CONFIG_NET_MULTI | |
| 349 | #define CONFIG_NET_MULTI 1 | |
| 350 | #endif | |
| 351 | ||
| 352 | /* | |
| 353 | * TSEC | |
| 354 | */ | |
| 355 | #define CONFIG_TSEC_ENET /* TSEC ethernet support */ | |
| 356 | #define CFG_TSEC1_OFFSET 0x24000 | |
| 357 | #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) | |
| 358 | #define CFG_TSEC2_OFFSET 0x25000 | |
| 359 | #define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) | |
| 360 | ||
| 361 | /* | |
| 362 | * TSEC ethernet configuration | |
| 363 | */ | |
| 364 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 365 | #define CONFIG_TSEC1 1 | |
| 366 | #define CONFIG_TSEC1_NAME "eTSEC0" | |
| 367 | #define CONFIG_TSEC2 1 | |
| 368 | #define CONFIG_TSEC2_NAME "eTSEC1" | |
| 369 | #define TSEC1_PHY_ADDR 2 | |
| 370 | #define TSEC2_PHY_ADDR 3 | |
| 371 | #define TSEC1_PHYIDX 0 | |
| 372 | #define TSEC2_PHYIDX 0 | |
| 373 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 374 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 375 | ||
| 376 | /* Options are: TSEC[0-1] */ | |
| 377 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 378 | ||
| 379 | /* | |
| 380 | * Environment | |
| 381 | */ | |
| 382 | #ifndef CFG_RAMBOOT | |
| 383 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 921d4b19 | 384 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) |
| 19580e66 DL |
385 | #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
| 386 | #define CFG_ENV_SIZE 0x2000 | |
| 387 | #else | |
| 388 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ | |
| 389 | #define CFG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 390 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) | |
| 391 | #define CFG_ENV_SIZE 0x2000 | |
| 392 | #endif | |
| 393 | ||
| 394 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 395 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 396 | ||
| 397 | /* | |
| 398 | * BOOTP options | |
| 399 | */ | |
| 400 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 401 | #define CONFIG_BOOTP_BOOTPATH | |
| 402 | #define CONFIG_BOOTP_GATEWAY | |
| 403 | #define CONFIG_BOOTP_HOSTNAME | |
| 404 | ||
| 405 | ||
| 406 | /* | |
| 407 | * Command line configuration. | |
| 408 | */ | |
| 409 | #include <config_cmd_default.h> | |
| 410 | ||
| 411 | #define CONFIG_CMD_PING | |
| 412 | #define CONFIG_CMD_I2C | |
| 413 | #define CONFIG_CMD_MII | |
| 414 | #define CONFIG_CMD_DATE | |
| 415 | ||
| 416 | #if defined(CONFIG_PCI) | |
| 417 | #define CONFIG_CMD_PCI | |
| 418 | #endif | |
| 419 | ||
| 420 | #if defined(CFG_RAMBOOT) | |
| 421 | #undef CONFIG_CMD_ENV | |
| 422 | #undef CONFIG_CMD_LOADS | |
| 423 | #endif | |
| 424 | ||
| 425 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
| 426 | ||
| 427 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 428 | ||
| 429 | /* | |
| 430 | * Miscellaneous configurable options | |
| 431 | */ | |
| 432 | #define CFG_LONGHELP /* undef to save memory */ | |
| 433 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
| 434 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 435 | ||
| 436 | #if defined(CONFIG_CMD_KGDB) | |
| 437 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
| 438 | #else | |
| 439 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 440 | #endif | |
| 441 | ||
| 442 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 443 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 444 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 445 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 446 | ||
| 447 | /* | |
| 448 | * For booting Linux, the board info and command line data | |
| 449 | * have to be in the first 8 MB of memory, since this is | |
| 450 | * the maximum mapped by the Linux kernel during initialization. | |
| 451 | */ | |
| 452 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
| 453 | ||
| 454 | /* | |
| 455 | * Core HID Setup | |
| 456 | */ | |
| 457 | #define CFG_HID0_INIT 0x000000000 | |
| 458 | #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK | |
| 459 | #define CFG_HID2 HID2_HBE | |
| 460 | ||
| 19580e66 DL |
461 | /* |
| 462 | * MMU Setup | |
| 463 | */ | |
| 464 | ||
| 465 | /* DDR: cache cacheable */ | |
| 466 | #define CFG_SDRAM_LOWER CFG_SDRAM_BASE | |
| 467 | #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) | |
| 468 | ||
| 469 | #define CFG_IBAT0L (CFG_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 470 | #define CFG_IBAT0U (CFG_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 471 | #define CFG_DBAT0L CFG_IBAT0L | |
| 472 | #define CFG_DBAT0U CFG_IBAT0U | |
| 473 | ||
| 474 | #define CFG_IBAT1L (CFG_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 475 | #define CFG_IBAT1U (CFG_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 476 | #define CFG_DBAT1L CFG_IBAT1L | |
| 477 | #define CFG_DBAT1U CFG_IBAT1U | |
| 478 | ||
| 479 | /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ | |
| 480 | #define CFG_IBAT2L (CFG_IMMR | BATL_PP_10 | \ | |
| 481 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 482 | #define CFG_IBAT2U (CFG_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) | |
| 483 | #define CFG_DBAT2L CFG_IBAT2L | |
| 484 | #define CFG_DBAT2U CFG_IBAT2U | |
| 485 | ||
| 486 | /* BCSR: cache-inhibit and guarded */ | |
| 487 | #define CFG_IBAT3L (CFG_BCSR | BATL_PP_10 | \ | |
| 488 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 489 | #define CFG_IBAT3U (CFG_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 490 | #define CFG_DBAT3L CFG_IBAT3L | |
| 491 | #define CFG_DBAT3U CFG_IBAT3U | |
| 492 | ||
| 493 | /* FLASH: icache cacheable, but dcache-inhibit and guarded */ | |
| 494 | #define CFG_IBAT4L (CFG_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 495 | #define CFG_IBAT4U (CFG_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | |
| 496 | #define CFG_DBAT4L (CFG_FLASH_BASE | BATL_PP_10 | \ | |
| 497 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 498 | #define CFG_DBAT4U CFG_IBAT4U | |
| 499 | ||
| 500 | /* Stack in dcache: cacheable, no memory coherence */ | |
| 501 | #define CFG_IBAT5L (CFG_INIT_RAM_ADDR | BATL_PP_10) | |
| 502 | #define CFG_IBAT5U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 503 | #define CFG_DBAT5L CFG_IBAT5L | |
| 504 | #define CFG_DBAT5U CFG_IBAT5U | |
| 505 | ||
| 506 | #ifdef CONFIG_PCI | |
| 507 | /* PCI MEM space: cacheable */ | |
| 508 | #define CFG_IBAT6L (CFG_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) | |
| 509 | #define CFG_IBAT6U (CFG_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 510 | #define CFG_DBAT6L CFG_IBAT6L | |
| 511 | #define CFG_DBAT6U CFG_IBAT6U | |
| 512 | /* PCI MMIO space: cache-inhibit and guarded */ | |
| 513 | #define CFG_IBAT7L (CFG_PCI_MMIO_PHYS | BATL_PP_10 | \ | |
| 514 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 515 | #define CFG_IBAT7U (CFG_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | |
| 516 | #define CFG_DBAT7L CFG_IBAT7L | |
| 517 | #define CFG_DBAT7U CFG_IBAT7U | |
| 518 | #else | |
| 519 | #define CFG_IBAT6L (0) | |
| 520 | #define CFG_IBAT6U (0) | |
| 521 | #define CFG_IBAT7L (0) | |
| 522 | #define CFG_IBAT7U (0) | |
| 523 | #define CFG_DBAT6L CFG_IBAT6L | |
| 524 | #define CFG_DBAT6U CFG_IBAT6U | |
| 525 | #define CFG_DBAT7L CFG_IBAT7L | |
| 526 | #define CFG_DBAT7U CFG_IBAT7U | |
| 527 | #endif | |
| 528 | ||
| 529 | /* | |
| 530 | * Internal Definitions | |
| 531 | * | |
| 532 | * Boot Flags | |
| 533 | */ | |
| 534 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 535 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 536 | ||
| 537 | #if defined(CONFIG_CMD_KGDB) | |
| 538 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ | |
| 539 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 540 | #endif | |
| 541 | ||
| 542 | /* | |
| 543 | * Environment Configuration | |
| 544 | */ | |
| 545 | ||
| 546 | #define CONFIG_ENV_OVERWRITE | |
| 547 | ||
| 548 | #if defined(CONFIG_TSEC_ENET) | |
| 549 | #define CONFIG_HAS_ETH0 | |
| 550 | #define CONFIG_ETHADDR 00:E0:0C:00:83:79 | |
| 551 | #define CONFIG_HAS_ETH1 | |
| 552 | #define CONFIG_ETH1ADDR 00:E0:0C:00:83:78 | |
| 553 | #endif | |
| 554 | ||
| 555 | #define CONFIG_BAUDRATE 115200 | |
| 556 | ||
| 557 | #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ | |
| 558 | ||
| 559 | #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ | |
| 560 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 561 | ||
| 562 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 563 | "netdev=eth0\0" \ | |
| 564 | "consoledev=ttyS0\0" \ | |
| 565 | "ramdiskaddr=1000000\0" \ | |
| 566 | "ramdiskfile=ramfs.83xx\0" \ | |
| 567 | "fdtaddr=400000\0" \ | |
| 568 | "fdtfile=mpc837xemds.dtb\0" \ | |
| 569 | "" | |
| 570 | ||
| 571 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 572 | "setenv bootargs root=/dev/nfs rw " \ | |
| 573 | "nfsroot=$serverip:$rootpath " \ | |
| 574 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 575 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 576 | "tftp $loadaddr $bootfile;" \ | |
| 577 | "tftp $fdtaddr $fdtfile;" \ | |
| 578 | "bootm $loadaddr - $fdtaddr" | |
| 579 | ||
| 580 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 581 | "setenv bootargs root=/dev/ram rw " \ | |
| 582 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 583 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 584 | "tftp $loadaddr $bootfile;" \ | |
| 585 | "tftp $fdtaddr $fdtfile;" \ | |
| 586 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 587 | ||
| 588 | ||
| 589 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 590 | ||
| 591 | #endif /* __CONFIG_H */ |