projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 9490a7f1 | 1 | /* |
| c7e1a43d | 2 | * Copyright 2007-2009,2010 Freescale Semiconductor, Inc. |
| 9490a7f1 KG |
3 | * |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 24 | * mpc8536ds board configuration file | |
| 25 | * | |
| 26 | */ | |
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| c7e1a43d KG |
30 | #include "../board/freescale/common/ics307_clk.h" |
| 31 | ||
| d24f2d32 | 32 | #ifdef CONFIG_36BIT |
| 337f9fde KG |
33 | #define CONFIG_PHYS_64BIT 1 |
| 34 | #endif | |
| 35 | ||
| d24f2d32 | 36 | #ifdef CONFIG_NAND |
| 9a1a0aed MH |
37 | #define CONFIG_NAND_U_BOOT 1 |
| 38 | #define CONFIG_RAMBOOT_NAND 1 | |
| 2ae18241 | 39 | #define CONFIG_SYS_TEXT_BASE 0xf8f82000 |
| 9a1a0aed MH |
40 | #endif |
| 41 | ||
| d24f2d32 | 42 | #ifdef CONFIG_SDCARD |
| e40ac487 | 43 | #define CONFIG_RAMBOOT_SDCARD 1 |
| 2ae18241 | 44 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 |
| e40ac487 MH |
45 | #endif |
| 46 | ||
| d24f2d32 | 47 | #ifdef CONFIG_SPIFLASH |
| e40ac487 | 48 | #define CONFIG_RAMBOOT_SPIFLASH 1 |
| 2ae18241 WD |
49 | #define CONFIG_SYS_TEXT_BASE 0xf8f80000 |
| 50 | #endif | |
| 51 | ||
| 52 | #ifndef CONFIG_SYS_TEXT_BASE | |
| 53 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
| e40ac487 MH |
54 | #endif |
| 55 | ||
| 9490a7f1 KG |
56 | /* High Level Configuration Options */ |
| 57 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 58 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 59 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
| 60 | #define CONFIG_MPC8536 1 | |
| 61 | #define CONFIG_MPC8536DS 1 | |
| 62 | ||
| c51fc5d5 | 63 | #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ |
| 9490a7f1 KG |
64 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 65 | #define CONFIG_PCI1 1 /* Enable PCI controller 1 */ | |
| 66 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
| 67 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| 68 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
| 69 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 70 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
| 0151cbac | 71 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| af025065 | 72 | #define CONFIG_SYS_HAS_SERDES /* has SERDES */ |
| 9490a7f1 KG |
73 | |
| 74 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
| f6155c6f | 75 | #define CONFIG_E1000 1 /* Defind e1000 pci Ethernet card*/ |
| 9490a7f1 KG |
76 | |
| 77 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 78 | #define CONFIG_ENV_OVERWRITE | |
| 79 | ||
| c7e1a43d KG |
80 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ |
| 81 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() | |
| 9490a7f1 | 82 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
| 9490a7f1 KG |
83 | |
| 84 | /* | |
| 85 | * These can be toggled for performance analysis, otherwise use default. | |
| 86 | */ | |
| 87 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
| 88 | #define CONFIG_BTB /* toggle branch predition */ | |
| 9490a7f1 | 89 | |
| 80522dc8 AF |
90 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
| 91 | ||
| 9490a7f1 KG |
92 | #define CONFIG_ENABLE_36BIT_PHYS 1 |
| 93 | ||
| 337f9fde KG |
94 | #ifdef CONFIG_PHYS_64BIT |
| 95 | #define CONFIG_ADDR_MAP 1 | |
| 96 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
| 97 | #endif | |
| 98 | ||
| 07355700 MH |
99 | #define CONFIG_SYS_MEMTEST_START 0x00010000 /* skip exception vectors */ |
| 100 | #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */ | |
| 9490a7f1 KG |
101 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 102 | ||
| 9a1a0aed MH |
103 | /* |
| 104 | * Config the L2 Cache as L2 SRAM | |
| 105 | */ | |
| 106 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
| 107 | #ifdef CONFIG_PHYS_64BIT | |
| 108 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull | |
| 109 | #else | |
| 110 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
| 111 | #endif | |
| 112 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
| 113 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
| 114 | ||
| 9490a7f1 KG |
115 | /* |
| 116 | * Base addresses -- Note these are effective addresses where the | |
| 117 | * actual resources get mapped (not physical addresses) | |
| 118 | */ | |
| 6d0f6bcf | 119 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| 337f9fde | 120 | #ifdef CONFIG_PHYS_64BIT |
| 07355700 | 121 | #define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ |
| 337f9fde | 122 | #else |
| 07355700 | 123 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR |
| 337f9fde | 124 | #endif |
| 07355700 | 125 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| 9490a7f1 | 126 | |
| 9a1a0aed MH |
127 | #if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) |
| 128 | #define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR | |
| 129 | #else | |
| 130 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
| 131 | #endif | |
| 132 | ||
| 9490a7f1 | 133 | /* DDR Setup */ |
| 337f9fde | 134 | #define CONFIG_VERY_BIG_RAM |
| 9490a7f1 KG |
135 | #define CONFIG_FSL_DDR2 |
| 136 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 137 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 138 | #define CONFIG_DDR_SPD | |
| 139 | #undef CONFIG_DDR_DLL | |
| 140 | ||
| 9b0ad1b1 | 141 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
| 9490a7f1 KG |
142 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
| 143 | ||
| 6d0f6bcf JCPV |
144 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
| 145 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 9490a7f1 KG |
146 | |
| 147 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
| 148 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
| 149 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
| 150 | ||
| 151 | /* I2C addresses of SPD EEPROMs */ | |
| 152 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ | |
| 6d0f6bcf | 153 | #define CONFIG_SYS_SPD_BUS_NUM 1 |
| 9490a7f1 KG |
154 | |
| 155 | /* These are used when DDR doesn't use SPD. */ | |
| 07355700 | 156 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
| 6d0f6bcf | 157 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F |
| 07355700 | 158 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ |
| 6d0f6bcf JCPV |
159 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 |
| 160 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 161 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
| 162 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
| 163 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
| 164 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 165 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
| 166 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 167 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
| 168 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 169 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
| 07355700 | 170 | #define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */ |
| 6d0f6bcf JCPV |
171 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 |
| 172 | ||
| 173 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
| 174 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
| 175 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
| 9490a7f1 | 176 | |
| 9490a7f1 KG |
177 | /* Make sure required options are set */ |
| 178 | #ifndef CONFIG_SPD_EEPROM | |
| 179 | #error ("CONFIG_SPD_EEPROM is required") | |
| 180 | #endif | |
| 181 | ||
| 182 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 183 | ||
| 184 | ||
| 185 | /* | |
| 186 | * Memory map -- xxx -this is wrong, needs updating | |
| 187 | * | |
| 188 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 189 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
| 190 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
| 191 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
| 192 | * | |
| 193 | * Localbus cacheable (TBD) | |
| 194 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
| 195 | * | |
| 196 | * Localbus non-cacheable | |
| c57fc289 | 197 | * 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable |
| 9490a7f1 | 198 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable |
| c57fc289 | 199 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
| 9490a7f1 KG |
200 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
| 201 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
| 202 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
| 203 | */ | |
| 204 | ||
| 205 | /* | |
| 206 | * Local Bus Definitions | |
| 207 | */ | |
| 6d0f6bcf | 208 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
| 337f9fde KG |
209 | #ifdef CONFIG_PHYS_64BIT |
| 210 | #define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull | |
| 211 | #else | |
| c953ddfd | 212 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
| 337f9fde | 213 | #endif |
| 9490a7f1 | 214 | |
| 9a1a0aed | 215 | #define CONFIG_FLASH_BR_PRELIM \ |
| 07355700 MH |
216 | (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \ |
| 217 | | BR_PS_16 | BR_V) | |
| 9a1a0aed | 218 | #define CONFIG_FLASH_OR_PRELIM 0xf8000ff7 |
| 9490a7f1 | 219 | |
| 07355700 MH |
220 | #define CONFIG_SYS_BR1_PRELIM \ |
| 221 | (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ | |
| 222 | | BR_PS_16 | BR_V) | |
| c953ddfd | 223 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 |
| 9490a7f1 | 224 | |
| 07355700 MH |
225 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \ |
| 226 | CONFIG_SYS_FLASH_BASE_PHYS } | |
| 6d0f6bcf | 227 | #define CONFIG_SYS_FLASH_QUIET_TEST |
| 9490a7f1 KG |
228 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
| 229 | ||
| 07355700 MH |
230 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
| 231 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
| 6d0f6bcf | 232 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 07355700 MH |
233 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ |
| 234 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 9490a7f1 | 235 | |
| 14d0a02a | 236 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| 9490a7f1 | 237 | |
| e40ac487 MH |
238 | #if defined(CONFIG_SYS_SPL) || defined(CONFIG_RAMBOOT_NAND) \ |
| 239 | || defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) | |
| 9a1a0aed MH |
240 | #define CONFIG_SYS_RAMBOOT |
| 241 | #else | |
| 242 | #undef CONFIG_SYS_RAMBOOT | |
| 243 | #endif | |
| 244 | ||
| 9490a7f1 | 245 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
246 | #define CONFIG_SYS_FLASH_CFI |
| 247 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| 248 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
| 9490a7f1 KG |
249 | |
| 250 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
| 251 | ||
| 252 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ | |
| 253 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
| 337f9fde KG |
254 | #ifdef CONFIG_PHYS_64BIT |
| 255 | #define PIXIS_BASE_PHYS 0xfffdf0000ull | |
| 256 | #else | |
| 52b565f5 | 257 | #define PIXIS_BASE_PHYS PIXIS_BASE |
| 337f9fde | 258 | #endif |
| 9490a7f1 | 259 | |
| 52b565f5 | 260 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
| 07355700 | 261 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
| 9490a7f1 KG |
262 | |
| 263 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
| 264 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 265 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 266 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
| 267 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 268 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
| 269 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
| 270 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 271 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
| 272 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 273 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
| 274 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 275 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 276 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
| 277 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 6bb5b412 KG |
278 | #define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */ |
| 279 | #define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */ | |
| 280 | #define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */ | |
| 281 | #define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */ | |
| 282 | #define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */ | |
| 283 | #define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */ | |
| 284 | #define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */ | |
| 9490a7f1 KG |
285 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 286 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 287 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
| 288 | #define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */ | |
| 289 | #define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */ | |
| 290 | #define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */ | |
| 291 | #define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */ | |
| 292 | #define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */ | |
| 293 | #define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */ | |
| 294 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
| 295 | #define PIXIS_LED 0x25 /* LED Register */ | |
| 296 | ||
| 9a1a0aed MH |
297 | #define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */ |
| 298 | ||
| 9490a7f1 KG |
299 | /* old pixis referenced names */ |
| 300 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 301 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 302 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
| 9490a7f1 | 303 | |
| 6d0f6bcf JCPV |
304 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 305 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
| 306 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
| 9490a7f1 | 307 | |
| 6d0f6bcf | 308 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
| 07355700 MH |
309 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
| 310 | (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
| 6d0f6bcf | 311 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| 9490a7f1 | 312 | |
| 07355700 MH |
313 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 314 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| 9490a7f1 | 315 | |
| 9a1a0aed | 316 | #ifndef CONFIG_NAND_SPL |
| 337f9fde KG |
317 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
| 318 | #ifdef CONFIG_PHYS_64BIT | |
| 319 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull | |
| 320 | #else | |
| 321 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 322 | #endif | |
| 9a1a0aed MH |
323 | #else |
| 324 | #define CONFIG_SYS_NAND_BASE 0xfff00000 | |
| 325 | #ifdef CONFIG_PHYS_64BIT | |
| 326 | #define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull | |
| 327 | #else | |
| 328 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
| 329 | #endif | |
| 330 | #endif | |
| c57fc289 JJ |
331 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ |
| 332 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
| 333 | CONFIG_SYS_NAND_BASE + 0x80000, \ | |
| 334 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
| 335 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
| c57fc289 JJ |
336 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
| 337 | #define CONFIG_CMD_NAND 1 | |
| 338 | #define CONFIG_NAND_FSL_ELBC 1 | |
| 339 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
| 340 | ||
| 9a1a0aed MH |
341 | /* NAND boot: 4K NAND loader config */ |
| 342 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
| 343 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
| 344 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
| 345 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
| 346 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
| 347 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
| 348 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
| 349 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
| 350 | ||
| c57fc289 | 351 | /* NAND flash config */ |
| 07355700 MH |
352 | #define CONFIG_NAND_BR_PRELIM \ |
| 353 | (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
| 354 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 355 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 356 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 357 | | BR_V) /* valid */ | |
| 358 | #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
| 359 | | OR_FCM_PGS /* Large Page*/ \ | |
| 360 | | OR_FCM_CSCT \ | |
| 361 | | OR_FCM_CST \ | |
| 362 | | OR_FCM_CHT \ | |
| 363 | | OR_FCM_SCY_1 \ | |
| 364 | | OR_FCM_TRLX \ | |
| 365 | | OR_FCM_EHTR) | |
| 366 | ||
| 9a1a0aed MH |
367 | #ifdef CONFIG_RAMBOOT_NAND |
| 368 | #define CONFIG_SYS_BR0_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
| 369 | #define CONFIG_SYS_OR0_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 370 | #define CONFIG_SYS_BR2_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 371 | #define CONFIG_SYS_OR2_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 372 | #else | |
| 373 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ | |
| 374 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
| 07355700 MH |
375 | #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ |
| 376 | #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 9a1a0aed | 377 | #endif |
| 07355700 MH |
378 | |
| 379 | #define CONFIG_SYS_BR4_PRELIM \ | |
| 380 | (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)) \ | |
| 381 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 382 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 383 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 384 | | BR_V) /* valid */ | |
| 385 | #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 386 | #define CONFIG_SYS_BR5_PRELIM \ | |
| 387 | (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)) \ | |
| 388 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 389 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 390 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 391 | | BR_V) /* valid */ | |
| 392 | #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| 393 | ||
| 394 | #define CONFIG_SYS_BR6_PRELIM \ | |
| 395 | (BR_PHYS_ADDR((CONFIG_SYS_NAND_BASE_PHYS + 0xc0000)) \ | |
| 396 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
| 397 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
| 398 | | BR_MS_FCM /* MSEL = FCM */ \ | |
| 399 | | BR_V) /* valid */ | |
| 400 | #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
| c57fc289 | 401 | |
| 9490a7f1 KG |
402 | /* Serial Port - controlled on board with jumper J8 |
| 403 | * open - index 2 | |
| 404 | * shorted - index 1 | |
| 405 | */ | |
| 406 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
407 | #define CONFIG_SYS_NS16550 |
| 408 | #define CONFIG_SYS_NS16550_SERIAL | |
| 409 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 410 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| 93341909 KG |
411 | #ifdef CONFIG_NAND_SPL |
| 412 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
| 413 | #endif | |
| 9490a7f1 | 414 | |
| 6d0f6bcf | 415 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| 9490a7f1 KG |
416 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 417 | ||
| 07355700 MH |
418 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) |
| 419 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) | |
| 9490a7f1 KG |
420 | |
| 421 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
422 | #define CONFIG_SYS_HUSH_PARSER |
| 423 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 424 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| 9490a7f1 KG |
425 | #endif |
| 426 | ||
| 427 | /* | |
| 428 | * Pass open firmware flat tree | |
| 429 | */ | |
| 430 | #define CONFIG_OF_LIBFDT 1 | |
| 431 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 432 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| 433 | ||
| 9490a7f1 KG |
434 | /* |
| 435 | * I2C | |
| 436 | */ | |
| 437 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 438 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 439 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 440 | #define CONFIG_I2C_MULTI_BUS | |
| 6d0f6bcf JCPV |
441 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 442 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 443 | #define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}} /* Don't probe these addrs */ | |
| 444 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
| 445 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
| 9490a7f1 KG |
446 | |
| 447 | /* | |
| 448 | * I2C2 EEPROM | |
| 449 | */ | |
| 32628c50 JCPV |
450 | #define CONFIG_ID_EEPROM |
| 451 | #ifdef CONFIG_ID_EEPROM | |
| 6d0f6bcf | 452 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 9490a7f1 | 453 | #endif |
| 6d0f6bcf JCPV |
454 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 455 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| 456 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
| 9490a7f1 KG |
457 | |
| 458 | /* | |
| 459 | * General PCI | |
| 460 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 461 | */ | |
| 462 | ||
| 5af0fdd8 | 463 | #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 |
| 337f9fde KG |
464 | #ifdef CONFIG_PHYS_64BIT |
| 465 | #define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000 | |
| 466 | #define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull | |
| 467 | #else | |
| 5af0fdd8 KG |
468 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
| 469 | #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 | |
| 337f9fde | 470 | #endif |
| 6d0f6bcf | 471 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
| 337f9fde KG |
472 | #define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 |
| 473 | #define CONFIG_SYS_PCI1_IO_BUS 0x00000000 | |
| 474 | #ifdef CONFIG_PHYS_64BIT | |
| 475 | #define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull | |
| 476 | #else | |
| 477 | #define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000 | |
| 478 | #endif | |
| 479 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */ | |
| 9490a7f1 KG |
480 | |
| 481 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
| 5af0fdd8 | 482 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000 |
| 337f9fde KG |
483 | #ifdef CONFIG_PHYS_64BIT |
| 484 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000 | |
| 485 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull | |
| 486 | #else | |
| 10795f42 | 487 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000 |
| 5af0fdd8 | 488 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000 |
| 337f9fde | 489 | #endif |
| 6d0f6bcf | 490 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */ |
| aca5f018 | 491 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000 |
| 337f9fde KG |
492 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
| 493 | #ifdef CONFIG_PHYS_64BIT | |
| 494 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull | |
| 495 | #else | |
| 6d0f6bcf | 496 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000 |
| 337f9fde | 497 | #endif |
| 6d0f6bcf | 498 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ |
| 9490a7f1 KG |
499 | |
| 500 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
| 5af0fdd8 | 501 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000 |
| 337f9fde KG |
502 | #ifdef CONFIG_PHYS_64BIT |
| 503 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000 | |
| 504 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull | |
| 505 | #else | |
| 10795f42 | 506 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000 |
| 5af0fdd8 | 507 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000 |
| 337f9fde | 508 | #endif |
| 6d0f6bcf | 509 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */ |
| aca5f018 | 510 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000 |
| 337f9fde KG |
511 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
| 512 | #ifdef CONFIG_PHYS_64BIT | |
| 513 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull | |
| 514 | #else | |
| 6d0f6bcf | 515 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000 |
| 337f9fde | 516 | #endif |
| 6d0f6bcf | 517 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ |
| 9490a7f1 KG |
518 | |
| 519 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ | |
| 5af0fdd8 | 520 | #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 |
| 337f9fde KG |
521 | #ifdef CONFIG_PHYS_64BIT |
| 522 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 | |
| 523 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull | |
| 524 | #else | |
| 10795f42 | 525 | #define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 |
| 5af0fdd8 | 526 | #define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 |
| 337f9fde | 527 | #endif |
| 6d0f6bcf | 528 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
| aca5f018 | 529 | #define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000 |
| 337f9fde KG |
530 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
| 531 | #ifdef CONFIG_PHYS_64BIT | |
| 532 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull | |
| 533 | #else | |
| 6d0f6bcf | 534 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000 |
| 337f9fde | 535 | #endif |
| 6d0f6bcf | 536 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ |
| 9490a7f1 KG |
537 | |
| 538 | #if defined(CONFIG_PCI) | |
| 539 | ||
| 540 | #define CONFIG_NET_MULTI | |
| 541 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 542 | ||
| 543 | /*PCIE video card used*/ | |
| aca5f018 | 544 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT |
| 9490a7f1 KG |
545 | |
| 546 | /*PCI video card used*/ | |
| aca5f018 | 547 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ |
| 9490a7f1 KG |
548 | |
| 549 | /* video */ | |
| 550 | #define CONFIG_VIDEO | |
| 551 | ||
| 552 | #if defined(CONFIG_VIDEO) | |
| 553 | #define CONFIG_BIOSEMU | |
| 554 | #define CONFIG_CFB_CONSOLE | |
| 555 | #define CONFIG_VIDEO_SW_CURSOR | |
| 556 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 557 | #define CONFIG_ATI_RADEON_FB | |
| 558 | #define CONFIG_VIDEO_LOGO | |
| 559 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
| aca5f018 | 560 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT |
| 9490a7f1 KG |
561 | #endif |
| 562 | ||
| 563 | #undef CONFIG_EEPRO100 | |
| 564 | #undef CONFIG_TULIP | |
| 565 | #undef CONFIG_RTL8139 | |
| 566 | ||
| 9490a7f1 | 567 | #ifndef CONFIG_PCI_PNP |
| 5f91ef6a KG |
568 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS |
| 569 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS | |
| 9490a7f1 KG |
570 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
| 571 | #endif | |
| 572 | ||
| 573 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 574 | ||
| 575 | #endif /* CONFIG_PCI */ | |
| 576 | ||
| 577 | /* SATA */ | |
| 578 | #define CONFIG_LIBATA | |
| 579 | #define CONFIG_FSL_SATA | |
| 580 | ||
| 6d0f6bcf | 581 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 |
| 9490a7f1 | 582 | #define CONFIG_SATA1 |
| 6d0f6bcf JCPV |
583 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR |
| 584 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
| 9490a7f1 | 585 | #define CONFIG_SATA2 |
| 6d0f6bcf JCPV |
586 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR |
| 587 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
| 9490a7f1 KG |
588 | |
| 589 | #ifdef CONFIG_FSL_SATA | |
| 590 | #define CONFIG_LBA48 | |
| 591 | #define CONFIG_CMD_SATA | |
| 592 | #define CONFIG_DOS_PARTITION | |
| 593 | #define CONFIG_CMD_EXT2 | |
| 594 | #endif | |
| 595 | ||
| 596 | #if defined(CONFIG_TSEC_ENET) | |
| 597 | ||
| 598 | #ifndef CONFIG_NET_MULTI | |
| 599 | #define CONFIG_NET_MULTI 1 | |
| 600 | #endif | |
| 601 | ||
| 602 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 603 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 604 | #define CONFIG_TSEC1 1 | |
| 605 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 606 | #define CONFIG_TSEC3 1 | |
| 607 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 608 | ||
| 2e26d837 JJ |
609 | #define CONFIG_FSL_SGMII_RISER 1 |
| 610 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
| 611 | ||
| 9490a7f1 KG |
612 | #define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */ |
| 613 | #define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */ | |
| 614 | ||
| 615 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 616 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 617 | ||
| 618 | #define TSEC1_PHYIDX 0 | |
| 619 | #define TSEC3_PHYIDX 0 | |
| 620 | ||
| 621 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 622 | ||
| 623 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 624 | ||
| 625 | #endif /* CONFIG_TSEC_ENET */ | |
| 626 | ||
| 627 | /* | |
| 628 | * Environment | |
| 629 | */ | |
| 9a1a0aed MH |
630 | |
| 631 | #if defined(CONFIG_SYS_RAMBOOT) | |
| 632 | #if defined(CONFIG_RAMBOOT_NAND) | |
| 633 | #define CONFIG_ENV_IS_IN_NAND 1 | |
| 634 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
| 635 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) | |
| e40ac487 MH |
636 | #elif defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) |
| 637 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ | |
| 638 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
| 639 | #define CONFIG_ENV_SIZE 0x2000 | |
| 9a1a0aed | 640 | #endif |
| 9490a7f1 | 641 | #else |
| 9a1a0aed MH |
642 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 643 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
| 644 | #define CONFIG_ENV_ADDR 0xfff80000 | |
| 645 | #else | |
| 646 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
| 647 | #endif | |
| 648 | #define CONFIG_ENV_SIZE 0x2000 | |
| 649 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
| 9490a7f1 | 650 | #endif |
| 9490a7f1 KG |
651 | |
| 652 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 653 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| 9490a7f1 KG |
654 | |
| 655 | /* | |
| 656 | * Command line configuration. | |
| 657 | */ | |
| 658 | #include <config_cmd_default.h> | |
| 659 | ||
| 660 | #define CONFIG_CMD_IRQ | |
| 661 | #define CONFIG_CMD_PING | |
| 662 | #define CONFIG_CMD_I2C | |
| 663 | #define CONFIG_CMD_MII | |
| 664 | #define CONFIG_CMD_ELF | |
| 1c9aa76b KG |
665 | #define CONFIG_CMD_IRQ |
| 666 | #define CONFIG_CMD_SETEXPR | |
| 199e262e | 667 | #define CONFIG_CMD_REGINFO |
| 9490a7f1 KG |
668 | |
| 669 | #if defined(CONFIG_PCI) | |
| 670 | #define CONFIG_CMD_PCI | |
| 9490a7f1 KG |
671 | #define CONFIG_CMD_NET |
| 672 | #endif | |
| 673 | ||
| 674 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 675 | ||
| 80522dc8 AF |
676 | #define CONFIG_MMC 1 |
| 677 | ||
| 678 | #ifdef CONFIG_MMC | |
| 679 | #define CONFIG_FSL_ESDHC | |
| 680 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
| 681 | #define CONFIG_CMD_MMC | |
| 682 | #define CONFIG_GENERIC_MMC | |
| 683 | #define CONFIG_CMD_EXT2 | |
| 684 | #define CONFIG_CMD_FAT | |
| 685 | #define CONFIG_DOS_PARTITION | |
| 686 | #endif | |
| 687 | ||
| 9490a7f1 KG |
688 | /* |
| 689 | * Miscellaneous configurable options | |
| 690 | */ | |
| 6d0f6bcf | 691 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 07355700 | 692 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 5be58f5f | 693 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
| 6d0f6bcf JCPV |
694 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 695 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| 9490a7f1 | 696 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 697 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 9490a7f1 | 698 | #else |
| 6d0f6bcf | 699 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| 9490a7f1 | 700 | #endif |
| 07355700 MH |
701 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \ |
| 702 | + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ | |
| 6d0f6bcf | 703 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ |
| 07355700 | 704 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ |
| 6d0f6bcf | 705 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ |
| 9490a7f1 KG |
706 | |
| 707 | /* | |
| 708 | * For booting Linux, the board info and command line data | |
| 89188a62 | 709 | * have to be in the first 16 MB of memory, since this is |
| 9490a7f1 KG |
710 | * the maximum mapped by the Linux kernel during initialization. |
| 711 | */ | |
| 07355700 | 712 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */ |
| 9490a7f1 | 713 | |
| 9490a7f1 KG |
714 | #if defined(CONFIG_CMD_KGDB) |
| 715 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 716 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 717 | #endif | |
| 718 | ||
| 719 | /* | |
| 720 | * Environment Configuration | |
| 721 | */ | |
| 722 | ||
| 723 | /* The mac addresses for all ethernet interface */ | |
| 724 | #if defined(CONFIG_TSEC_ENET) | |
| 725 | #define CONFIG_HAS_ETH0 | |
| 726 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
| 727 | #define CONFIG_HAS_ETH1 | |
| 728 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
| 729 | #define CONFIG_HAS_ETH2 | |
| 730 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
| 731 | #define CONFIG_HAS_ETH3 | |
| 732 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
| 733 | #endif | |
| 734 | ||
| 735 | #define CONFIG_IPADDR 192.168.1.254 | |
| 736 | ||
| 737 | #define CONFIG_HOSTNAME unknown | |
| 738 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 739 | #define CONFIG_BOOTFILE uImage | |
| 07355700 | 740 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| 9490a7f1 KG |
741 | |
| 742 | #define CONFIG_SERVERIP 192.168.1.1 | |
| 743 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
| 744 | #define CONFIG_NETMASK 255.255.255.0 | |
| 745 | ||
| 746 | /* default location for tftp and bootm */ | |
| 747 | #define CONFIG_LOADADDR 1000000 | |
| 748 | ||
| 749 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 750 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
| 751 | ||
| 752 | #define CONFIG_BAUDRATE 115200 | |
| 753 | ||
| 754 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
| 755 | "netdev=eth0\0" \ | |
| 756 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 757 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 14d0a02a WD |
758 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 759 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 760 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
| 761 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 762 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
| 9490a7f1 KG |
763 | "consoledev=ttyS0\0" \ |
| 764 | "ramdiskaddr=2000000\0" \ | |
| 765 | "ramdiskfile=8536ds/ramdisk.uboot\0" \ | |
| 766 | "fdtaddr=c00000\0" \ | |
| 767 | "fdtfile=8536ds/mpc8536ds.dtb\0" \ | |
| 4bc6eb79 VM |
768 | "bdev=sda3\0" \ |
| 769 | "usb_phy_type=ulpi\0" | |
| 9490a7f1 KG |
770 | |
| 771 | #define CONFIG_HDBOOT \ | |
| 772 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 773 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 774 | "tftp $loadaddr $bootfile;" \ | |
| 775 | "tftp $fdtaddr $fdtfile;" \ | |
| 776 | "bootm $loadaddr - $fdtaddr" | |
| 777 | ||
| 778 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 779 | "setenv bootargs root=/dev/nfs rw " \ | |
| 780 | "nfsroot=$serverip:$rootpath " \ | |
| 781 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 782 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 783 | "tftp $loadaddr $bootfile;" \ | |
| 784 | "tftp $fdtaddr $fdtfile;" \ | |
| 785 | "bootm $loadaddr - $fdtaddr" | |
| 786 | ||
| 787 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 788 | "setenv bootargs root=/dev/ram rw " \ | |
| 789 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 790 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 791 | "tftp $loadaddr $bootfile;" \ | |
| 792 | "tftp $fdtaddr $fdtfile;" \ | |
| 793 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| 794 | ||
| 795 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
| 796 | ||
| 797 | #endif /* __CONFIG_H */ |