[people/ms/u-boot.git] / include / configs / MPC8540ADS.h

/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8540ads board configuration file
 *
 * Please refer to doc/README.mpc85xx for more info.
 *
 * Make sure you change the MAC address and other network params first,
 * search for CONFIG_SERVERIP, etc in this file.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE */
#define CONFIG_E500		1	/* BOOKE e500 family */
#define CONFIG_MPC8540		1	/* MPC8540 specific */
#define CONFIG_MPC8540ADS	1	/* MPC8540ADS board specific */

/*
 * default CCARBAR is at 0xff700000
 * assume U-Boot is less than 0.5MB
 */
#define	CONFIG_SYS_TEXT_BASE	0xfff80000

#ifndef CONFIG_HAS_FEC
#define CONFIG_HAS_FEC		1	/* 8540 has FEC */
#endif

#define CONFIG_PCI
#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/*
 * sysclk for MPC85xx
 *
 * Two valid values are:
 *    33000000
 *    66000000
 *
 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
 * is likely the desired value here, so that is now the default.
 * The board, however, can run at 66MHz.  In any event, this value
 * must match the settings of some switches.  Details can be found
 * in the README.mpc85xxads.
 *
 * XXX -- Can't we run at 66 MHz, anyway?  PCI should drop to
 * 33MHz to accommodate, based on a PCI pin.
 * Note that PCI-X won't work at 33MHz.
 */

#ifndef CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_CLK_FREQ	33000000
#endif

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			/* toggle L2 cache */
#define CONFIG_BTB			/* toggle branch predition */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* These are used when DDR doesn't use SPD. */
#define CONFIG_SYS_SDRAM_SIZE	128		/* DDR is 128MB */
#define CONFIG_SYS_DDR_CS0_BNDS	0x00000007	/* 0-128MB */
#define CONFIG_SYS_DDR_CS0_CONFIG	0x80000002
#define CONFIG_SYS_DDR_TIMING_1	0x37344321
#define CONFIG_SYS_DDR_TIMING_2	0x00000800	/* P9-45,may need tuning */
#define CONFIG_SYS_DDR_CONTROL		0xc2000000	/* unbuffered,no DYN_PWR */
#define CONFIG_SYS_DDR_MODE		0x00000062	/* DLL,normal,seq,4/2.5 */
#define CONFIG_SYS_DDR_INTERVAL	0x05200100	/* autocharge,no open page */

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM		0xff001801	/* port size 32bit */

#define CONFIG_SYS_OR0_PRELIM		0xff006ff7	/* 16MB Flash */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	64		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM		0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000    /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x20000000    /* LB refresh timer prescal*/

#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_BSMA1516	\
				| LSDMR_RFCR5		\
				| LSDMR_PRETOACT3	\
				| LSDMR_ACTTORW3	\
				| LSDMR_BL8		\
				| LSDMR_WRC2		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * SDRAM Controller configuration sequence.
 */
#define CONFIG_SYS_LBC_LSDMR_1	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
#define CONFIG_SYS_LBC_LSDMR_2	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_3	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
#define CONFIG_SYS_LBC_LSDMR_4	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
#define CONFIG_SYS_LBC_LSDMR_5	(CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)

/*
 * 32KB, 8-bit wide for ADS config reg
 */
#define CONFIG_SYS_BR4_PRELIM          0xf8000801
#define CONFIG_SYS_OR4_PRELIM		0xffffe1f1
#define CONFIG_SYS_BCSR		(CONFIG_SYS_BR4_PRELIM & 0xffff8000)

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     1
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* RapidIO MMU */
#define CONFIG_SYS_RIO_MEM_VIRT	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_BUS	0xc0000000	/* base address */
#define CONFIG_SYS_RIO_MEM_PHYS	0xc0000000
#define CONFIG_SYS_RIO_MEM_SIZE	0x20000000	/* 128M */

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x100000	/* 1M */

#if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
    #define PCI_ENET0_IOADDR	0xe0000000
    #define PCI_ENET0_MEMADDR	0xe0000000
    #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

#if CONFIG_HAS_FEC
#define CONFIG_MPC85XX_FEC	1
#define CONFIG_MPC85XX_FEC_NAME		"FEC"
#define FEC_PHY_ADDR		3
#define FEC_PHYIDX		0
#define FEC_FLAGS		0
#endif

/* Options are: TSEC[0-1], FEC */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#ifndef CONFIG_SYS_RAMBOOT
  #define CONFIG_ENV_IS_IN_FLASH	1
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
  #define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
  #define CONFIG_ENV_SIZE		0x2000
#else
  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now */
  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only */
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/*
 * Command line configuration.
 */
#define CONFIG_CMD_IRQ

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

#if defined(CONFIG_CMD_KGDB)
    #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
    #define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif

#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */

/* The mac addresses for all ethernet interface */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME		unknown
#define CONFIG_ROOTPATH		"/nfsroot"
#define CONFIG_BOOTFILE		"your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000	/* default location for tftp and bootm */

#undef  CONFIG_BOOTARGS		/* the boot command will set bootargs */

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS0\0"                                                 \
   "ramdiskaddr=1000000\0"						\
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
42d1f039	1	/*
7c57f3e8	2	* Copyright 2004, 2011 Freescale Semiconductor.
42d1f039 WD	3	* (C) Copyright 2002,2003 Motorola,Inc.
	4	* Xianghua Xiao <X.Xiao@motorola.com>
	5	*
3765b3e7	6	* SPDX-License-Identifier: GPL-2.0+
42d1f039 WD	7	*/
42d1f039 WD	8
0ac6f8b7 WD	9	/*
	10	* mpc8540ads board configuration file
	11	*
	12	* Please refer to doc/README.mpc85xx for more info.
	13	*
	14	* Make sure you change the MAC address and other network params first,
92ac5208	15	* search for CONFIG_SERVERIP, etc in this file.
42d1f039 WD	16	*/
	17
	18	#ifndef __CONFIG_H
	19	#define __CONFIG_H
	20
	21	/* High Level Configuration Options */
0ac6f8b7 WD	22	#define CONFIG_BOOKE 1 /* BOOKE */
0ac6f8b7 WD	23	#define CONFIG_E500 1 /* BOOKE e500 family */
0ac6f8b7 WD	24	#define CONFIG_MPC8540 1 /* MPC8540 specific */
	25	#define CONFIG_MPC8540ADS 1 /* MPC8540ADS board specific */
	26
2ae18241 WD	27	/*
	28	* default CCARBAR is at 0xff700000
	29	* assume U-Boot is less than 0.5MB
	30	*/
	31	#define CONFIG_SYS_TEXT_BASE 0xfff80000
	32
288693ab JL	33	#ifndef CONFIG_HAS_FEC
	34	#define CONFIG_HAS_FEC 1 /* 8540 has FEC */
	35	#endif
	36
0ac6f8b7	37	#define CONFIG_PCI
842033e6	38	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	39	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	40	#define CONFIG_TSEC_ENET /* tsec ethernet support */
42d1f039	41	#define CONFIG_ENV_OVERWRITE
7232a272	42	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
42d1f039	43
0ac6f8b7 WD	44	/*
	45	* sysclk for MPC85xx
	46	*
	47	* Two valid values are:
	48	* 33000000
	49	* 66000000
	50	*
	51	* Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
9aea9530 WD	52	* is likely the desired value here, so that is now the default.
	53	* The board, however, can run at 66MHz. In any event, this value
	54	* must match the settings of some switches. Details can be found
	55	* in the README.mpc85xxads.
34c3c0e0 MM	56	*
	57	* XXX -- Can't we run at 66 MHz, anyway? PCI should drop to
	58	* 33MHz to accommodate, based on a PCI pin.
	59	* Note that PCI-X won't work at 33MHz.
0ac6f8b7 WD	60	*/
0ac6f8b7 WD	61
9aea9530	62	#ifndef CONFIG_SYS_CLK_FREQ
34c3c0e0	63	#define CONFIG_SYS_CLK_FREQ 33000000
42d1f039 WD	64	#endif
42d1f039 WD	65
0ac6f8b7 WD	66	/*
	67	* These can be toggled for performance analysis, otherwise use default.
	68	*/
	69	#define CONFIG_L2_CACHE /* toggle L2 cache */
	70	#define CONFIG_BTB /* toggle branch predition */
42d1f039	71
6d0f6bcf JCPV	72	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
6d0f6bcf JCPV	73	#define CONFIG_SYS_MEMTEST_END 0x00400000
42d1f039	74
e46fedfe TT	75	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	76	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
42d1f039	77
9617c8d4	78	/* DDR Setup */
5614e71b	79	#define CONFIG_SYS_FSL_DDR1
9617c8d4 KG	80	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	81	#define CONFIG_DDR_SPD
	82	#undef CONFIG_FSL_DDR_INTERACTIVE
	83
	84	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
9aea9530	85
6d0f6bcf JCPV	86	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	87	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	88
9617c8d4 KG	89	#define CONFIG_NUM_DDR_CONTROLLERS 1
	90	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	91	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	92
	93	/* I2C addresses of SPD EEPROMs */
	94	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	95
	96	/* These are used when DDR doesn't use SPD. */
6d0f6bcf JCPV	97	#define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
	98	#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
	99	#define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
	100	#define CONFIG_SYS_DDR_TIMING_1 0x37344321
	101	#define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
	102	#define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
	103	#define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
	104	#define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
42d1f039	105
0ac6f8b7 WD	106	/*
	107	* SDRAM on the Local Bus
	108	*/
6d0f6bcf JCPV	109	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	110	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
42d1f039	111
6d0f6bcf JCPV	112	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	113	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
42d1f039	114
6d0f6bcf JCPV	115	#define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
	116	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	117	#define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
	118	#undef CONFIG_SYS_FLASH_CHECKSUM
	119	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	120	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
0ac6f8b7	121
14d0a02a	122	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
42d1f039	123
6d0f6bcf JCPV	124	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	125	#define CONFIG_SYS_RAMBOOT
42d1f039	126	#else
6d0f6bcf	127	#undef CONFIG_SYS_RAMBOOT
42d1f039 WD	128	#endif
42d1f039 WD	129
00b1883a	130	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	131	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	132	#define CONFIG_SYS_FLASH_EMPTY_INFO
42d1f039	133
0ac6f8b7 WD	134	#undef CONFIG_CLOCKS_IN_MHZ
0ac6f8b7 WD	135
0ac6f8b7 WD	136	/*
	137	* Local Bus Definitions
	138	*/
	139
	140	/*
	141	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	142	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
0ac6f8b7 WD	143	*
	144	* For BR2, need:
	145	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	146	* port-size = 32-bits = BR2[19:20] = 11
	147	* no parity checking = BR2[21:22] = 00
	148	* SDRAM for MSEL = BR2[24:26] = 011
	149	* Valid = BR[31] = 1
	150	*
	151	* 0 4 8 12 16 20 24 28
	152	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	153	*
6d0f6bcf	154	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
0ac6f8b7 WD	155	* FIXME: the top 17 bits of BR2.
	156	*/
	157
6d0f6bcf	158	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
0ac6f8b7 WD	159
0ac6f8b7 WD	160	/*
6d0f6bcf	161	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
0ac6f8b7 WD	162	*
	163	* For OR2, need:
	164	* 64MB mask for AM, OR2[0:7] = 1111 1100
	165	* XAM, OR2[17:18] = 11
	166	* 9 columns OR2[19-21] = 010
	167	* 13 rows OR2[23-25] = 100
	168	* EAD set for extra time OR[31] = 1
	169	*
	170	* 0 4 8 12 16 20 24 28
	171	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	172	*/
	173
6d0f6bcf	174	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
0ac6f8b7	175
6d0f6bcf JCPV	176	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	177	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	178	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	179	#define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
0ac6f8b7	180
b0fe93ed KG	181	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
	182	\| LSDMR_RFCR5 \
	183	\| LSDMR_PRETOACT3 \
	184	\| LSDMR_ACTTORW3 \
	185	\| LSDMR_BL8 \
	186	\| LSDMR_WRC2 \
	187	\| LSDMR_CL3 \
	188	\| LSDMR_RFEN \
0ac6f8b7 WD	189	)
	190
	191	/*
	192	* SDRAM Controller configuration sequence.
	193	*/
b0fe93ed KG	194	#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_PCHALL)
	195	#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	196	#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_ARFRSH)
	197	#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_MRW)
	198	#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON \| LSDMR_OP_NORMAL)
0ac6f8b7	199
9aea9530 WD	200	/*
	201	* 32KB, 8-bit wide for ADS config reg
	202	*/
6d0f6bcf JCPV	203	#define CONFIG_SYS_BR4_PRELIM 0xf8000801
	204	#define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
	205	#define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
42d1f039	206
6d0f6bcf JCPV	207	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	208	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	209	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
42d1f039	210
25ddd1fb	211	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	212	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
42d1f039	213
6d0f6bcf JCPV	214	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	215	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
42d1f039 WD	216
	217	/* Serial Port */
	218	#define CONFIG_CONS_INDEX 1
6d0f6bcf JCPV	219	#define CONFIG_SYS_NS16550_SERIAL
	220	#define CONFIG_SYS_NS16550_REG_SIZE 1
	221	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
42d1f039	222
6d0f6bcf	223	#define CONFIG_SYS_BAUDRATE_TABLE \
42d1f039 WD	224	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
42d1f039 WD	225
6d0f6bcf JCPV	226	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	227	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
42d1f039	228
20476726 JL	229	/*
	230	* I2C
	231	*/
00f792e0 HS	232	#define CONFIG_SYS_I2C
	233	#define CONFIG_SYS_I2C_FSL
	234	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	235	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	236	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	237	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
0ac6f8b7 WD	238
0ac6f8b7 WD	239	/* RapidIO MMU */
5af0fdd8	240	#define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
10795f42	241	#define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
5af0fdd8	242	#define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
6d0f6bcf	243	#define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
0ac6f8b7 WD	244
	245	/*
	246	* General PCI
362dd830	247	* Memory space is mapped 1-1, but I/O space must start from 0.
0ac6f8b7	248	*/
5af0fdd8	249	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	250	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	251	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	252	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	253	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	254	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	255	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
6d0f6bcf JCPV	256	#define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
42d1f039	257
42d1f039	258	#if defined(CONFIG_PCI)
0ac6f8b7	259
53677ef1	260	#define CONFIG_PCI_PNP /* do pci plug-and-play */
0ac6f8b7	261
42d1f039	262	#undef CONFIG_EEPRO100
0ac6f8b7 WD	263	#undef CONFIG_TULIP
	264
	265	#if !defined(CONFIG_PCI_PNP)
	266	#define PCI_ENET0_IOADDR 0xe0000000
	267	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	268	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
42d1f039	269	#endif
0ac6f8b7 WD	270
0ac6f8b7 WD	271	#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	272	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
0ac6f8b7 WD	273
	274	#endif /* CONFIG_PCI */
	275
0ac6f8b7 WD	276	#if defined(CONFIG_TSEC_ENET)
0ac6f8b7 WD	277
0ac6f8b7	278	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	279	#define CONFIG_TSEC1 1
	280	#define CONFIG_TSEC1_NAME "TSEC0"
	281	#define CONFIG_TSEC2 1
	282	#define CONFIG_TSEC2_NAME "TSEC1"
0ac6f8b7 WD	283	#define TSEC1_PHY_ADDR 0
0ac6f8b7 WD	284	#define TSEC2_PHY_ADDR 1
0ac6f8b7 WD	285	#define TSEC1_PHYIDX 0
0ac6f8b7 WD	286	#define TSEC2_PHYIDX 0
3a79013e AF	287	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	288	#define TSEC2_FLAGS TSEC_GIGABIT
9aea9530	289
288693ab	290	#if CONFIG_HAS_FEC
9aea9530	291	#define CONFIG_MPC85XX_FEC 1
d9b94f28	292	#define CONFIG_MPC85XX_FEC_NAME "FEC"
9aea9530	293	#define FEC_PHY_ADDR 3
0ac6f8b7	294	#define FEC_PHYIDX 0
3a79013e	295	#define FEC_FLAGS 0
288693ab	296	#endif
9aea9530	297
d9b94f28 JL	298	/* Options are: TSEC[0-1], FEC */
d9b94f28 JL	299	#define CONFIG_ETHPRIME "TSEC0"
0ac6f8b7 WD	300
	301	#endif /* CONFIG_TSEC_ENET */
	302
0ac6f8b7 WD	303	/*
	304	* Environment
	305	*/
6d0f6bcf	306	#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0	307	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	308	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	309	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	310	#define CONFIG_ENV_SIZE 0x2000
42d1f039	311	#else
6d0f6bcf	312	#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725	313	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf	314	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	315	#define CONFIG_ENV_SIZE 0x2000
42d1f039 WD	316	#endif
42d1f039 WD	317
0ac6f8b7	318	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	319	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
42d1f039	320
659e2f67 JL	321	/*
	322	* BOOTP options
	323	*/
	324	#define CONFIG_BOOTP_BOOTFILESIZE
	325	#define CONFIG_BOOTP_BOOTPATH
	326	#define CONFIG_BOOTP_GATEWAY
	327	#define CONFIG_BOOTP_HOSTNAME
	328
2835e518 JL	329	/*
	330	* Command line configuration.
	331	*/
1c9aa76b	332	#define CONFIG_CMD_IRQ
2835e518 JL	333
	334	#if defined(CONFIG_PCI)
	335	#define CONFIG_CMD_PCI
	336	#endif
	337
0ac6f8b7	338	#undef CONFIG_WATCHDOG /* watchdog disabled */
42d1f039 WD	339
	340	/*
	341	* Miscellaneous configurable options
	342	*/
6d0f6bcf	343	#define CONFIG_SYS_LONGHELP /* undef to save memory */
5be58f5f KP	344	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f KP	345	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
6d0f6bcf	346	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
0ac6f8b7	347
2835e518	348	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	349	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
42d1f039	350	#else
6d0f6bcf	351	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
42d1f039	352	#endif
0ac6f8b7	353
6d0f6bcf JCPV	354	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	355	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	356	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
42d1f039 WD	357
	358	/*
	359	* For booting Linux, the board info and command line data
a832ac41	360	* have to be in the first 64 MB of memory, since this is
42d1f039 WD	361	* the maximum mapped by the Linux kernel during initialization.
42d1f039 WD	362	*/
a832ac41 KG	363	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	364	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
42d1f039	365
2835e518	366	#if defined(CONFIG_CMD_KGDB)
42d1f039	367	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
42d1f039 WD	368	#endif
42d1f039 WD	369
9aea9530 WD	370	/*
	371	* Environment Configuration
	372	*/
0ac6f8b7 WD	373
0ac6f8b7 WD	374	/* The mac addresses for all ethernet interface */
42d1f039	375	#if defined(CONFIG_TSEC_ENET)
10327dc5	376	#define CONFIG_HAS_ETH0
e2ffd59b	377	#define CONFIG_HAS_ETH1
e2ffd59b	378	#define CONFIG_HAS_ETH2
42d1f039 WD	379	#endif
42d1f039 WD	380
0ac6f8b7 WD	381	#define CONFIG_IPADDR 192.168.1.253
	382
	383	#define CONFIG_HOSTNAME unknown
8b3637c6	384	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	385	#define CONFIG_BOOTFILE "your.uImage"
0ac6f8b7 WD	386
	387	#define CONFIG_SERVERIP 192.168.1.1
	388	#define CONFIG_GATEWAYIP 192.168.1.1
	389	#define CONFIG_NETMASK 255.255.255.0
	390
	391	#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
	392
0ac6f8b7 WD	393	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	394
	395	#define CONFIG_BAUDRATE 115200
	396
9aea9530	397	#define CONFIG_EXTRA_ENV_SETTINGS \
0ac6f8b7 WD	398	"netdev=eth0\0" \
0ac6f8b7 WD	399	"consoledev=ttyS0\0" \
d3ec0d94	400	"ramdiskaddr=1000000\0" \
8272dc2f AF	401	"ramdiskfile=your.ramdisk.u-boot\0" \
	402	"fdtaddr=400000\0" \
	403	"fdtfile=your.fdt.dtb\0"
0ac6f8b7	404
9aea9530	405	#define CONFIG_NFSBOOTCOMMAND \
0ac6f8b7 WD	406	"setenv bootargs root=/dev/nfs rw " \
	407	"nfsroot=$serverip:$rootpath " \
	408	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	409	"console=$consoledev,$baudrate $othbootargs;" \
	410	"tftp $loadaddr $bootfile;" \
8272dc2f AF	411	"tftp $fdtaddr $fdtfile;" \
8272dc2f AF	412	"bootm $loadaddr - $fdtaddr"
0ac6f8b7 WD	413
	414	#define CONFIG_RAMBOOTCOMMAND \
	415	"setenv bootargs root=/dev/ram rw " \
	416	"console=$consoledev,$baudrate $othbootargs;" \
	417	"tftp $ramdiskaddr $ramdiskfile;" \
	418	"tftp $loadaddr $bootfile;" \
8272dc2f	419	"tftp $fdtaddr $fdtfile;" \
d3ec0d94	420	"bootm $loadaddr $ramdiskaddr $fdtaddr"
0ac6f8b7 WD	421
0ac6f8b7 WD	422	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
42d1f039 WD	423
42d1f039 WD	424	#endif /* __CONFIG_H */