projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 0cde4b00 JL |
1 | /* |
| 2 | * Copyright 2007 Freescale Semiconductor, Inc. | |
| 3 | * | |
| 4 | * See file CREDITS for list of people who contributed to this | |
| 5 | * project. | |
| 6 | * | |
| 7 | * This program is free software; you can redistribute it and/or | |
| 8 | * modify it under the terms of the GNU General Public License as | |
| 9 | * published by the Free Software Foundation; either version 2 of | |
| 10 | * the License, or (at your option) any later version. | |
| 11 | * | |
| 12 | * This program is distributed in the hope that it will be useful, | |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 15 | * GNU General Public License for more details. | |
| 16 | * | |
| 17 | * You should have received a copy of the GNU General Public License | |
| 18 | * along with this program; if not, write to the Free Software | |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 20 | * MA 02111-1307 USA | |
| 21 | */ | |
| 22 | ||
| 23 | /* | |
| 24 | * mpc8544ds board configuration file | |
| 25 | * | |
| 26 | */ | |
| 27 | #ifndef __CONFIG_H | |
| 28 | #define __CONFIG_H | |
| 29 | ||
| 30 | /* High Level Configuration Options */ | |
| 31 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
| 32 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
| 33 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
| 34 | #define CONFIG_MPC8544 1 | |
| 35 | #define CONFIG_MPC8544DS 1 | |
| 36 | ||
| 837f1ba0 ES |
37 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 38 | #define CONFIG_PCI1 1 /* PCI controller 1 */ | |
| 39 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
| 40 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
| 41 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
| 42 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
| 43 | ||
| 44 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
| 0cde4b00 JL |
45 | #define CONFIG_ENV_OVERWRITE |
| 46 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 47 | #undef CONFIG_DDR_DLL | |
| 48 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
| 49 | ||
| 50 | #define CONFIG_DDR_ECC /* only for ECC DDR module */ | |
| 51 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
| 52 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 53 | ||
| 54 | #define CONFIG_DDR_ECC_CMD | |
| 837f1ba0 | 55 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
| 0cde4b00 JL |
56 | |
| 57 | /* | |
| 58 | * When initializing flash, if we cannot find the manufacturer ID, | |
| 59 | * assume this is the AMD flash associated with the CDS board. | |
| 60 | * This allows booting from a promjet. | |
| 61 | */ | |
| 62 | #define CONFIG_ASSUME_AMD_FLASH | |
| 63 | ||
| 64 | #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ | |
| 65 | ||
| 66 | #ifndef __ASSEMBLY__ | |
| 67 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 68 | #endif | |
| 69 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
| 70 | ||
| 71 | /* | |
| 72 | * These can be toggled for performance analysis, otherwise use default. | |
| 73 | */ | |
| 837f1ba0 | 74 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
| 0cde4b00 JL |
75 | #define CONFIG_BTB /* toggle branch predition */ |
| 76 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
| 77 | #define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ | |
| 78 | ||
| 79 | /* | |
| 80 | * Only possible on E500 Version 2 or newer cores. | |
| 81 | */ | |
| 82 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
| 83 | ||
| 84 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
| 85 | ||
| 86 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
| 87 | #define CFG_MEMTEST_START 0x00200000 /* memtest works on */ | |
| 88 | #define CFG_MEMTEST_END 0x00400000 | |
| 89 | #define CFG_ALT_MEMTEST | |
| 837f1ba0 | 90 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
| 0cde4b00 JL |
91 | |
| 92 | /* | |
| 93 | * Base addresses -- Note these are effective addresses where the | |
| 94 | * actual resources get mapped (not physical addresses) | |
| 95 | */ | |
| 837f1ba0 | 96 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| 0cde4b00 JL |
97 | #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
| 98 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
| 99 | ||
| 100 | #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) | |
| 101 | #define CFG_PCIE1_ADDR (CFG_CCSRBAR+0xa000) | |
| 102 | #define CFG_PCIE2_ADDR (CFG_CCSRBAR+0x9000) | |
| 103 | #define CFG_PCIE3_ADDR (CFG_CCSRBAR+0xb000) | |
| 104 | ||
| 105 | /* | |
| 106 | * DDR Setup | |
| 107 | */ | |
| 108 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
| 109 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
| 110 | ||
| 111 | #define SPD_EEPROM_ADDRESS 0x51 /* DDR DIMM */ | |
| 112 | ||
| 113 | /* | |
| 114 | * Make sure required options are set | |
| 115 | */ | |
| 116 | #ifndef CONFIG_SPD_EEPROM | |
| 117 | #error ("CONFIG_SPD_EEPROM is required") | |
| 118 | #endif | |
| 119 | ||
| 120 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 121 | ||
| 122 | /* | |
| 123 | * Memory map | |
| 124 | * | |
| 125 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
| 126 | * | |
| 127 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
| 128 | * | |
| 129 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
| 130 | * | |
| 131 | * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable | |
| 132 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
| 133 | * | |
| 134 | * Localbus cacheable | |
| 135 | * | |
| 136 | * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable | |
| 137 | * 0xf401_0000 0xf401_3fff L1 for stack 4K Cacheable TLB0 | |
| 138 | * | |
| 139 | * Localbus non-cacheable | |
| 140 | * | |
| 141 | * 0xf800_0000 0xf80f_ffff NVRAM/CADMUS (*) 1M non-cacheable | |
| 142 | * 0xff00_0000 0xff7f_ffff FLASH (2nd bank) 8M non-cacheable | |
| 143 | * 0xff80_0000 0xffff_ffff FLASH (boot bank) 8M non-cacheable | |
| 144 | * | |
| 145 | */ | |
| 146 | ||
| 147 | /* | |
| 148 | * Local Bus Definitions | |
| 149 | */ | |
| 150 | #define CFG_BOOT_BLOCK 0xfc000000 /* boot TLB */ | |
| 151 | ||
| 152 | #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ | |
| 153 | ||
| 154 | #define CFG_FLASH_BASE 0xff800000 /* start of FLASH 8M */ | |
| 155 | ||
| 156 | #define CFG_BR0_PRELIM 0xff801001 | |
| 157 | #define CFG_BR1_PRELIM 0xfe801001 | |
| 158 | ||
| 159 | #define CFG_OR0_PRELIM 0xff806e65 | |
| 160 | #define CFG_OR1_PRELIM 0xff806e65 | |
| 161 | ||
| 162 | #define CFG_FLASH_BANKS_LIST {0xfe800000,CFG_FLASH_BASE} | |
| 163 | ||
| 164 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
| 165 | #define CFG_MAX_FLASH_SECT 128 /* sectors per device */ | |
| 166 | #undef CFG_FLASH_CHECKSUM | |
| 167 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 168 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 169 | ||
| 170 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
| 171 | ||
| 172 | #define CFG_FLASH_CFI_DRIVER | |
| 173 | #define CFG_FLASH_CFI | |
| 174 | #define CFG_FLASH_EMPTY_INFO | |
| 175 | ||
| 176 | #define CFG_LBC_NONCACHE_BASE 0xf8000000 | |
| 177 | ||
| 178 | #define CFG_BR2_PRELIM 0xf8201001 /* port size 16bit */ | |
| 179 | #define CFG_OR2_PRELIM 0xfff06ff7 /* 1MB Compact Flash area*/ | |
| 180 | ||
| 181 | #define CFG_BR3_PRELIM 0xf8100801 /* port size 8bit */ | |
| 182 | #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
| 183 | ||
| 184 | #define PIXIS_BASE 0xf8100000 /* PIXIS registers */ | |
| 185 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
| 186 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 187 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 188 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 189 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch | |
| 190 | * register */ | |
| 191 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 192 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 193 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 194 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 195 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 196 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
| 197 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 198 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 199 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 200 | ||
| 201 | ||
| 202 | /* define to use L1 as initial stack */ | |
| 203 | #define CONFIG_L1_INIT_RAM 1 | |
| 204 | #define CFG_INIT_L1_LOCK 1 | |
| 205 | #define CFG_INIT_L1_ADDR 0xf4010000 /* Initial L1 address */ | |
| 206 | #define CFG_INIT_L1_END 0x00004000 /* End of used area in RAM */ | |
| 207 | ||
| 208 | /* define to use L2SRAM as initial stack */ | |
| 209 | #undef CONFIG_L2_INIT_RAM | |
| 210 | #define CFG_INIT_L2_ADDR 0xf8fc0000 | |
| 211 | #define CFG_INIT_L2_END 0x00040000 /* End of used area in RAM */ | |
| 212 | ||
| 213 | #ifdef CONFIG_L1_INIT_RAM | |
| 214 | #define CFG_INIT_RAM_ADDR CFG_INIT_L1_ADDR | |
| 215 | #define CFG_INIT_RAM_END CFG_INIT_L1_END | |
| 216 | #else | |
| 217 | #define CFG_INIT_RAM_ADDR CFG_INIT_L2_ADDR | |
| 218 | #define CFG_INIT_RAM_END CFG_INIT_L2_END | |
| 219 | #endif | |
| 220 | ||
| 221 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
| 222 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
| 223 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
| 224 | ||
| 225 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
| 226 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
| 227 | ||
| 228 | /* Serial Port - controlled on board with jumper J8 | |
| 229 | * open - index 2 | |
| 230 | * shorted - index 1 | |
| 231 | */ | |
| 232 | #define CONFIG_CONS_INDEX 1 | |
| 233 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
| 234 | #define CFG_NS16550 | |
| 235 | #define CFG_NS16550_SERIAL | |
| 236 | #define CFG_NS16550_REG_SIZE 1 | |
| 237 | #define CFG_NS16550_CLK get_bus_freq(0) | |
| 238 | ||
| 239 | #define CFG_BAUDRATE_TABLE \ | |
| 240 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
| 241 | ||
| 242 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
| 243 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
| 244 | ||
| 245 | /* Use the HUSH parser */ | |
| 246 | #define CFG_HUSH_PARSER | |
| 247 | #ifdef CFG_HUSH_PARSER | |
| 248 | #define CFG_PROMPT_HUSH_PS2 "> " | |
| 249 | #endif | |
| 250 | ||
| 251 | /* pass open firmware flat tree */ | |
| 252 | #define CONFIG_OF_FLAT_TREE 1 | |
| 253 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 254 | ||
| 255 | /* maximum size of the flat tree (8K) */ | |
| 256 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
| 257 | ||
| 258 | #define OF_CPU "PowerPC,8544@0" | |
| 259 | #define OF_SOC "soc8544@e0000000" | |
| 260 | #define OF_TBCLK (bd->bi_busfreq / 8) | |
| 261 | #define OF_STDOUT_PATH "/soc8544@e0000000/serial@4500" | |
| 262 | ||
| 263 | /* I2C */ | |
| 264 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
| 265 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
| 266 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
| 267 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
| 268 | #define CFG_I2C_EEPROM_ADDR 0x57 | |
| 269 | #define CFG_I2C_SLAVE 0x7F | |
| 270 | #define CFG_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 271 | #define CFG_I2C_OFFSET 0x3100 | |
| 272 | ||
| 273 | /* | |
| 274 | * General PCI | |
| 275 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
| 276 | */ | |
| 277 | #define CFG_PCIE_PHYS 0x80000000 /* 1G PCIE TLB */ | |
| 278 | #define CFG_PCI_PHYS 0xc0000000 /* 512M PCI TLB */ | |
| 279 | ||
| 280 | #define CFG_PCI1_MEM_BASE 0xc0000000 | |
| 281 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
| 282 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
| 283 | #define CFG_PCI1_IO_BASE 0x00000000 | |
| 284 | #define CFG_PCI1_IO_PHYS 0xe1000000 | |
| 285 | #define CFG_PCI1_IO_SIZE 0x00100000 /* 1M */ | |
| 286 | ||
| 287 | /* PCI view of System Memory */ | |
| 288 | #define CFG_PCI_MEMORY_BUS 0x00000000 | |
| 289 | #define CFG_PCI_MEMORY_PHYS 0x00000000 | |
| 290 | #define CFG_PCI_MEMORY_SIZE 0x80000000 | |
| 291 | ||
| 292 | /* controller 2, Slot 1, tgtid 1, Base address 9000 */ | |
| 293 | #define CFG_PCIE2_MEM_BASE 0x80000000 | |
| 294 | #define CFG_PCIE2_MEM_PHYS CFG_PCIE2_MEM_BASE | |
| 295 | #define CFG_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 296 | #define CFG_PCIE2_IO_BASE 0x00000000 | |
| 297 | #define CFG_PCIE2_IO_PHYS 0xe2000000 | |
| 298 | #define CFG_PCIE2_IO_SIZE 0x00100000 /* 1M */ | |
| 299 | ||
| 300 | /* controller 1, Slot 2,tgtid 2, Base address a000 */ | |
| 301 | #define CFG_PCIE1_MEM_BASE 0xa0000000 | |
| 302 | #define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE | |
| 303 | #define CFG_PCIE1_MEM_SIZE 0x08000000 /* 128M */ | |
| 304 | #define CFG_PCIE1_MEM_BASE2 0xa8000000 | |
| 305 | #define CFG_PCIE1_MEM_PHYS2 CFG_PCIE1_MEM_BASE2 | |
| 306 | #define CFG_PCIE1_MEM_SIZE2 0x04000000 /* 64M */ | |
| 307 | #define CFG_PCIE1_IO_BASE 0x00000000 /* reuse mem LAW */ | |
| 308 | #define CFG_PCIE1_IO_PHYS 0xaf000000 | |
| 309 | #define CFG_PCIE1_IO_SIZE 0x00100000 /* 1M */ | |
| 310 | ||
| 311 | /* controller 3, direct to uli, tgtid 3, Base address b000 */ | |
| 312 | #define CFG_PCIE3_MEM_BASE 0xb0000000 | |
| 313 | #define CFG_PCIE3_MEM_PHYS CFG_PCIE3_MEM_BASE | |
| 314 | #define CFG_PCIE3_MEM_SIZE 0x10000000 /* 256M */ | |
| 315 | #define CFG_PCIE3_IO_BASE 0x00000000 | |
| 316 | #define CFG_PCIE3_IO_PHYS 0xe3000000 | |
| 317 | #define CFG_PCIE3_IO_SIZE 0x00100000 /* 1M */ | |
| 318 | ||
| 319 | #if defined(CONFIG_PCI) | |
| 320 | ||
| 321 | #define CONFIG_NET_MULTI | |
| 322 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
| 323 | ||
| 324 | #undef CONFIG_EEPRO100 | |
| 325 | #undef CONFIG_TULIP | |
| 326 | #define CONFIG_RTL8139 | |
| 327 | ||
| 328 | #ifdef CONFIG_RTL8139 | |
| 329 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
| 330 | #define KSEG1ADDR(x) (x) | |
| 331 | #define _IO_BASE 0x00000000 | |
| 332 | #endif | |
| 333 | ||
| 334 | #ifndef CONFIG_PCI_PNP | |
| 335 | #define PCI_ENET0_IOADDR CFG_PCI1_IO_BASE | |
| 336 | #define PCI_ENET0_MEMADDR CFG_PCI1_IO_BASE | |
| 337 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ | |
| 338 | #endif | |
| 339 | ||
| 340 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
| 341 | #define CONFIG_DOS_PARTITION | |
| 342 | #define CONFIG_SCSI_AHCI | |
| 343 | ||
| 344 | #ifdef CONFIG_SCSI_AHCI | |
| 345 | #define CONFIG_SATA_ULI5288 | |
| 346 | #define CFG_SCSI_MAX_SCSI_ID 4 | |
| 347 | #define CFG_SCSI_MAX_LUN 1 | |
| 837f1ba0 | 348 | #define CFG_SCSI_MAX_DEVICE (CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN) |
| 0cde4b00 JL |
349 | #define CFG_SCSI_MAXDEVICE CFG_SCSI_MAX_DEVICE |
| 350 | #endif /* SCSCI */ | |
| 351 | ||
| 352 | #endif /* CONFIG_PCI */ | |
| 353 | ||
| 354 | ||
| 355 | #if defined(CONFIG_TSEC_ENET) | |
| 356 | ||
| 357 | #ifndef CONFIG_NET_MULTI | |
| 837f1ba0 | 358 | #define CONFIG_NET_MULTI 1 |
| 0cde4b00 JL |
359 | #endif |
| 360 | ||
| 361 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 362 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
| 255a3577 KP |
363 | #define CONFIG_TSEC1 1 |
| 364 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 365 | #define CONFIG_TSEC3 1 | |
| 366 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 0cde4b00 JL |
367 | #undef CONFIG_MPC85XX_FEC |
| 368 | ||
| 837f1ba0 ES |
369 | #define CONFIG_TSEC_TBI 1 /* enable internal TBI phy */ |
| 370 | #define CONFIG_SGMII_RISER | |
| 371 | #define TSEC1_SGMII_PHY_ADDR_OFFSET 0x1c /* sgmii phy base */ | |
| 372 | ||
| 0cde4b00 JL |
373 | #define TSEC1_PHY_ADDR 0 |
| 374 | #define TSEC3_PHY_ADDR 1 | |
| 375 | ||
| 376 | #define TSEC1_PHYIDX 0 | |
| 377 | #define TSEC3_PHYIDX 0 | |
| 378 | ||
| 379 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 380 | ||
| 381 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
| 0cde4b00 JL |
382 | #endif /* CONFIG_TSEC_ENET */ |
| 383 | ||
| 384 | /* | |
| 385 | * Environment | |
| 386 | */ | |
| 387 | #define CFG_ENV_IS_IN_FLASH 1 | |
| 388 | #if CFG_MONITOR_BASE > 0xfff80000 | |
| 389 | #define CFG_ENV_ADDR 0xfff80000 | |
| 390 | #else | |
| 391 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) | |
| 392 | #endif | |
| 393 | #define CFG_ENV_SIZE 0x2000 | |
| 394 | #define CFG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) */ | |
| 395 | ||
| 396 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 397 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
| 398 | ||
| 659e2f67 JL |
399 | /* |
| 400 | * BOOTP options | |
| 401 | */ | |
| 402 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 403 | #define CONFIG_BOOTP_BOOTPATH | |
| 404 | #define CONFIG_BOOTP_GATEWAY | |
| 405 | #define CONFIG_BOOTP_HOSTNAME | |
| 406 | ||
| 407 | ||
| 2835e518 JL |
408 | /* |
| 409 | * Command line configuration. | |
| 410 | */ | |
| 411 | #include <config_cmd_default.h> | |
| 412 | ||
| 413 | #define CONFIG_CMD_PING | |
| 414 | #define CONFIG_CMD_I2C | |
| 415 | #define CONFIG_CMD_MII | |
| 416 | ||
| 0cde4b00 | 417 | #if defined(CONFIG_PCI) |
| 2835e518 JL |
418 | #define CONFIG_CMD_PCI |
| 419 | #define CONFIG_CMD_BEDBUG | |
| 420 | #define CONFIG_CMD_NET | |
| 837f1ba0 ES |
421 | #define CONFIG_CMD_SCSI |
| 422 | #define CONFIG_CMD_EXT2 | |
| 0cde4b00 | 423 | #endif |
| 2835e518 | 424 | |
| 0cde4b00 JL |
425 | |
| 426 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 427 | ||
| 428 | /* | |
| 429 | * Miscellaneous configurable options | |
| 430 | */ | |
| 431 | #define CFG_LONGHELP /* undef to save memory */ | |
| 432 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
| 433 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
| 2835e518 | 434 | #if defined(CONFIG_CMD_KGDB) |
| 0cde4b00 JL |
435 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 436 | #else | |
| 437 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
| 438 | #endif | |
| 439 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
| 440 | #define CFG_MAXARGS 16 /* max number of command args */ | |
| 441 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
| 442 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| 443 | ||
| 444 | /* | |
| 445 | * For booting Linux, the board info and command line data | |
| 446 | * have to be in the first 8 MB of memory, since this is | |
| 447 | * the maximum mapped by the Linux kernel during initialization. | |
| 448 | */ | |
| 837f1ba0 | 449 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| 0cde4b00 JL |
450 | |
| 451 | /* Cache Configuration */ | |
| 837f1ba0 | 452 | #define CFG_DCACHE_SIZE 32768 |
| 0cde4b00 | 453 | #define CFG_CACHELINE_SIZE 32 |
| 2835e518 | 454 | #if defined(CONFIG_CMD_KGDB) |
| 0cde4b00 JL |
455 | #define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ |
| 456 | #endif | |
| 457 | ||
| 458 | /* | |
| 459 | * Internal Definitions | |
| 460 | * | |
| 461 | * Boot Flags | |
| 462 | */ | |
| 463 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
| 464 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
| 465 | ||
| 2835e518 | 466 | #if defined(CONFIG_CMD_KGDB) |
| 0cde4b00 JL |
467 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
| 468 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| 469 | #endif | |
| 470 | ||
| 471 | /* | |
| 472 | * Environment Configuration | |
| 473 | */ | |
| 474 | ||
| 475 | /* The mac addresses for all ethernet interface */ | |
| 476 | #if defined(CONFIG_TSEC_ENET) | |
| 477 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
| 478 | #define CONFIG_HAS_ETH1 | |
| 479 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
| 480 | #define CONFIG_HAS_ETH2 | |
| 481 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
| 482 | #define CONFIG_HAS_ETH3 | |
| 483 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
| 484 | #endif | |
| 485 | ||
| 486 | #define CONFIG_IPADDR 192.168.1.251 | |
| 487 | ||
| 488 | #define CONFIG_HOSTNAME 8544ds_unknown | |
| 489 | #define CONFIG_ROOTPATH /nfs/mpc85xx | |
| 837f1ba0 ES |
490 | #define CONFIG_BOOTFILE 8544ds/uImage.uboot |
| 491 | #define CONFIG_UBOOTPATH 8544ds/u-boot.bin /* TFTP server */ | |
| 0cde4b00 JL |
492 | |
| 493 | #define CONFIG_SERVERIP 192.168.0.1 | |
| 494 | #define CONFIG_GATEWAYIP 192.168.0.1 | |
| 495 | #define CONFIG_NETMASK 255.255.0.0 | |
| 496 | ||
| 497 | #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ | |
| 498 | ||
| 499 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 837f1ba0 | 500 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
| 0cde4b00 JL |
501 | |
| 502 | #define CONFIG_BAUDRATE 115200 | |
| 503 | ||
| 504 | #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) || defined(CONFIG_PCIE3) | |
| 505 | #define PCIE_ENV \ | |
| 506 | "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ | |
| 507 | "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ | |
| 837f1ba0 | 508 | "pcieerr=md ${a}020 1; md ${a}e00 e;" \ |
| 0cde4b00 JL |
509 | "pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ |
| 510 | "pci d.w $b.0 56 1;" \ | |
| 511 | "pci d $b.0 104 1;pci d $b.0 110 1;pci d $b.0 130 1\0" \ | |
| 512 | "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff;" \ | |
| 513 | "pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff;" \ | |
| 514 | "pci w $b.0 104 ffffffff; pci w $b.0 110 ffffffff;" \ | |
| 515 | "pci w $b.0 130 ffffffff\0" \ | |
| 516 | "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ | |
| 837f1ba0 ES |
517 | "pcie1regs=setenv a e000a; run pciereg\0" \ |
| 518 | "pcie2regs=setenv a e0009; run pciereg\0" \ | |
| 519 | "pcie3regs=setenv a e000b; run pciereg\0" \ | |
| 520 | "pcie1cfg=setenv b 3; run pciecfg\0" \ | |
| 521 | "pcie2cfg=setenv b 5; run pciecfg\0" \ | |
| 522 | "pcie3cfg=setenv b 0; run pciecfg\0" \ | |
| 523 | "pcie1err=setenv a e000a; setenv b 3; run pcieerr\0" \ | |
| 524 | "pcie2err=setenv a e0009; setenv b 5; run pcieerr\0" \ | |
| 525 | "pcie3err=setenv a e000b; setenv b 0; run pcieerr\0" \ | |
| 526 | "pcie1errc=setenv a e000a; setenv b 3; run pcieerrc\0" \ | |
| 527 | "pcie2errc=setenv a e0009; setenv b 5; run pcieerrc\0" \ | |
| 528 | "pcie3errc=setenv a e000b; setenv b 0; run pcieerrc\0" | |
| 0cde4b00 JL |
529 | #else |
| 530 | #define PCIE_ENV "" | |
| 531 | #endif | |
| 532 | ||
| 533 | #if defined(CONFIG_PCI1) | |
| 534 | #define PCI_ENV \ | |
| 535 | "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ | |
| 837f1ba0 | 536 | "echo e;md ${a}e00 9\0" \ |
| 0cde4b00 JL |
537 | "pci1regs=setenv a e0008; run pcireg\0" \ |
| 538 | "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ | |
| 539 | "pci d.w $b.0 56 1\0" \ | |
| 837f1ba0 ES |
540 | "pcierrc=mw ${a}e00 ffffffff; mw ${a}e0c 0; pci w.b $b.0 7 ff;" \ |
| 541 | "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff\0" \ | |
| 542 | "pci1err=setenv a e0008; setenv b 7; run pcierr\0" \ | |
| 543 | "pci1errc=setenv a e0008; setenv b 7; run pcierrc\0" | |
| 0cde4b00 JL |
544 | #else |
| 545 | #define PCI_ENV "" | |
| 546 | #endif | |
| 547 | ||
| 548 | #if defined(CONFIG_TSEC_ENET) | |
| 549 | #define ENET_ENV \ | |
| 550 | "enetreg1=md ${a}000 2; md ${a}010 9; md ${a}050 4; md ${a}08c 1;" \ | |
| 551 | "md ${a}098 2\0" \ | |
| 552 | "enetregt=echo t;md ${a}100 6; md ${a}140 2; md ${a}180 10; md ${a}200 10\0" \ | |
| 553 | "enetregr=echo r;md ${a}300 6; md ${a}330 5; md ${a}380 10; md ${a}400 10\0" \ | |
| 554 | "enetregm=echo mac;md ${a}500 5; md ${a}520 28;echo fifo;md ${a}a00 1;" \ | |
| 555 | "echo mib;md ${a}680 31\0" \ | |
| 556 | "enetreg=run enetreg1; run enetregm; run enetregt; run enetregr\0" \ | |
| 557 | "enet1regs=setenv a e0024; run enetreg\0" \ | |
| 558 | "enet3regs=setenv a e0026; run enetreg\0" | |
| 559 | #else | |
| 560 | #define ENET_ENV "" | |
| 561 | #endif | |
| 562 | ||
| 837f1ba0 ES |
563 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 564 | "netdev=eth0\0" \ | |
| 565 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 566 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 567 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 568 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 569 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
| 570 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
| 571 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
| 0cde4b00 JL |
572 | "consoledev=ttyS0\0" \ |
| 573 | "ramdiskaddr=2000000\0" \ | |
| 837f1ba0 ES |
574 | "ramdiskfile=8544ds/ramdisk.uboot\0" \ |
| 575 | "dtbaddr=c00000\0" \ | |
| 576 | "dtbfile=8544ds/mpc8544ds.dtb\0" \ | |
| 577 | "bdev=sda3\0" \ | |
| 578 | "eoi=mw e00400b0 0\0" \ | |
| 579 | "iack=md e00400a0 1\0" \ | |
| 0cde4b00 JL |
580 | "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4; md ${a}bf0 4;" \ |
| 581 | "md ${a}e00 3; md ${a}e20 3; md ${a}e40 7; md ${a}f00 5\0" \ | |
| 837f1ba0 | 582 | "ddrregs=setenv a e0002; run ddrreg\0" \ |
| 0cde4b00 | 583 | "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}b20 3;" \ |
| 837f1ba0 ES |
584 | "md ${a}e00 1; md ${a}e60 1; md ${a}ef0 15\0" \ |
| 585 | "guregs=setenv a e00e0; run gureg\0" \ | |
| 0cde4b00 | 586 | "ecmreg=md ${a}000 1; md ${a}010 1; md ${a}bf8 2; md ${a}e00 6\0" \ |
| 837f1ba0 ES |
587 | "ecmregs=setenv a e0001; run ecmreg\0" \ |
| 588 | "lawregs=md e0000c08 4b\0" \ | |
| 589 | "lbcregs=md e0005000 36\0" \ | |
| 590 | "dma0regs=md e0021100 12\0" \ | |
| 591 | "dma1regs=md e0021180 12\0" \ | |
| 592 | "dma2regs=md e0021200 12\0" \ | |
| 593 | "dma3regs=md e0021280 12\0" \ | |
| 594 | PCIE_ENV \ | |
| 595 | PCI_ENV \ | |
| 0cde4b00 JL |
596 | ENET_ENV |
| 597 | ||
| 598 | ||
| 599 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 600 | "setenv bootargs root=/dev/nfs rw " \ | |
| 601 | "nfsroot=$serverip:$rootpath " \ | |
| 602 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 603 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 604 | "tftp $loadaddr $bootfile;" \ | |
| 837f1ba0 ES |
605 | "tftp $dtbaddr $dtbfile;" \ |
| 606 | "bootm $loadaddr - $dtbaddr" | |
| 0cde4b00 JL |
607 | |
| 608 | ||
| 837f1ba0 | 609 | #define CONFIG_RAMBOOTCOMMAND \ |
| 0cde4b00 JL |
610 | "setenv bootargs root=/dev/ram rw " \ |
| 611 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 612 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 613 | "tftp $loadaddr $bootfile;" \ | |
| 837f1ba0 ES |
614 | "tftp $dtbaddr $dtbfile;" \ |
| 615 | "bootm $loadaddr $ramdiskaddr $dtbaddr" | |
| 0cde4b00 | 616 | |
| 837f1ba0 ES |
617 | #define CONFIG_BOOTCOMMAND \ |
| 618 | "setenv bootargs root=/dev/$bdev rw " \ | |
| 0cde4b00 JL |
619 | "console=$consoledev,$baudrate $othbootargs;" \ |
| 620 | "tftp $loadaddr $bootfile;" \ | |
| 837f1ba0 ES |
621 | "tftp $dtbaddr $dtbfile;" \ |
| 622 | "bootm $loadaddr - $dtbaddr" | |
| 0cde4b00 JL |
623 | |
| 624 | #endif /* __CONFIG_H */ |