[people/ms/u-boot.git] / include / configs / MPC8555CDS.h

/*
 * Copyright 2004, 2011 Freescale Semiconductor.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * mpc8555cds board configuration file
 *
 * Please refer to doc/README.mpc85xxcds for more info.
 *
 */
#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_CPM2		1	/* has CPM2 */

#define CONFIG_PCI_INDIRECT_BRIDGE
#define CONFIG_SYS_PCI_64BIT	1	/* enable 64-bit PCI resources */
#define CONFIG_TSEC_ENET		/* tsec ethernet support */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_FSL_VIA

#ifndef __ASSEMBLY__
extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_SYS_CLK_FREQ	get_clock_freq() /* sysclk for MPC85xx */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE			    /* toggle L2 cache	*/
#define CONFIG_BTB			    /* toggle branch predition */

#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest works on */
#define CONFIG_SYS_MEMTEST_END		0x00400000

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */

/* Make sure required options are set */
#ifndef CONFIG_SPD_EEPROM
#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
#endif

#undef CONFIG_CLOCKS_IN_MHZ

/*
 * Local Bus Definitions
 */

/*
 * FLASH on the Local Bus
 * Two banks, 8M each, using the CFI driver.
 * Boot from BR0/OR0 bank at 0xff00_0000
 * Alternate BR1/OR1 bank at 0xff80_0000
 *
 * BR0, BR1:
 *    Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
 *    Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
 *    Port Size = 16 bits = BRx[19:20] = 10
 *    Use GPCM = BRx[24:26] = 000
 *    Valid = BRx[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001    BR0
 * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001    BR1
 *
 * OR0, OR1:
 *    Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
 *    Reserved ORx[17:18] = 11, confusion here?
 *    CSNT = ORx[20] = 1
 *    ACS = half cycle delay = ORx[21:22] = 11
 *    SCY = 6 = ORx[24:27] = 0110
 *    TRLX = use relaxed timing = ORx[29] = 1
 *    EAD = use external address latch delay = OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65    ORx
 */

#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 8M */

#define CONFIG_SYS_BR0_PRELIM		0xff801001
#define CONFIG_SYS_BR1_PRELIM		0xff001001

#define	CONFIG_SYS_OR0_PRELIM		0xff806e65
#define	CONFIG_SYS_OR1_PRELIM		0xff806e65

#define CONFIG_SYS_FLASH_BANKS_LIST	{0xff800000, CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS	2		/* number of banks */
#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Flash Erase Timeout (ms) */
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Flash Write Timeout (ms) */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

/*
 * SDRAM on the Local Bus
 */
#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */

/*
 * Base Register 2 and Option Register 2 configure SDRAM.
 * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
 *
 * For BR2, need:
 *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
 *    port-size = 32-bits = BR2[19:20] = 11
 *    no parity checking = BR2[21:22] = 00
 *    SDRAM for MSEL = BR2[24:26] = 011
 *    Valid = BR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
 *
 * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
 * FIXME: the top 17 bits of BR2.
 */

#define CONFIG_SYS_BR2_PRELIM          0xf0001861

/*
 * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
 *
 * For OR2, need:
 *    64MB mask for AM, OR2[0:7] = 1111 1100
 *		   XAM, OR2[17:18] = 11
 *    9 columns OR2[19-21] = 010
 *    13 rows   OR2[23-25] = 100
 *    EAD set for extra time OR[31] = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
 */

#define CONFIG_SYS_OR2_PRELIM		0xfc006901

#define CONFIG_SYS_LBC_LCRR		0x00030004    /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR		0x00000000    /* LB config reg */
#define CONFIG_SYS_LBC_LSRT		0x20000000  /* LB sdram refresh timer */
#define CONFIG_SYS_LBC_MRTPR		0x00000000  /* LB refresh timer prescal*/

/*
 * Common settings for all Local Bus SDRAM commands.
 * At run time, either BSMA1516 (for CPU 1.1)
 *                  or BSMA1617 (for CPU 1.0) (old)
 * is OR'ed in too.
 */
#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
				| LSDMR_PRETOACT7	\
				| LSDMR_ACTTORW7	\
				| LSDMR_BL8		\
				| LSDMR_WRC4		\
				| LSDMR_CL3		\
				| LSDMR_RFEN		\
				)

/*
 * The CADMUS registers are connected to CS3 on CDS.
 * The new memory map places CADMUS at 0xf8000000.
 *
 * For BR3, need:
 *    Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
 *    port-size = 8-bits  = BR[19:20] = 01
 *    no parity checking  = BR[21:22] = 00
 *    GPMC for MSEL       = BR[24:26] = 000
 *    Valid               = BR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
 *
 * For OR3, need:
 *    1 MB mask for AM,   OR[0:16]  = 1111 1111 1111 0000 0
 *    disable buffer ctrl OR[19]    = 0
 *    CSNT                OR[20]    = 1
 *    ACS                 OR[21:22] = 11
 *    XACS                OR[23]    = 1
 *    SCY 15 wait states  OR[24:27] = 1111	max is suboptimal but safe
 *    SETA                OR[28]    = 0
 *    TRLX                OR[29]    = 1
 *    EHTR                OR[30]    = 1
 *    EAD extra time      OR[31]    = 1
 *
 * 0    4    8    12   16   20   24   28
 * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
 */

#define CONFIG_FSL_CADMUS

#define CADMUS_BASE_ADDR 0xf8000000
#define CONFIG_SYS_BR3_PRELIM   0xf8000801
#define CONFIG_SYS_OR3_PRELIM   0xfff00ff7

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000	    /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024) /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     2
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE    1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}

#define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2        (CONFIG_SYS_CCSRBAR+0x4600)

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }

/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_CCID
#define CONFIG_SYS_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2

/*
 * General PCI
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */

#define CONFIG_SYS_PCI2_MEM_VIRT	0xa0000000
#define CONFIG_SYS_PCI2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	0xa0000000
#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI2_IO_VIRT	0xe2100000
#define CONFIG_SYS_PCI2_IO_BUS	0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS	0xe2100000
#define CONFIG_SYS_PCI2_IO_SIZE	0x00100000	/* 1M */

#ifdef CONFIG_LEGACY
#define BRIDGE_ID 17
#define VIA_ID 2
#else
#define BRIDGE_ID 28
#define VIA_ID 4
#endif

#if defined(CONFIG_PCI)

#define CONFIG_MPC85XX_PCI2

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif	/* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management */
#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"
#define TSEC1_PHY_ADDR		0
#define TSEC2_PHY_ADDR		1
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT

/* Options are: TSEC[0-1] */
#define CONFIG_ETHPRIME		"TSEC0"

#endif	/* CONFIG_TSEC_ENET */

/*
 * Environment
 */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x40000)
#define CONFIG_ENV_SECT_SIZE	0x40000	/* 256K(one sector) for env */
#define CONFIG_ENV_SIZE		0x2000

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE

#undef CONFIG_WATCHDOG			/* watchdog disabled */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 64 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(64 << 20)	/* Increase max gunzip size */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*
 * Environment Configuration
 */
#if defined(CONFIG_TSEC_ENET)
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#endif

#define CONFIG_IPADDR    192.168.1.253

#define CONFIG_HOSTNAME  unknown
#define CONFIG_ROOTPATH  "/nfsroot"
#define CONFIG_BOOTFILE  "your.uImage"

#define CONFIG_SERVERIP  192.168.1.1
#define CONFIG_GATEWAYIP 192.168.1.1
#define CONFIG_NETMASK   255.255.255.0

#define CONFIG_LOADADDR  200000   /*default location for tftp and bootm*/

#define	CONFIG_EXTRA_ENV_SETTINGS				        \
   "netdev=eth0\0"                                                      \
   "consoledev=ttyS1\0"                                                 \
   "ramdiskaddr=600000\0"                                               \
   "ramdiskfile=your.ramdisk.u-boot\0"					\
   "fdtaddr=400000\0"							\
   "fdtfile=your.fdt.dtb\0"

#define CONFIG_NFSBOOTCOMMAND	                                        \
   "setenv bootargs root=/dev/nfs rw "                                  \
      "nfsroot=$serverip:$rootpath "                                    \
      "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $loadaddr $bootfile;"                                          \
   "tftp $fdtaddr $fdtfile;"						\
   "bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND \
   "setenv bootargs root=/dev/ram rw "                                  \
      "console=$consoledev,$baudrate $othbootargs;"                     \
   "tftp $ramdiskaddr $ramdiskfile;"                                    \
   "tftp $loadaddr $bootfile;"                                          \
   "bootm $loadaddr $ramdiskaddr"

#define CONFIG_BOOTCOMMAND  CONFIG_NFSBOOTCOMMAND

#endif	/* __CONFIG_H */
Commit	Line	Data
03f5c550	1	/*
7c57f3e8	2	* Copyright 2004, 2011 Freescale Semiconductor.
03f5c550	3	*
3765b3e7	4	* SPDX-License-Identifier: GPL-2.0+
03f5c550 WD	5	*/
	6
	7	/*
	8	* mpc8555cds board configuration file
	9	*
	10	* Please refer to doc/README.mpc85xxcds for more info.
	11	*
	12	*/
03f5c550 WD	13	#ifndef __CONFIG_H
	14	#define __CONFIG_H
	15
	16	/* High Level Configuration Options */
9c4c5ae3	17	#define CONFIG_CPM2 1 /* has CPM2 */
03f5c550	18
842033e6	19	#define CONFIG_PCI_INDIRECT_BRIDGE
0151cbac	20	#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
53677ef1	21	#define CONFIG_TSEC_ENET /* tsec ethernet support */
03f5c550	22	#define CONFIG_ENV_OVERWRITE
03f5c550	23
25eedb2c	24	#define CONFIG_FSL_VIA
e8d18541	25
03f5c550 WD	26	#ifndef __ASSEMBLY__
	27	extern unsigned long get_clock_freq(void);
	28	#endif
	29	#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
	30
	31	/*
	32	* These can be toggled for performance analysis, otherwise use default.
	33	*/
53677ef1	34	#define CONFIG_L2_CACHE /* toggle L2 cache */
03f5c550	35	#define CONFIG_BTB /* toggle branch predition */
03f5c550	36
6d0f6bcf JCPV	37	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
6d0f6bcf JCPV	38	#define CONFIG_SYS_MEMTEST_END 0x00400000
03f5c550	39
e46fedfe TT	40	#define CONFIG_SYS_CCSRBAR 0xe0000000
e46fedfe TT	41	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
03f5c550	42
2b40edb1	43	/* DDR Setup */
2b40edb1 JL	44	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	45	#define CONFIG_DDR_SPD
	46	#undef CONFIG_FSL_DDR_INTERACTIVE
	47
	48	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
	49
6d0f6bcf JCPV	50	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	51	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
03f5c550	52
2b40edb1 JL	53	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
2b40edb1 JL	54	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
03f5c550	55
2b40edb1 JL	56	/* I2C addresses of SPD EEPROMs */
	57	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
	58
	59	/* Make sure required options are set */
03f5c550 WD	60	#ifndef CONFIG_SPD_EEPROM
	61	#error ("CONFIG_SPD_EEPROM is required by MPC85555CDS")
	62	#endif
	63
7202d43d JL	64	#undef CONFIG_CLOCKS_IN_MHZ
7202d43d JL	65
03f5c550	66	/*
7202d43d	67	* Local Bus Definitions
03f5c550	68	*/
7202d43d JL	69
	70	/*
	71	* FLASH on the Local Bus
	72	* Two banks, 8M each, using the CFI driver.
	73	* Boot from BR0/OR0 bank at 0xff00_0000
	74	* Alternate BR1/OR1 bank at 0xff80_0000
	75	*
	76	* BR0, BR1:
	77	* Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
	78	* Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
	79	* Port Size = 16 bits = BRx[19:20] = 10
	80	* Use GPCM = BRx[24:26] = 000
	81	* Valid = BRx[31] = 1
	82	*
	83	* 0 4 8 12 16 20 24 28
	84	* 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
	85	* 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
	86	*
	87	* OR0, OR1:
	88	* Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
	89	* Reserved ORx[17:18] = 11, confusion here?
	90	* CSNT = ORx[20] = 1
	91	* ACS = half cycle delay = ORx[21:22] = 11
	92	* SCY = 6 = ORx[24:27] = 0110
	93	* TRLX = use relaxed timing = ORx[29] = 1
	94	* EAD = use external address latch delay = OR[31] = 1
	95	*
	96	* 0 4 8 12 16 20 24 28
	97	* 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
	98	*/
	99
6d0f6bcf	100	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 8M */
03f5c550	101
6d0f6bcf JCPV	102	#define CONFIG_SYS_BR0_PRELIM 0xff801001
6d0f6bcf JCPV	103	#define CONFIG_SYS_BR1_PRELIM 0xff001001
03f5c550	104
6d0f6bcf JCPV	105	#define CONFIG_SYS_OR0_PRELIM 0xff806e65
6d0f6bcf JCPV	106	#define CONFIG_SYS_OR1_PRELIM 0xff806e65
03f5c550	107
6d0f6bcf JCPV	108	#define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
	109	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
	110	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
	111	#undef CONFIG_SYS_FLASH_CHECKSUM
	112	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
	113	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
03f5c550	114
14d0a02a	115	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
03f5c550	116
00b1883a	117	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	118	#define CONFIG_SYS_FLASH_CFI
6d0f6bcf JCPV	119	#define CONFIG_SYS_FLASH_EMPTY_INFO
03f5c550	120
03f5c550	121	/*
7202d43d	122	* SDRAM on the Local Bus
03f5c550	123	*/
6d0f6bcf JCPV	124	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	125	#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
03f5c550 WD	126
	127	/*
	128	* Base Register 2 and Option Register 2 configure SDRAM.
6d0f6bcf	129	* The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
03f5c550 WD	130	*
	131	* For BR2, need:
	132	* Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
	133	* port-size = 32-bits = BR2[19:20] = 11
	134	* no parity checking = BR2[21:22] = 00
	135	* SDRAM for MSEL = BR2[24:26] = 011
	136	* Valid = BR[31] = 1
	137	*
	138	* 0 4 8 12 16 20 24 28
	139	* 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
	140	*
6d0f6bcf	141	* FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
03f5c550 WD	142	* FIXME: the top 17 bits of BR2.
	143	*/
	144
6d0f6bcf	145	#define CONFIG_SYS_BR2_PRELIM 0xf0001861
03f5c550 WD	146
03f5c550 WD	147	/*
6d0f6bcf	148	* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
03f5c550 WD	149	*
	150	* For OR2, need:
	151	* 64MB mask for AM, OR2[0:7] = 1111 1100
	152	* XAM, OR2[17:18] = 11
	153	* 9 columns OR2[19-21] = 010
	154	* 13 rows OR2[23-25] = 100
	155	* EAD set for extra time OR[31] = 1
	156	*
	157	* 0 4 8 12 16 20 24 28
	158	* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
	159	*/
	160
6d0f6bcf	161	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
03f5c550	162
6d0f6bcf JCPV	163	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
	164	#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
	165	#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
	166	#define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
03f5c550	167
03f5c550 WD	168	/*
	169	* Common settings for all Local Bus SDRAM commands.
	170	* At run time, either BSMA1516 (for CPU 1.1)
	171	* or BSMA1617 (for CPU 1.0) (old)
	172	* is OR'ed in too.
	173	*/
b0fe93ed KG	174	#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
	175	\| LSDMR_PRETOACT7 \
	176	\| LSDMR_ACTTORW7 \
	177	\| LSDMR_BL8 \
	178	\| LSDMR_WRC4 \
	179	\| LSDMR_CL3 \
	180	\| LSDMR_RFEN \
03f5c550 WD	181	)
	182
	183	/*
	184	* The CADMUS registers are connected to CS3 on CDS.
	185	* The new memory map places CADMUS at 0xf8000000.
	186	*
	187	* For BR3, need:
	188	* Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
	189	* port-size = 8-bits = BR[19:20] = 01
	190	* no parity checking = BR[21:22] = 00
	191	* GPMC for MSEL = BR[24:26] = 000
	192	* Valid = BR[31] = 1
	193	*
	194	* 0 4 8 12 16 20 24 28
	195	* 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
	196	*
	197	* For OR3, need:
	198	* 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
	199	* disable buffer ctrl OR[19] = 0
	200	* CSNT OR[20] = 1
	201	* ACS OR[21:22] = 11
	202	* XACS OR[23] = 1
	203	* SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
	204	* SETA OR[28] = 0
	205	* TRLX OR[29] = 1
	206	* EHTR OR[30] = 1
	207	* EAD extra time OR[31] = 1
	208	*
	209	* 0 4 8 12 16 20 24 28
	210	* 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
	211	*/
	212
25eedb2c JL	213	#define CONFIG_FSL_CADMUS
25eedb2c JL	214
03f5c550	215	#define CADMUS_BASE_ADDR 0xf8000000
6d0f6bcf JCPV	216	#define CONFIG_SYS_BR3_PRELIM 0xf8000801
6d0f6bcf JCPV	217	#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
03f5c550	218
6d0f6bcf JCPV	219	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	220	#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
553f0982	221	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
03f5c550	222
25ddd1fb	223	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	224	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
03f5c550	225
6d0f6bcf JCPV	226	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	227	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
03f5c550 WD	228
	229	/* Serial Port */
	230	#define CONFIG_CONS_INDEX 2
6d0f6bcf JCPV	231	#define CONFIG_SYS_NS16550_SERIAL
	232	#define CONFIG_SYS_NS16550_REG_SIZE 1
	233	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
03f5c550	234
6d0f6bcf	235	#define CONFIG_SYS_BAUDRATE_TABLE \
03f5c550 WD	236	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
03f5c550 WD	237
6d0f6bcf JCPV	238	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	239	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
03f5c550	240
20476726 JL	241	/*
	242	* I2C
	243	*/
00f792e0 HS	244	#define CONFIG_SYS_I2C
	245	#define CONFIG_SYS_I2C_FSL
	246	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	247	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	248	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
	249	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
03f5c550	250
e8d18541 TT	251	/* EEPROM */
e8d18541 TT	252	#define CONFIG_ID_EEPROM
6d0f6bcf JCPV	253	#define CONFIG_SYS_I2C_EEPROM_CCID
	254	#define CONFIG_SYS_ID_EEPROM
	255	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	256	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
e8d18541	257
03f5c550 WD	258	/*
	259	* General PCI
	260	* Addresses are mapped 1-1.
	261	*/
5af0fdd8	262	#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
10795f42	263	#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
5af0fdd8	264	#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
6d0f6bcf	265	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
aca5f018	266	#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
5f91ef6a	267	#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
6d0f6bcf JCPV	268	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
	269	#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
	270
5af0fdd8	271	#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
10795f42	272	#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
5af0fdd8	273	#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
6d0f6bcf	274	#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
aca5f018	275	#define CONFIG_SYS_PCI2_IO_VIRT 0xe2100000
5f91ef6a	276	#define CONFIG_SYS_PCI2_IO_BUS 0x00000000
6d0f6bcf JCPV	277	#define CONFIG_SYS_PCI2_IO_PHYS 0xe2100000
6d0f6bcf JCPV	278	#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
03f5c550	279
7f3f2bd2 RV	280	#ifdef CONFIG_LEGACY
	281	#define BRIDGE_ID 17
	282	#define VIA_ID 2
	283	#else
	284	#define BRIDGE_ID 28
	285	#define VIA_ID 4
	286	#endif
03f5c550 WD	287
	288	#if defined(CONFIG_PCI)
	289
bf1dfffd	290	#define CONFIG_MPC85XX_PCI2
03f5c550 WD	291
	292	#undef CONFIG_EEPRO100
	293	#undef CONFIG_TULIP
	294
bf1dfffd	295	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	296	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
03f5c550 WD	297
	298	#endif /* CONFIG_PCI */
	299
03f5c550 WD	300	#if defined(CONFIG_TSEC_ENET)
03f5c550 WD	301
03f5c550	302	#define CONFIG_MII 1 /* MII PHY management */
255a3577 KP	303	#define CONFIG_TSEC1 1
	304	#define CONFIG_TSEC1_NAME "TSEC0"
	305	#define CONFIG_TSEC2 1
	306	#define CONFIG_TSEC2_NAME "TSEC1"
03f5c550 WD	307	#define TSEC1_PHY_ADDR 0
03f5c550 WD	308	#define TSEC2_PHY_ADDR 1
03f5c550 WD	309	#define TSEC1_PHYIDX 0
03f5c550 WD	310	#define TSEC2_PHYIDX 0
3a79013e AF	311	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	312	#define TSEC2_FLAGS TSEC_GIGABIT
d9b94f28 JL	313
	314	/* Options are: TSEC[0-1] */
	315	#define CONFIG_ETHPRIME "TSEC0"
03f5c550 WD	316
	317	#endif /* CONFIG_TSEC_ENET */
	318
03f5c550 WD	319	/*
	320	* Environment
	321	*/
6d0f6bcf	322	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
0e8d1586 JCPV	323	#define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
0e8d1586 JCPV	324	#define CONFIG_ENV_SIZE 0x2000
03f5c550 WD	325
03f5c550 WD	326	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	327	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
03f5c550	328
659e2f67 JL	329	/*
	330	* BOOTP options
	331	*/
	332	#define CONFIG_BOOTP_BOOTFILESIZE
659e2f67	333
03f5c550 WD	334	#undef CONFIG_WATCHDOG /* watchdog disabled */
	335
	336	/*
	337	* Miscellaneous configurable options
	338	*/
6d0f6bcf	339	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
03f5c550 WD	340
	341	/*
	342	* For booting Linux, the board info and command line data
a832ac41	343	* have to be in the first 64 MB of memory, since this is
03f5c550 WD	344	* the maximum mapped by the Linux kernel during initialization.
03f5c550 WD	345	*/
a832ac41 KG	346	#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
a832ac41 KG	347	#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
03f5c550	348
2835e518	349	#if defined(CONFIG_CMD_KGDB)
03f5c550	350	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
03f5c550 WD	351	#endif
03f5c550 WD	352
03f5c550 WD	353	/*
	354	* Environment Configuration
	355	*/
03f5c550	356	#if defined(CONFIG_TSEC_ENET)
10327dc5	357	#define CONFIG_HAS_ETH0
e2ffd59b	358	#define CONFIG_HAS_ETH1
e2ffd59b	359	#define CONFIG_HAS_ETH2
03f5c550 WD	360	#endif
	361
	362	#define CONFIG_IPADDR 192.168.1.253
	363
	364	#define CONFIG_HOSTNAME unknown
8b3637c6	365	#define CONFIG_ROOTPATH "/nfsroot"
b3f44c21	366	#define CONFIG_BOOTFILE "your.uImage"
03f5c550 WD	367
	368	#define CONFIG_SERVERIP 192.168.1.1
	369	#define CONFIG_GATEWAYIP 192.168.1.1
	370	#define CONFIG_NETMASK 255.255.255.0
	371
	372	#define CONFIG_LOADADDR 200000 /default location for tftp and bootm/
	373
03f5c550 WD	374	#define CONFIG_EXTRA_ENV_SETTINGS \
	375	"netdev=eth0\0" \
	376	"consoledev=ttyS1\0" \
8272dc2f AF	377	"ramdiskaddr=600000\0" \
	378	"ramdiskfile=your.ramdisk.u-boot\0" \
	379	"fdtaddr=400000\0" \
	380	"fdtfile=your.fdt.dtb\0"
03f5c550 WD	381
	382	#define CONFIG_NFSBOOTCOMMAND \
	383	"setenv bootargs root=/dev/nfs rw " \
	384	"nfsroot=$serverip:$rootpath " \
	385	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	386	"console=$consoledev,$baudrate $othbootargs;" \
	387	"tftp $loadaddr $bootfile;" \
8272dc2f AF	388	"tftp $fdtaddr $fdtfile;" \
8272dc2f AF	389	"bootm $loadaddr - $fdtaddr"
03f5c550 WD	390
	391	#define CONFIG_RAMBOOTCOMMAND \
	392	"setenv bootargs root=/dev/ram rw " \
	393	"console=$consoledev,$baudrate $othbootargs;" \
	394	"tftp $ramdiskaddr $ramdiskfile;" \
	395	"tftp $loadaddr $bootfile;" \
	396	"bootm $loadaddr $ramdiskaddr"
	397
	398	#define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
	399
03f5c550	400	#endif /* __CONFIG_H */