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Commit | Line | Data |
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765547dc | 1 | /* |
e5fe96b1 | 2 | * Copyright 2009-2011 Freescale Semiconductor, Inc. |
765547dc | 3 | * |
3765b3e7 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
765547dc HW |
5 | */ |
6 | ||
7 | /* | |
8 | * mpc8569mds board configuration file | |
9 | */ | |
10 | #ifndef __CONFIG_H | |
11 | #define __CONFIG_H | |
12 | ||
13 | /* High Level Configuration Options */ | |
14 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
15 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
765547dc HW |
16 | #define CONFIG_MPC8569 1 /* MPC8569 specific */ |
17 | #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ | |
18 | ||
19 | #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ | |
20 | ||
e5fe96b1 KG |
21 | #define CONFIG_SYS_SRIO |
22 | #define CONFIG_SRIO1 /* SRIO port 1 */ | |
23 | ||
765547dc HW |
24 | #define CONFIG_PCIE1 1 /* PCIE controller */ |
25 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ | |
842033e6 | 26 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
765547dc HW |
27 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ |
28 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
29 | #define CONFIG_QE /* Enable QE */ | |
30 | #define CONFIG_ENV_OVERWRITE | |
31 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
32 | ||
765547dc HW |
33 | #ifndef __ASSEMBLY__ |
34 | extern unsigned long get_clock_freq(void); | |
35 | #endif | |
36 | /* Replace a call to get_clock_freq (after it is implemented)*/ | |
67351049 DL |
37 | #define CONFIG_SYS_CLK_FREQ 66666666 |
38 | #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
765547dc | 39 | |
d24f2d32 | 40 | #ifdef CONFIG_ATM |
c95d541e LY |
41 | #define CONFIG_PQ_MDS_PIB |
42 | #define CONFIG_PQ_MDS_PIB_ATM | |
43 | #endif | |
44 | ||
765547dc HW |
45 | /* |
46 | * These can be toggled for performance analysis, otherwise use default. | |
47 | */ | |
48 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
49 | #define CONFIG_BTB /* toggle branch predition */ | |
50 | ||
2ae18241 WD |
51 | #ifndef CONFIG_SYS_TEXT_BASE |
52 | #define CONFIG_SYS_TEXT_BASE 0xfff80000 | |
674ef7bd LY |
53 | #endif |
54 | ||
96196a1f HW |
55 | #ifndef CONFIG_SYS_MONITOR_BASE |
56 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
57 | #endif | |
58 | ||
765547dc HW |
59 | /* |
60 | * Only possible on E500 Version 2 or newer cores. | |
61 | */ | |
62 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
63 | ||
64 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
3aed5507 | 65 | #define CONFIG_BOARD_EARLY_INIT_R 1 |
7f52ed5e | 66 | #define CONFIG_HWCONFIG |
765547dc HW |
67 | |
68 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
69 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
70 | ||
674ef7bd LY |
71 | /* |
72 | * Config the L2 Cache as L2 SRAM | |
73 | */ | |
74 | #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 | |
75 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
76 | #define CONFIG_SYS_L2_SIZE (512 << 10) | |
77 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
78 | ||
e46fedfe TT |
79 | #define CONFIG_SYS_CCSRBAR 0xe0000000 |
80 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
765547dc | 81 | |
8d22ddca | 82 | #if defined(CONFIG_NAND_SPL) |
e46fedfe | 83 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
674ef7bd LY |
84 | #endif |
85 | ||
765547dc | 86 | /* DDR Setup */ |
5614e71b | 87 | #define CONFIG_SYS_FSL_DDR3 |
765547dc HW |
88 | #undef CONFIG_FSL_DDR_INTERACTIVE |
89 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
90 | #define CONFIG_DDR_SPD | |
765547dc HW |
91 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ |
92 | ||
93 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
94 | ||
95 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
96 | /* DDR is system memory*/ | |
97 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
98 | ||
99 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
100 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
101 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
102 | ||
103 | /* I2C addresses of SPD EEPROMs */ | |
c39f44dc | 104 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
765547dc HW |
105 | |
106 | /* These are used when DDR doesn't use SPD. */ | |
107 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ | |
108 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
109 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
110 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
111 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
112 | #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 | |
113 | #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 | |
114 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 | |
115 | #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 | |
116 | #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 | |
117 | #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 | |
118 | #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 | |
119 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
120 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 | |
121 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
122 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
123 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
124 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 | |
125 | #define CONFIG_SYS_DDR_CDR_1 0x80040000 | |
126 | #define CONFIG_SYS_DDR_CDR_2 0x00000000 | |
127 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
128 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
129 | #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ | |
130 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
131 | ||
132 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
133 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
134 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
135 | ||
136 | #undef CONFIG_CLOCKS_IN_MHZ | |
137 | ||
138 | /* | |
139 | * Local Bus Definitions | |
140 | */ | |
141 | ||
142 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ | |
143 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
144 | ||
145 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 | |
146 | #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE | |
147 | ||
148 | /*Chip select 0 - Flash*/ | |
674ef7bd LY |
149 | #define CONFIG_FLASH_BR_PRELIM 0xfe000801 |
150 | #define CONFIG_FLASH_OR_PRELIM 0xfe000ff7 | |
765547dc | 151 | |
399b53cb | 152 | /*Chip select 1 - BCSR*/ |
765547dc HW |
153 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
154 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 | |
155 | ||
399b53cb HW |
156 | /*Chip select 4 - PIB*/ |
157 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 | |
158 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 | |
159 | ||
160 | /*Chip select 5 - PIB*/ | |
161 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 | |
162 | #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 | |
163 | ||
765547dc HW |
164 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
165 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
166 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
167 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
168 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
169 | ||
674ef7bd | 170 | #undef CONFIG_SYS_RAMBOOT |
674ef7bd | 171 | |
765547dc HW |
172 | #define CONFIG_FLASH_CFI_DRIVER |
173 | #define CONFIG_SYS_FLASH_CFI | |
174 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
175 | ||
a29155e1 | 176 | /* Chip select 3 - NAND */ |
674ef7bd | 177 | #ifndef CONFIG_NAND_SPL |
a29155e1 | 178 | #define CONFIG_SYS_NAND_BASE 0xFC000000 |
674ef7bd LY |
179 | #else |
180 | #define CONFIG_SYS_NAND_BASE 0xFFF00000 | |
181 | #endif | |
182 | ||
183 | /* NAND boot: 4K NAND loader config */ | |
184 | #define CONFIG_SYS_NAND_SPL_SIZE 0x1000 | |
185 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
186 | #define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR) | |
187 | #define CONFIG_SYS_NAND_U_BOOT_START \ | |
188 | (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE) | |
189 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (0) | |
190 | #define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000) | |
191 | #define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
192 | ||
a29155e1 AV |
193 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE |
194 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } | |
195 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
a29155e1 AV |
196 | #define CONFIG_CMD_NAND 1 |
197 | #define CONFIG_NAND_FSL_ELBC 1 | |
198 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
a3055c58 | 199 | #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ |
a29155e1 AV |
200 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
201 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
202 | | BR_MS_FCM /* MSEL = FCM */ \ | |
203 | | BR_V) /* valid */ | |
a3055c58 | 204 | #define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ |
a29155e1 AV |
205 | | OR_FCM_CSCT \ |
206 | | OR_FCM_CST \ | |
207 | | OR_FCM_CHT \ | |
208 | | OR_FCM_SCY_1 \ | |
209 | | OR_FCM_TRLX \ | |
210 | | OR_FCM_EHTR) | |
674ef7bd | 211 | |
674ef7bd LY |
212 | #define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */ |
213 | #define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */ | |
a3055c58 MM |
214 | #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */ |
215 | #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ | |
765547dc | 216 | |
765547dc HW |
217 | #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ |
218 | #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ | |
219 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
220 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
221 | ||
222 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
223 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
553f0982 | 224 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
765547dc | 225 | |
765547dc | 226 | #define CONFIG_SYS_GBL_DATA_OFFSET \ |
25ddd1fb | 227 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
765547dc HW |
228 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
229 | ||
230 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
fb279490 | 231 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
765547dc HW |
232 | |
233 | /* Serial Port */ | |
234 | #define CONFIG_CONS_INDEX 1 | |
765547dc HW |
235 | #define CONFIG_SYS_NS16550_SERIAL |
236 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
237 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
93341909 KG |
238 | #ifdef CONFIG_NAND_SPL |
239 | #define CONFIG_NS16550_MIN_FUNCTIONS | |
240 | #endif | |
765547dc HW |
241 | |
242 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
243 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
244 | ||
245 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
246 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
247 | ||
765547dc HW |
248 | /* |
249 | * I2C | |
250 | */ | |
00f792e0 HS |
251 | #define CONFIG_SYS_I2C |
252 | #define CONFIG_SYS_I2C_FSL | |
253 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
254 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
255 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
256 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
257 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
258 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
259 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
765547dc HW |
260 | |
261 | /* | |
262 | * I2C2 EEPROM | |
263 | */ | |
264 | #define CONFIG_ID_EEPROM | |
265 | #ifdef CONFIG_ID_EEPROM | |
266 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
267 | #endif | |
268 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
269 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
270 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
271 | ||
272 | #define PLPPAR1_I2C_BIT_MASK 0x0000000F | |
273 | #define PLPPAR1_I2C2_VAL 0x00000000 | |
7f52ed5e | 274 | #define PLPPAR1_ESDHC_VAL 0x0000000A |
765547dc HW |
275 | #define PLPDIR1_I2C_BIT_MASK 0x0000000F |
276 | #define PLPDIR1_I2C2_VAL 0x0000000F | |
7f52ed5e | 277 | #define PLPDIR1_ESDHC_VAL 0x00000006 |
c4ca10f1 AV |
278 | #define PLPPAR1_UART0_BIT_MASK 0x00000fc0 |
279 | #define PLPPAR1_ESDHC_4BITS_VAL 0x00000a80 | |
280 | #define PLPDIR1_UART0_BIT_MASK 0x00000fc0 | |
281 | #define PLPDIR1_ESDHC_4BITS_VAL 0x00000a80 | |
765547dc HW |
282 | |
283 | /* | |
284 | * General PCI | |
285 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 | |
286 | */ | |
94f2bc48 | 287 | #define CONFIG_SYS_PCIE1_NAME "Slot" |
765547dc HW |
288 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 |
289 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
290 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
291 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
292 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 | |
293 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
294 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
295 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
296 | ||
e5fe96b1 KG |
297 | #define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 |
298 | #define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 | |
299 | #define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS | |
300 | #define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ | |
765547dc HW |
301 | |
302 | #ifdef CONFIG_QE | |
303 | /* | |
304 | * QE UEC ethernet configuration | |
305 | */ | |
f82107f6 HW |
306 | #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ |
307 | #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ | |
765547dc HW |
308 | |
309 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
310 | #define CONFIG_UEC_ETH | |
78b7a8ef | 311 | #define CONFIG_ETHPRIME "UEC0" |
765547dc HW |
312 | #define CONFIG_PHY_MODE_NEED_CHANGE |
313 | ||
314 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
315 | #define CONFIG_HAS_ETH0 | |
316 | ||
317 | #ifdef CONFIG_UEC_ETH1 | |
318 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
319 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
f82107f6 | 320 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
765547dc HW |
321 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 |
322 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
323 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 | |
865ff856 | 324 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 325 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 |
f82107f6 HW |
326 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
327 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
328 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
329 | #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ | |
865ff856 | 330 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 331 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 |
f82107f6 HW |
332 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
333 | #endif /* CONFIG_UEC_ETH1 */ | |
765547dc HW |
334 | |
335 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
336 | #define CONFIG_HAS_ETH1 | |
337 | ||
338 | #ifdef CONFIG_UEC_ETH2 | |
339 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ | |
340 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
f82107f6 | 341 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
765547dc HW |
342 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 |
343 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
344 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
865ff856 | 345 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 346 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 |
f82107f6 HW |
347 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
348 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ | |
349 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
350 | #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ | |
865ff856 | 351 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 352 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 |
f82107f6 HW |
353 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
354 | #endif /* CONFIG_UEC_ETH2 */ | |
765547dc | 355 | |
750098d3 HW |
356 | #define CONFIG_UEC_ETH3 /* GETH3 */ |
357 | #define CONFIG_HAS_ETH2 | |
358 | ||
359 | #ifdef CONFIG_UEC_ETH3 | |
360 | #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ | |
361 | #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE | |
f82107f6 | 362 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
750098d3 HW |
363 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 |
364 | #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH | |
365 | #define CONFIG_SYS_UEC3_PHY_ADDR 2 | |
865ff856 | 366 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 367 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 |
f82107f6 HW |
368 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
369 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ | |
370 | #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH | |
371 | #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ | |
865ff856 | 372 | #define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 373 | #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 |
f82107f6 HW |
374 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
375 | #endif /* CONFIG_UEC_ETH3 */ | |
750098d3 HW |
376 | |
377 | #define CONFIG_UEC_ETH4 /* GETH4 */ | |
378 | #define CONFIG_HAS_ETH3 | |
379 | ||
380 | #ifdef CONFIG_UEC_ETH4 | |
381 | #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ | |
382 | #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE | |
f82107f6 | 383 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
750098d3 HW |
384 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 |
385 | #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH | |
386 | #define CONFIG_SYS_UEC4_PHY_ADDR 3 | |
865ff856 | 387 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID |
582c55a0 | 388 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 |
f82107f6 HW |
389 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
390 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
391 | #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH | |
392 | #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ | |
865ff856 | 393 | #define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII |
582c55a0 | 394 | #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 |
f82107f6 HW |
395 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ |
396 | #endif /* CONFIG_UEC_ETH4 */ | |
3bd8e532 HW |
397 | |
398 | #undef CONFIG_UEC_ETH6 /* GETH6 */ | |
399 | #define CONFIG_HAS_ETH5 | |
400 | ||
401 | #ifdef CONFIG_UEC_ETH6 | |
402 | #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ | |
403 | #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE | |
404 | #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE | |
405 | #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH | |
406 | #define CONFIG_SYS_UEC6_PHY_ADDR 4 | |
865ff856 | 407 | #define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
582c55a0 | 408 | #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 |
3bd8e532 HW |
409 | #endif /* CONFIG_UEC_ETH6 */ |
410 | ||
411 | #undef CONFIG_UEC_ETH8 /* GETH8 */ | |
412 | #define CONFIG_HAS_ETH7 | |
413 | ||
414 | #ifdef CONFIG_UEC_ETH8 | |
415 | #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ | |
416 | #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE | |
417 | #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE | |
418 | #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH | |
419 | #define CONFIG_SYS_UEC8_PHY_ADDR 6 | |
865ff856 | 420 | #define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII |
582c55a0 | 421 | #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 |
3bd8e532 HW |
422 | #endif /* CONFIG_UEC_ETH8 */ |
423 | ||
765547dc HW |
424 | #endif /* CONFIG_QE */ |
425 | ||
426 | #if defined(CONFIG_PCI) | |
427 | ||
765547dc HW |
428 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
429 | ||
430 | #undef CONFIG_EEPRO100 | |
431 | #undef CONFIG_TULIP | |
432 | ||
433 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
434 | ||
435 | #endif /* CONFIG_PCI */ | |
436 | ||
765547dc HW |
437 | /* |
438 | * Environment | |
439 | */ | |
674ef7bd | 440 | #if defined(CONFIG_SYS_RAMBOOT) |
674ef7bd | 441 | #else |
765547dc | 442 | #define CONFIG_ENV_IS_IN_FLASH 1 |
fb279490 | 443 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
1b8e4fa1 HW |
444 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ |
445 | #define CONFIG_ENV_SIZE 0x2000 | |
674ef7bd | 446 | #endif |
765547dc HW |
447 | |
448 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
449 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
450 | ||
451 | /* QE microcode/firmware address */ | |
f2717b47 | 452 | #define CONFIG_SYS_QE_FMAN_FW_IN_NOR |
dcf1d774 | 453 | #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 |
765547dc HW |
454 | |
455 | /* | |
456 | * BOOTP options | |
457 | */ | |
458 | #define CONFIG_BOOTP_BOOTFILESIZE | |
459 | #define CONFIG_BOOTP_BOOTPATH | |
460 | #define CONFIG_BOOTP_GATEWAY | |
461 | #define CONFIG_BOOTP_HOSTNAME | |
462 | ||
765547dc HW |
463 | /* |
464 | * Command line configuration. | |
465 | */ | |
765547dc | 466 | #define CONFIG_CMD_IRQ |
199e262e | 467 | #define CONFIG_CMD_REGINFO |
765547dc HW |
468 | |
469 | #if defined(CONFIG_PCI) | |
470 | #define CONFIG_CMD_PCI | |
471 | #endif | |
472 | ||
765547dc HW |
473 | #undef CONFIG_WATCHDOG /* watchdog disabled */ |
474 | ||
7f52ed5e AV |
475 | #define CONFIG_MMC 1 |
476 | ||
477 | #ifdef CONFIG_MMC | |
478 | #define CONFIG_FSL_ESDHC | |
a6da8b81 | 479 | #define CONFIG_FSL_ESDHC_PIN_MUX |
7f52ed5e | 480 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
7f52ed5e | 481 | #define CONFIG_GENERIC_MMC |
7f52ed5e AV |
482 | #define CONFIG_DOS_PARTITION |
483 | #endif | |
484 | ||
765547dc HW |
485 | /* |
486 | * Miscellaneous configurable options | |
487 | */ | |
5be58f5f KP |
488 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
489 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
490 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
765547dc | 491 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
765547dc HW |
492 | #if defined(CONFIG_CMD_KGDB) |
493 | #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ | |
494 | #else | |
495 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
496 | #endif | |
497 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
498 | /* Print Buffer Size */ | |
499 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
500 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
501 | /* Boot Argument Buffer Size */ | |
765547dc HW |
502 | |
503 | /* | |
504 | * For booting Linux, the board info and command line data | |
a832ac41 | 505 | * have to be in the first 64 MB of memory, since this is |
765547dc HW |
506 | * the maximum mapped by the Linux kernel during initialization. |
507 | */ | |
a832ac41 KG |
508 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ |
509 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
765547dc | 510 | |
765547dc HW |
511 | #if defined(CONFIG_CMD_KGDB) |
512 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
765547dc HW |
513 | #endif |
514 | ||
515 | /* | |
516 | * Environment Configuration | |
517 | */ | |
518 | #define CONFIG_HOSTNAME mpc8569mds | |
8b3637c6 | 519 | #define CONFIG_ROOTPATH "/nfsroot" |
b3f44c21 | 520 | #define CONFIG_BOOTFILE "your.uImage" |
765547dc HW |
521 | |
522 | #define CONFIG_SERVERIP 192.168.1.1 | |
523 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
524 | #define CONFIG_NETMASK 255.255.255.0 | |
525 | ||
526 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
527 | ||
765547dc HW |
528 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ |
529 | ||
530 | #define CONFIG_BAUDRATE 115200 | |
531 | ||
532 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
533 | "netdev=eth0\0" \ | |
534 | "consoledev=ttyS0\0" \ | |
535 | "ramdiskaddr=600000\0" \ | |
536 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
537 | "fdtaddr=400000\0" \ | |
538 | "fdtfile=your.fdt.dtb\0" \ | |
539 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
540 | "nfsroot=$serverip:$rootpath " \ | |
541 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
542 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
543 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
544 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
545 | ||
546 | #define CONFIG_NFSBOOTCOMMAND \ | |
547 | "run nfsargs;" \ | |
548 | "tftp $loadaddr $bootfile;" \ | |
549 | "tftp $fdtaddr $fdtfile;" \ | |
550 | "bootm $loadaddr - $fdtaddr" | |
551 | ||
552 | #define CONFIG_RAMBOOTCOMMAND \ | |
553 | "run ramargs;" \ | |
554 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
555 | "tftp $loadaddr $bootfile;" \ | |
556 | "bootm $loadaddr $ramdiskaddr" | |
557 | ||
558 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
559 | ||
560 | #endif /* __CONFIG_H */ |