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765547dc | 1 | /* |
4c2e3da8 | 2 | * Copyright (C) 2009 Freescale Semiconductor, Inc. |
765547dc HW |
3 | * |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8569mds board configuration file | |
25 | */ | |
26 | #ifndef __CONFIG_H | |
27 | #define __CONFIG_H | |
28 | ||
29 | /* High Level Configuration Options */ | |
30 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
31 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
32 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48/68 */ | |
33 | #define CONFIG_MPC8569 1 /* MPC8569 specific */ | |
34 | #define CONFIG_MPC8569MDS 1 /* MPC8569MDS board specific */ | |
35 | ||
36 | #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ | |
37 | ||
38 | #define CONFIG_PCI 1 /* Disable PCI/PCIE */ | |
39 | #define CONFIG_PCIE1 1 /* PCIE controller */ | |
40 | #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ | |
41 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
42 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ | |
43 | #define CONFIG_QE /* Enable QE */ | |
44 | #define CONFIG_ENV_OVERWRITE | |
45 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
46 | ||
765547dc HW |
47 | #ifndef __ASSEMBLY__ |
48 | extern unsigned long get_clock_freq(void); | |
49 | #endif | |
50 | /* Replace a call to get_clock_freq (after it is implemented)*/ | |
67351049 DL |
51 | #define CONFIG_SYS_CLK_FREQ 66666666 |
52 | #define CONFIG_DDR_CLK_FREQ CONFIG_SYS_CLK_FREQ | |
765547dc HW |
53 | |
54 | /* | |
55 | * These can be toggled for performance analysis, otherwise use default. | |
56 | */ | |
57 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
58 | #define CONFIG_BTB /* toggle branch predition */ | |
59 | ||
60 | /* | |
61 | * Only possible on E500 Version 2 or newer cores. | |
62 | */ | |
63 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
64 | ||
65 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ | |
7f52ed5e | 66 | #define CONFIG_HWCONFIG |
765547dc HW |
67 | |
68 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ | |
69 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
70 | ||
71 | /* | |
72 | * Base addresses -- Note these are effective addresses where the | |
73 | * actual resources get mapped (not physical addresses) | |
74 | */ | |
75 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ | |
76 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ | |
77 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR | |
78 | /* physical addr of CCSRBAR */ | |
79 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR | |
80 | /* PQII uses CONFIG_SYS_IMMR */ | |
81 | ||
82 | #define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) | |
83 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) | |
84 | ||
85 | /* DDR Setup */ | |
86 | #define CONFIG_FSL_DDR3 | |
87 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
88 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
89 | #define CONFIG_DDR_SPD | |
90 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ | |
91 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
92 | ||
93 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
94 | ||
95 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
96 | /* DDR is system memory*/ | |
97 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
98 | ||
99 | #define CONFIG_NUM_DDR_CONTROLLERS 1 | |
100 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
101 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
102 | ||
103 | /* I2C addresses of SPD EEPROMs */ | |
104 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
105 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ | |
106 | ||
107 | /* These are used when DDR doesn't use SPD. */ | |
108 | #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ | |
109 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F | |
110 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 | |
111 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
112 | #define CONFIG_SYS_DDR_TIMING_0 0x00330004 | |
113 | #define CONFIG_SYS_DDR_TIMING_1 0x6F6B4644 | |
114 | #define CONFIG_SYS_DDR_TIMING_2 0x002888D0 | |
115 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x47000000 | |
116 | #define CONFIG_SYS_DDR_SDRAM_CFG_2 0x04401040 | |
117 | #define CONFIG_SYS_DDR_SDRAM_MODE 0x40401521 | |
118 | #define CONFIG_SYS_DDR_SDRAM_MODE_2 0x8000C000 | |
119 | #define CONFIG_SYS_DDR_SDRAM_INTERVAL 0x03E00000 | |
120 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
121 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x01000000 | |
122 | #define CONFIG_SYS_DDR_TIMING_4 0x00220001 | |
123 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
124 | #define CONFIG_SYS_DDR_ZQ_CNTL 0x89080600 | |
125 | #define CONFIG_SYS_DDR_WRLVL_CNTL 0x0655A604 | |
126 | #define CONFIG_SYS_DDR_CDR_1 0x80040000 | |
127 | #define CONFIG_SYS_DDR_CDR_2 0x00000000 | |
128 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
129 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
130 | #define CONFIG_SYS_DDR_CONTROL 0xc7000000 /* Type = DDR3 */ | |
131 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
132 | ||
133 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
134 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
135 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
136 | ||
137 | #undef CONFIG_CLOCKS_IN_MHZ | |
138 | ||
139 | /* | |
140 | * Local Bus Definitions | |
141 | */ | |
142 | ||
143 | #define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ | |
144 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
145 | ||
146 | #define CONFIG_SYS_BCSR_BASE 0xf8000000 | |
147 | #define CONFIG_SYS_BCSR_BASE_PHYS CONFIG_SYS_BCSR_BASE | |
148 | ||
149 | /*Chip select 0 - Flash*/ | |
150 | #define CONFIG_SYS_BR0_PRELIM 0xfe000801 | |
151 | #define CONFIG_SYS_OR0_PRELIM 0xfe000ff7 | |
152 | ||
399b53cb | 153 | /*Chip select 1 - BCSR*/ |
765547dc HW |
154 | #define CONFIG_SYS_BR1_PRELIM 0xf8000801 |
155 | #define CONFIG_SYS_OR1_PRELIM 0xffffe9f7 | |
156 | ||
399b53cb HW |
157 | /*Chip select 4 - PIB*/ |
158 | #define CONFIG_SYS_BR4_PRELIM 0xf8008801 | |
159 | #define CONFIG_SYS_OR4_PRELIM 0xffffe9f7 | |
160 | ||
161 | /*Chip select 5 - PIB*/ | |
162 | #define CONFIG_SYS_BR5_PRELIM 0xf8010801 | |
163 | #define CONFIG_SYS_OR5_PRELIM 0xffffe9f7 | |
164 | ||
765547dc HW |
165 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
166 | #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ | |
167 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
168 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
169 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
170 | ||
171 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
172 | ||
173 | #define CONFIG_FLASH_CFI_DRIVER | |
174 | #define CONFIG_SYS_FLASH_CFI | |
175 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
176 | ||
a29155e1 AV |
177 | /* Chip select 3 - NAND */ |
178 | #define CONFIG_SYS_NAND_BASE 0xFC000000 | |
179 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
180 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } | |
181 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
182 | #define CONFIG_MTD_NAND_VERIFY_WRITE 1 | |
183 | #define CONFIG_CMD_NAND 1 | |
184 | #define CONFIG_NAND_FSL_ELBC 1 | |
185 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
186 | #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | |
187 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | |
188 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
189 | | BR_MS_FCM /* MSEL = FCM */ \ | |
190 | | BR_V) /* valid */ | |
191 | #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
192 | | OR_FCM_CSCT \ | |
193 | | OR_FCM_CST \ | |
194 | | OR_FCM_CHT \ | |
195 | | OR_FCM_SCY_1 \ | |
196 | | OR_FCM_TRLX \ | |
197 | | OR_FCM_EHTR) | |
198 | #define CONFIG_SYS_BR3_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
199 | #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
765547dc HW |
200 | |
201 | /* | |
202 | * SDRAM on the LocalBus | |
203 | */ | |
204 | #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
205 | #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ | |
206 | ||
207 | #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ | |
208 | #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ | |
209 | #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
210 | #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ | |
211 | ||
212 | #define CONFIG_SYS_INIT_RAM_LOCK 1 | |
213 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
214 | #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ | |
215 | ||
216 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ | |
217 | #define CONFIG_SYS_GBL_DATA_OFFSET \ | |
218 | (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
219 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
220 | ||
221 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ | |
fb279490 | 222 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ |
765547dc HW |
223 | |
224 | /* Serial Port */ | |
225 | #define CONFIG_CONS_INDEX 1 | |
7f52ed5e | 226 | #define CONFIG_SERIAL_MULTI 1 |
765547dc HW |
227 | #undef CONFIG_SERIAL_SOFTWARE_FIFO |
228 | #define CONFIG_SYS_NS16550 | |
229 | #define CONFIG_SYS_NS16550_SERIAL | |
230 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
231 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
232 | ||
233 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
234 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
235 | ||
236 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
237 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
238 | ||
239 | /* Use the HUSH parser*/ | |
240 | #define CONFIG_SYS_HUSH_PARSER | |
241 | #ifdef CONFIG_SYS_HUSH_PARSER | |
242 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
243 | #endif | |
244 | ||
245 | /* pass open firmware flat tree */ | |
246 | #define CONFIG_OF_LIBFDT 1 | |
247 | #define CONFIG_OF_BOARD_SETUP 1 | |
248 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
249 | ||
765547dc HW |
250 | /* |
251 | * I2C | |
252 | */ | |
253 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
254 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
255 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
256 | #define CONFIG_I2C_MULTI_BUS | |
765547dc HW |
257 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
258 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
259 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ | |
260 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
261 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
262 | ||
263 | /* | |
264 | * I2C2 EEPROM | |
265 | */ | |
266 | #define CONFIG_ID_EEPROM | |
267 | #ifdef CONFIG_ID_EEPROM | |
268 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
269 | #endif | |
270 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52 | |
271 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
272 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
273 | ||
274 | #define PLPPAR1_I2C_BIT_MASK 0x0000000F | |
275 | #define PLPPAR1_I2C2_VAL 0x00000000 | |
7f52ed5e | 276 | #define PLPPAR1_ESDHC_VAL 0x0000000A |
765547dc HW |
277 | #define PLPDIR1_I2C_BIT_MASK 0x0000000F |
278 | #define PLPDIR1_I2C2_VAL 0x0000000F | |
7f52ed5e | 279 | #define PLPDIR1_ESDHC_VAL 0x00000006 |
765547dc HW |
280 | |
281 | /* | |
282 | * General PCI | |
283 | * Memory Addresses are mapped 1-1. I/O is mapped from 0 | |
284 | */ | |
285 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 | |
286 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 | |
287 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 | |
288 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
289 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 | |
290 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
291 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 | |
292 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ | |
293 | ||
294 | #define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 | |
295 | #define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 | |
296 | #define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 | |
297 | ||
298 | #ifdef CONFIG_QE | |
299 | /* | |
300 | * QE UEC ethernet configuration | |
301 | */ | |
f82107f6 HW |
302 | #define CONFIG_SYS_UCC_RGMII_MODE /* Set UCC work at RGMII by default */ |
303 | #undef CONFIG_SYS_UCC_RMII_MODE /* Set UCC work at RMII mode */ | |
765547dc HW |
304 | |
305 | #define CONFIG_MIIM_ADDRESS (CONFIG_SYS_CCSRBAR + 0x82120) | |
306 | #define CONFIG_UEC_ETH | |
307 | #define CONFIG_ETHPRIME "FSL UEC0" | |
308 | #define CONFIG_PHY_MODE_NEED_CHANGE | |
309 | ||
310 | #define CONFIG_UEC_ETH1 /* GETH1 */ | |
311 | #define CONFIG_HAS_ETH0 | |
312 | ||
313 | #ifdef CONFIG_UEC_ETH1 | |
314 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
315 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE | |
f82107f6 | 316 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
765547dc HW |
317 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 |
318 | #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH | |
319 | #define CONFIG_SYS_UEC1_PHY_ADDR 7 | |
320 | #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_1000_RGMII_ID | |
f82107f6 HW |
321 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
322 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
323 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
324 | #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ | |
325 | #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII | |
326 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ | |
327 | #endif /* CONFIG_UEC_ETH1 */ | |
765547dc HW |
328 | |
329 | #define CONFIG_UEC_ETH2 /* GETH2 */ | |
330 | #define CONFIG_HAS_ETH1 | |
331 | ||
332 | #ifdef CONFIG_UEC_ETH2 | |
333 | #define CONFIG_SYS_UEC2_UCC_NUM 1 /* UCC2 */ | |
334 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE | |
f82107f6 | 335 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
765547dc HW |
336 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 |
337 | #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH | |
338 | #define CONFIG_SYS_UEC2_PHY_ADDR 1 | |
339 | #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_1000_RGMII_ID | |
f82107f6 HW |
340 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
341 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ | |
342 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
343 | #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ | |
344 | #define CONFIG_SYS_UEC2_INTERFACE_MODE ENET_100_RMII | |
345 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ | |
346 | #endif /* CONFIG_UEC_ETH2 */ | |
765547dc | 347 | |
750098d3 HW |
348 | #define CONFIG_UEC_ETH3 /* GETH3 */ |
349 | #define CONFIG_HAS_ETH2 | |
350 | ||
351 | #ifdef CONFIG_UEC_ETH3 | |
352 | #define CONFIG_SYS_UEC3_UCC_NUM 2 /* UCC3 */ | |
353 | #define CONFIG_SYS_UEC3_RX_CLK QE_CLK_NONE | |
f82107f6 | 354 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
750098d3 HW |
355 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 |
356 | #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH | |
357 | #define CONFIG_SYS_UEC3_PHY_ADDR 2 | |
358 | #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_1000_RGMII_ID | |
f82107f6 HW |
359 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
360 | #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ | |
361 | #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH | |
362 | #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ | |
363 | #define CONFIG_SYS_UEC3_INTERFACE_MODE ENET_100_RMII | |
364 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ | |
365 | #endif /* CONFIG_UEC_ETH3 */ | |
750098d3 HW |
366 | |
367 | #define CONFIG_UEC_ETH4 /* GETH4 */ | |
368 | #define CONFIG_HAS_ETH3 | |
369 | ||
370 | #ifdef CONFIG_UEC_ETH4 | |
371 | #define CONFIG_SYS_UEC4_UCC_NUM 3 /* UCC4 */ | |
372 | #define CONFIG_SYS_UEC4_RX_CLK QE_CLK_NONE | |
f82107f6 | 373 | #if defined(CONFIG_SYS_UCC_RGMII_MODE) |
750098d3 HW |
374 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 |
375 | #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH | |
376 | #define CONFIG_SYS_UEC4_PHY_ADDR 3 | |
377 | #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_1000_RGMII_ID | |
f82107f6 HW |
378 | #elif defined(CONFIG_SYS_UCC_RMII_MODE) |
379 | #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ | |
380 | #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH | |
381 | #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ | |
382 | #define CONFIG_SYS_UEC4_INTERFACE_MODE ENET_100_RMII | |
383 | #endif /* CONFIG_SYS_UCC_RGMII_MODE */ | |
384 | #endif /* CONFIG_UEC_ETH4 */ | |
3bd8e532 HW |
385 | |
386 | #undef CONFIG_UEC_ETH6 /* GETH6 */ | |
387 | #define CONFIG_HAS_ETH5 | |
388 | ||
389 | #ifdef CONFIG_UEC_ETH6 | |
390 | #define CONFIG_SYS_UEC6_UCC_NUM 5 /* UCC6 */ | |
391 | #define CONFIG_SYS_UEC6_RX_CLK QE_CLK_NONE | |
392 | #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE | |
393 | #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH | |
394 | #define CONFIG_SYS_UEC6_PHY_ADDR 4 | |
395 | #define CONFIG_SYS_UEC6_INTERFACE_MODE ENET_1000_SGMII | |
396 | #endif /* CONFIG_UEC_ETH6 */ | |
397 | ||
398 | #undef CONFIG_UEC_ETH8 /* GETH8 */ | |
399 | #define CONFIG_HAS_ETH7 | |
400 | ||
401 | #ifdef CONFIG_UEC_ETH8 | |
402 | #define CONFIG_SYS_UEC8_UCC_NUM 7 /* UCC8 */ | |
403 | #define CONFIG_SYS_UEC8_RX_CLK QE_CLK_NONE | |
404 | #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE | |
405 | #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH | |
406 | #define CONFIG_SYS_UEC8_PHY_ADDR 6 | |
407 | #define CONFIG_SYS_UEC8_INTERFACE_MODE ENET_1000_SGMII | |
408 | #endif /* CONFIG_UEC_ETH8 */ | |
409 | ||
765547dc HW |
410 | #endif /* CONFIG_QE */ |
411 | ||
412 | #if defined(CONFIG_PCI) | |
413 | ||
414 | #define CONFIG_NET_MULTI | |
415 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
416 | ||
417 | #undef CONFIG_EEPRO100 | |
418 | #undef CONFIG_TULIP | |
419 | ||
420 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
421 | ||
422 | #endif /* CONFIG_PCI */ | |
423 | ||
424 | #ifndef CONFIG_NET_MULTI | |
425 | #define CONFIG_NET_MULTI 1 | |
426 | #endif | |
427 | ||
428 | /* | |
429 | * Environment | |
430 | */ | |
431 | #define CONFIG_ENV_IS_IN_FLASH 1 | |
fb279490 | 432 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
765547dc | 433 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 256K(one sector) for env */ |
fb279490 | 434 | #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE |
765547dc HW |
435 | |
436 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
437 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
438 | ||
439 | /* QE microcode/firmware address */ | |
440 | #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 | |
441 | ||
442 | /* | |
443 | * BOOTP options | |
444 | */ | |
445 | #define CONFIG_BOOTP_BOOTFILESIZE | |
446 | #define CONFIG_BOOTP_BOOTPATH | |
447 | #define CONFIG_BOOTP_GATEWAY | |
448 | #define CONFIG_BOOTP_HOSTNAME | |
449 | ||
450 | ||
451 | /* | |
452 | * Command line configuration. | |
453 | */ | |
454 | #include <config_cmd_default.h> | |
455 | ||
456 | #define CONFIG_CMD_PING | |
457 | #define CONFIG_CMD_I2C | |
458 | #define CONFIG_CMD_MII | |
459 | #define CONFIG_CMD_ELF | |
460 | #define CONFIG_CMD_IRQ | |
461 | #define CONFIG_CMD_SETEXPR | |
462 | ||
463 | #if defined(CONFIG_PCI) | |
464 | #define CONFIG_CMD_PCI | |
465 | #endif | |
466 | ||
467 | ||
468 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
469 | ||
7f52ed5e AV |
470 | #define CONFIG_MMC 1 |
471 | ||
472 | #ifdef CONFIG_MMC | |
473 | #define CONFIG_FSL_ESDHC | |
474 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
475 | #define CONFIG_CMD_MMC | |
476 | #define CONFIG_GENERIC_MMC | |
477 | #define CONFIG_CMD_EXT2 | |
478 | #define CONFIG_CMD_FAT | |
479 | #define CONFIG_DOS_PARTITION | |
480 | #endif | |
481 | ||
765547dc HW |
482 | /* |
483 | * Miscellaneous configurable options | |
484 | */ | |
485 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
486 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
487 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
488 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
489 | #if defined(CONFIG_CMD_KGDB) | |
490 | #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ | |
491 | #else | |
492 | #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ | |
493 | #endif | |
494 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
495 | /* Print Buffer Size */ | |
496 | #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ | |
497 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
498 | /* Boot Argument Buffer Size */ | |
499 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
500 | ||
501 | /* | |
502 | * For booting Linux, the board info and command line data | |
89188a62 | 503 | * have to be in the first 16 MB of memory, since this is |
765547dc HW |
504 | * the maximum mapped by the Linux kernel during initialization. |
505 | */ | |
89188a62 | 506 | #define CONFIG_SYS_BOOTMAPSZ (16 << 20) |
765547dc HW |
507 | /* Initial Memory map for Linux*/ |
508 | ||
509 | /* | |
510 | * Internal Definitions | |
511 | * | |
512 | * Boot Flags | |
513 | */ | |
514 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
515 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
516 | ||
517 | #if defined(CONFIG_CMD_KGDB) | |
518 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
519 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
520 | #endif | |
521 | ||
522 | /* | |
523 | * Environment Configuration | |
524 | */ | |
525 | #define CONFIG_HOSTNAME mpc8569mds | |
526 | #define CONFIG_ROOTPATH /nfsroot | |
527 | #define CONFIG_BOOTFILE your.uImage | |
528 | ||
529 | #define CONFIG_SERVERIP 192.168.1.1 | |
530 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
531 | #define CONFIG_NETMASK 255.255.255.0 | |
532 | ||
533 | #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ | |
534 | ||
535 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
536 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ | |
537 | ||
538 | #define CONFIG_BAUDRATE 115200 | |
539 | ||
540 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
541 | "netdev=eth0\0" \ | |
542 | "consoledev=ttyS0\0" \ | |
543 | "ramdiskaddr=600000\0" \ | |
544 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
545 | "fdtaddr=400000\0" \ | |
546 | "fdtfile=your.fdt.dtb\0" \ | |
547 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
548 | "nfsroot=$serverip:$rootpath " \ | |
549 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
550 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
551 | "ramargs=setenv bootargs root=/dev/ram rw " \ | |
552 | "console=$consoledev,$baudrate $othbootargs\0" \ | |
553 | ||
554 | #define CONFIG_NFSBOOTCOMMAND \ | |
555 | "run nfsargs;" \ | |
556 | "tftp $loadaddr $bootfile;" \ | |
557 | "tftp $fdtaddr $fdtfile;" \ | |
558 | "bootm $loadaddr - $fdtaddr" | |
559 | ||
560 | #define CONFIG_RAMBOOTCOMMAND \ | |
561 | "run ramargs;" \ | |
562 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
563 | "tftp $loadaddr $bootfile;" \ | |
564 | "bootm $loadaddr $ramdiskaddr" | |
565 | ||
566 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
567 | ||
568 | #endif /* __CONFIG_H */ |