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129ba616 KG |
1 | /* |
2 | * Copyright 2007-2008 Freescale Semiconductor, Inc. | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | /* | |
24 | * mpc8572ds board configuration file | |
25 | * | |
26 | */ | |
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* High Level Configuration Options */ | |
31 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
32 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
33 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */ | |
34 | #define CONFIG_MPC8572 1 | |
35 | #define CONFIG_MPC8572DS 1 | |
36 | #define CONFIG_MP 1 /* support multiple processors */ | |
37 | #define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ | |
38 | ||
39 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ | |
40 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ | |
41 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot 2) */ | |
42 | #define CONFIG_PCIE3 1 /* PCIE controler 3 (ULI bridge) */ | |
43 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
44 | #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ | |
0151cbac | 45 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
129ba616 KG |
46 | |
47 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
48 | ||
49 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
50 | #define CONFIG_ENV_OVERWRITE | |
51 | ||
52 | /* | |
53 | * When initializing flash, if we cannot find the manufacturer ID, | |
54 | * assume this is the AMD flash associated with the CDS board. | |
55 | * This allows booting from a promjet. | |
56 | */ | |
57 | #define CONFIG_ASSUME_AMD_FLASH | |
58 | ||
59 | #ifndef __ASSEMBLY__ | |
60 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
61 | extern unsigned long get_board_ddr_clk(unsigned long dummy); | |
62 | #endif | |
63 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */ | |
64 | #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */ | |
4ca06607 | 65 | #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ |
129ba616 KG |
66 | #define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq |
67 | from ICS307 instead of switches */ | |
68 | ||
69 | /* | |
70 | * These can be toggled for performance analysis, otherwise use default. | |
71 | */ | |
72 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
73 | #define CONFIG_BTB /* toggle branch predition */ | |
129ba616 KG |
74 | |
75 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
76 | ||
6d0f6bcf JCPV |
77 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ |
78 | #define CONFIG_SYS_MEMTEST_END 0x7fffffff | |
129ba616 KG |
79 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ |
80 | ||
81 | /* | |
82 | * Base addresses -- Note these are effective addresses where the | |
83 | * actual resources get mapped (not physical addresses) | |
84 | */ | |
6d0f6bcf JCPV |
85 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
86 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ | |
87 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
88 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
129ba616 | 89 | |
6d0f6bcf JCPV |
90 | #define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) |
91 | #define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) | |
92 | #define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) | |
129ba616 KG |
93 | |
94 | /* DDR Setup */ | |
b5f65dfa | 95 | #define CONFIG_SYS_DDR_TLB_START 9 |
129ba616 KG |
96 | #define CONFIG_FSL_DDR2 |
97 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
98 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
99 | #define CONFIG_DDR_SPD | |
100 | #undef CONFIG_DDR_DLL | |
101 | ||
9b0ad1b1 | 102 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER |
129ba616 KG |
103 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
104 | ||
6d0f6bcf JCPV |
105 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 |
106 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
129ba616 KG |
107 | |
108 | #define CONFIG_NUM_DDR_CONTROLLERS 2 | |
109 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
110 | #define CONFIG_CHIP_SELECTS_PER_CTRL 2 | |
111 | ||
112 | /* I2C addresses of SPD EEPROMs */ | |
6d0f6bcf | 113 | #define CONFIG_SYS_SPD_BUS_NUM 1 /* SPD EEPROMS locate on I2C bus 1 */ |
129ba616 KG |
114 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ |
115 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ | |
116 | ||
117 | /* These are used when DDR doesn't use SPD. */ | |
dc889e86 DL |
118 | #define CONFIG_SYS_SDRAM_SIZE 512 /* DDR is 512MB */ |
119 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F | |
120 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
121 | #define CONFIG_SYS_DDR_TIMING_3 0x00020000 | |
122 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
123 | #define CONFIG_SYS_DDR_TIMING_1 0x626b2634 | |
124 | #define CONFIG_SYS_DDR_TIMING_2 0x062874cf | |
125 | #define CONFIG_SYS_DDR_MODE_1 0x00440462 | |
6d0f6bcf | 126 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 |
dc889e86 | 127 | #define CONFIG_SYS_DDR_INTERVAL 0x0c300100 |
6d0f6bcf | 128 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef |
dc889e86 DL |
129 | #define CONFIG_SYS_DDR_CLK_CTRL 0x00800000 |
130 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
6d0f6bcf | 131 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 |
dc889e86 DL |
132 | #define CONFIG_SYS_DDR_CONTROL 0xc3000008 /* Type = DDR2 */ |
133 | #define CONFIG_SYS_DDR_CONTROL2 0x24400000 | |
6d0f6bcf JCPV |
134 | |
135 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d | |
136 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
137 | #define CONFIG_SYS_DDR_SBE 0x00010000 | |
129ba616 | 138 | |
129ba616 KG |
139 | /* |
140 | * Make sure required options are set | |
141 | */ | |
142 | #ifndef CONFIG_SPD_EEPROM | |
143 | #error ("CONFIG_SPD_EEPROM is required") | |
144 | #endif | |
145 | ||
146 | #undef CONFIG_CLOCKS_IN_MHZ | |
147 | ||
148 | /* | |
149 | * Memory map | |
150 | * | |
151 | * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable | |
152 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable | |
153 | * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable | |
154 | * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable | |
155 | * | |
156 | * Localbus cacheable (TBD) | |
157 | * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable | |
158 | * | |
159 | * Localbus non-cacheable | |
160 | * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable | |
161 | * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable | |
3cbd8231 | 162 | * 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable |
129ba616 KG |
163 | * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0 |
164 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
165 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
166 | */ | |
167 | ||
168 | /* | |
169 | * Local Bus Definitions | |
170 | */ | |
6d0f6bcf | 171 | #define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */ |
c953ddfd | 172 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE |
129ba616 | 173 | |
c953ddfd KG |
174 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V) |
175 | #define CONFIG_SYS_OR0_PRELIM 0xf8000ff7 | |
129ba616 | 176 | |
c953ddfd KG |
177 | #define CONFIG_SYS_BR1_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V) |
178 | #define CONFIG_SYS_OR1_PRELIM 0xf8000ff7 | |
129ba616 | 179 | |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE + 0x8000000, CONFIG_SYS_FLASH_BASE} |
181 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
129ba616 KG |
182 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ |
183 | ||
6d0f6bcf JCPV |
184 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
185 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
186 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
187 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
188 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
129ba616 | 189 | |
6d0f6bcf | 190 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ |
129ba616 KG |
191 | |
192 | #define CONFIG_FLASH_CFI_DRIVER | |
6d0f6bcf JCPV |
193 | #define CONFIG_SYS_FLASH_CFI |
194 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
195 | #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 | |
129ba616 KG |
196 | |
197 | #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ | |
198 | ||
199 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ | |
200 | #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ | |
52b565f5 | 201 | #define PIXIS_BASE_PHYS PIXIS_BASE |
129ba616 | 202 | |
52b565f5 | 203 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) |
6d0f6bcf | 204 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ |
129ba616 KG |
205 | |
206 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
207 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
208 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
209 | #define PIXIS_CSR 0x3 /* PIXIS General control/status register */ | |
210 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
211 | #define PIXIS_PWR 0x5 /* PIXIS Power status register */ | |
212 | #define PIXIS_AUX 0x6 /* Auxiliary 1 register */ | |
213 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
214 | #define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ | |
215 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
216 | #define PIXIS_VSTAT 0x11 /* VELA Status Register */ | |
217 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
218 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
219 | #define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ | |
220 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
221 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
222 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
223 | #define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ | |
224 | #define PIXIS_VSYSCLK0 0x1C /* VELA SYSCLK0 Register */ | |
225 | #define PIXIS_VSYSCLK1 0x1D /* VELA SYSCLK1 Register */ | |
226 | #define PIXIS_VSYSCLK2 0x1E /* VELA SYSCLK2 Register */ | |
227 | #define PIXIS_VDDRCLK0 0x1F /* VELA DDRCLK0 Register */ | |
228 | #define PIXIS_VDDRCLK1 0x20 /* VELA DDRCLK1 Register */ | |
229 | #define PIXIS_VDDRCLK2 0x21 /* VELA DDRCLK2 Register */ | |
230 | #define PIXIS_VWATCH 0x24 /* Watchdog Register */ | |
231 | #define PIXIS_LED 0x25 /* LED Register */ | |
232 | ||
233 | /* old pixis referenced names */ | |
234 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
235 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
6d0f6bcf | 236 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 |
7e183cad LY |
237 | #define PIXIS_VSPEED2_TSEC1SER 0x8 |
238 | #define PIXIS_VSPEED2_TSEC2SER 0x4 | |
239 | #define PIXIS_VSPEED2_TSEC3SER 0x2 | |
240 | #define PIXIS_VSPEED2_TSEC4SER 0x1 | |
241 | #define PIXIS_VCFGEN1_TSEC1SER 0x20 | |
242 | #define PIXIS_VCFGEN1_TSEC2SER 0x20 | |
243 | #define PIXIS_VCFGEN1_TSEC3SER 0x20 | |
244 | #define PIXIS_VCFGEN1_TSEC4SER 0x20 | |
245 | #define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ | |
246 | | PIXIS_VSPEED2_TSEC2SER \ | |
247 | | PIXIS_VSPEED2_TSEC3SER \ | |
248 | | PIXIS_VSPEED2_TSEC4SER) | |
249 | #define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ | |
250 | | PIXIS_VCFGEN1_TSEC2SER \ | |
251 | | PIXIS_VCFGEN1_TSEC3SER \ | |
252 | | PIXIS_VCFGEN1_TSEC4SER) | |
129ba616 | 253 | |
6d0f6bcf JCPV |
254 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
255 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ | |
256 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
129ba616 | 257 | |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ |
259 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
260 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
129ba616 | 261 | |
6d0f6bcf JCPV |
262 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
263 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
129ba616 | 264 | |
c013b749 HW |
265 | #define CONFIG_SYS_NAND_BASE 0xffa00000 |
266 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
267 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\ | |
268 | CONFIG_SYS_NAND_BASE + 0x40000, \ | |
269 | CONFIG_SYS_NAND_BASE + 0x80000,\ | |
270 | CONFIG_SYS_NAND_BASE + 0xC0000} | |
271 | #define CONFIG_SYS_MAX_NAND_DEVICE 4 | |
c013b749 | 272 | #define CONFIG_MTD_NAND_VERIFY_WRITE |
3cbd8231 WD |
273 | #define CONFIG_CMD_NAND 1 |
274 | #define CONFIG_NAND_FSL_ELBC 1 | |
c013b749 HW |
275 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) |
276 | ||
277 | /* NAND flash config */ | |
278 | #define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | |
3cbd8231 WD |
279 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
280 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
281 | | BR_MS_FCM /* MSEL = FCM */ \ | |
282 | | BR_V) /* valid */ | |
283 | #define CONFIG_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \ | |
284 | | OR_FCM_PGS /* Large Page*/ \ | |
285 | | OR_FCM_CSCT \ | |
286 | | OR_FCM_CST \ | |
287 | | OR_FCM_CHT \ | |
288 | | OR_FCM_SCY_1 \ | |
289 | | OR_FCM_TRLX \ | |
290 | | OR_FCM_EHTR) | |
c013b749 HW |
291 | |
292 | #define CONFIG_SYS_BR2_PRELIM CONFIG_NAND_BR_PRELIM /* NAND Base Address */ | |
293 | #define CONFIG_SYS_OR2_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
294 | ||
295 | #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x40000)\ | |
3cbd8231 WD |
296 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
297 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
298 | | BR_MS_FCM /* MSEL = FCM */ \ | |
299 | | BR_V) /* valid */ | |
300 | #define CONFIG_SYS_OR4_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
c013b749 | 301 | #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0x80000)\ |
3cbd8231 WD |
302 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
303 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
304 | | BR_MS_FCM /* MSEL = FCM */ \ | |
305 | | BR_V) /* valid */ | |
306 | #define CONFIG_SYS_OR5_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
c013b749 HW |
307 | |
308 | #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_NAND_BASE_PHYS + 0xC0000)\ | |
3cbd8231 WD |
309 | | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ |
310 | | BR_PS_8 /* Port Size = 8 bit */ \ | |
311 | | BR_MS_FCM /* MSEL = FCM */ \ | |
312 | | BR_V) /* valid */ | |
313 | #define CONFIG_SYS_OR6_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ | |
c013b749 HW |
314 | |
315 | ||
129ba616 KG |
316 | /* Serial Port - controlled on board with jumper J8 |
317 | * open - index 2 | |
318 | * shorted - index 1 | |
319 | */ | |
320 | #define CONFIG_CONS_INDEX 1 | |
321 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_NS16550 |
323 | #define CONFIG_SYS_NS16550_SERIAL | |
324 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
325 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
129ba616 | 326 | |
6d0f6bcf | 327 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
129ba616 KG |
328 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
329 | ||
6d0f6bcf JCPV |
330 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
331 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
129ba616 KG |
332 | |
333 | /* Use the HUSH parser */ | |
6d0f6bcf JCPV |
334 | #define CONFIG_SYS_HUSH_PARSER |
335 | #ifdef CONFIG_SYS_HUSH_PARSER | |
336 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
129ba616 KG |
337 | #endif |
338 | ||
339 | /* | |
340 | * Pass open firmware flat tree | |
341 | */ | |
342 | #define CONFIG_OF_LIBFDT 1 | |
343 | #define CONFIG_OF_BOARD_SETUP 1 | |
344 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
345 | ||
6d0f6bcf JCPV |
346 | #define CONFIG_SYS_64BIT_VSPRINTF 1 |
347 | #define CONFIG_SYS_64BIT_STRTOUL 1 | |
129ba616 KG |
348 | |
349 | /* new uImage format support */ | |
350 | #define CONFIG_FIT 1 | |
351 | #define CONFIG_FIT_VERBOSE 1 /* enable fit_format_{error,warning}() */ | |
352 | ||
353 | /* I2C */ | |
354 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
355 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
356 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
1f3ba317 HW |
357 | #define CONFIG_I2C_MULTI_BUS |
358 | #define CONFIG_I2C_CMD_TREE | |
6d0f6bcf JCPV |
359 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
360 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
361 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
362 | #define CONFIG_SYS_I2C_NOPROBES {{0,0x29}}/* Don't probe these addrs */ | |
363 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
364 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
129ba616 | 365 | |
445a7b38 HW |
366 | /* |
367 | * I2C2 EEPROM | |
368 | */ | |
369 | #define CONFIG_ID_EEPROM | |
370 | #ifdef CONFIG_ID_EEPROM | |
6d0f6bcf | 371 | #define CONFIG_SYS_I2C_EEPROM_NXID |
445a7b38 | 372 | #endif |
6d0f6bcf JCPV |
373 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
374 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
375 | #define CONFIG_SYS_EEPROM_BUS_NUM 1 | |
445a7b38 | 376 | |
129ba616 KG |
377 | /* |
378 | * General PCI | |
379 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
380 | */ | |
381 | ||
129ba616 | 382 | /* controller 3, direct to uli, tgtid 3, Base address 8000 */ |
10795f42 KG |
383 | #define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000 |
384 | #define CONFIG_SYS_PCIE3_MEM_PHYS CONFIG_SYS_PCIE3_MEM_BUS | |
6d0f6bcf | 385 | #define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ |
5f91ef6a | 386 | #define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
387 | #define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000 |
388 | #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ | |
129ba616 KG |
389 | |
390 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
10795f42 KG |
391 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 |
392 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS | |
6d0f6bcf | 393 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ |
5f91ef6a | 394 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
395 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 |
396 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
129ba616 KG |
397 | |
398 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
10795f42 KG |
399 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000 |
400 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS | |
6d0f6bcf | 401 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
5f91ef6a | 402 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
403 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000 |
404 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
129ba616 KG |
405 | |
406 | #if defined(CONFIG_PCI) | |
407 | ||
408 | /*PCIE video card used*/ | |
6d0f6bcf | 409 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_PHYS |
129ba616 KG |
410 | |
411 | /* video */ | |
412 | #define CONFIG_VIDEO | |
413 | ||
414 | #if defined(CONFIG_VIDEO) | |
415 | #define CONFIG_BIOSEMU | |
416 | #define CONFIG_CFB_CONSOLE | |
417 | #define CONFIG_VIDEO_SW_CURSOR | |
418 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
419 | #define CONFIG_ATI_RADEON_FB | |
420 | #define CONFIG_VIDEO_LOGO | |
421 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
6d0f6bcf | 422 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET |
129ba616 KG |
423 | #endif |
424 | ||
425 | #define CONFIG_NET_MULTI | |
426 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
427 | ||
428 | #undef CONFIG_EEPRO100 | |
429 | #undef CONFIG_TULIP | |
430 | #undef CONFIG_RTL8139 | |
431 | ||
432 | #ifdef CONFIG_RTL8139 | |
433 | /* This macro is used by RTL8139 but not defined in PPC architecture */ | |
434 | #define KSEG1ADDR(x) (x) | |
435 | #define _IO_BASE 0x00000000 | |
436 | #endif | |
437 | ||
438 | #ifndef CONFIG_PCI_PNP | |
5f91ef6a KG |
439 | #define PCI_ENET0_IOADDR CONFIG_SYS_PCIE3_IO_BUS |
440 | #define PCI_ENET0_MEMADDR CONFIG_SYS_PCIE3_IO_BUS | |
129ba616 KG |
441 | #define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */ |
442 | #endif | |
443 | ||
444 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
445 | #define CONFIG_DOS_PARTITION | |
446 | #define CONFIG_SCSI_AHCI | |
447 | ||
448 | #ifdef CONFIG_SCSI_AHCI | |
449 | #define CONFIG_SATA_ULI5288 | |
6d0f6bcf JCPV |
450 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
451 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
452 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
453 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
129ba616 KG |
454 | #endif /* SCSI */ |
455 | ||
456 | #endif /* CONFIG_PCI */ | |
457 | ||
458 | ||
459 | #if defined(CONFIG_TSEC_ENET) | |
460 | ||
461 | #ifndef CONFIG_NET_MULTI | |
462 | #define CONFIG_NET_MULTI 1 | |
463 | #endif | |
464 | ||
465 | #define CONFIG_MII 1 /* MII PHY management */ | |
466 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
467 | #define CONFIG_TSEC1 1 | |
468 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
469 | #define CONFIG_TSEC2 1 | |
470 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
471 | #define CONFIG_TSEC3 1 | |
472 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
473 | #define CONFIG_TSEC4 1 | |
474 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
475 | ||
7e183cad LY |
476 | #define CONFIG_PIXIS_SGMII_CMD |
477 | #define CONFIG_FSL_SGMII_RISER 1 | |
478 | #define SGMII_RISER_PHY_OFFSET 0x1c | |
479 | ||
480 | #ifdef CONFIG_FSL_SGMII_RISER | |
481 | #define CONFIG_SYS_TBIPA_VALUE 0x10 /* avoid conflict with eTSEC4 paddr */ | |
482 | #endif | |
483 | ||
129ba616 KG |
484 | #define TSEC1_PHY_ADDR 0 |
485 | #define TSEC2_PHY_ADDR 1 | |
486 | #define TSEC3_PHY_ADDR 2 | |
487 | #define TSEC4_PHY_ADDR 3 | |
488 | ||
489 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
490 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
491 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
492 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
493 | ||
494 | #define TSEC1_PHYIDX 0 | |
495 | #define TSEC2_PHYIDX 0 | |
496 | #define TSEC3_PHYIDX 0 | |
497 | #define TSEC4_PHYIDX 0 | |
498 | ||
499 | #define CONFIG_ETHPRIME "eTSEC1" | |
500 | ||
501 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
502 | #endif /* CONFIG_TSEC_ENET */ | |
503 | ||
504 | /* | |
505 | * Environment | |
506 | */ | |
5a1aceb0 | 507 | #define CONFIG_ENV_IS_IN_FLASH 1 |
6d0f6bcf | 508 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 |
0e8d1586 | 509 | #define CONFIG_ENV_ADDR 0xfff80000 |
129ba616 | 510 | #else |
6fc110bd | 511 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
129ba616 | 512 | #endif |
0e8d1586 JCPV |
513 | #define CONFIG_ENV_SIZE 0x2000 |
514 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
129ba616 KG |
515 | |
516 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 517 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
129ba616 KG |
518 | |
519 | /* | |
520 | * Command line configuration. | |
521 | */ | |
522 | #include <config_cmd_default.h> | |
523 | ||
524 | #define CONFIG_CMD_IRQ | |
525 | #define CONFIG_CMD_PING | |
526 | #define CONFIG_CMD_I2C | |
527 | #define CONFIG_CMD_MII | |
528 | #define CONFIG_CMD_ELF | |
1c9aa76b KG |
529 | #define CONFIG_CMD_IRQ |
530 | #define CONFIG_CMD_SETEXPR | |
129ba616 KG |
531 | |
532 | #if defined(CONFIG_PCI) | |
533 | #define CONFIG_CMD_PCI | |
534 | #define CONFIG_CMD_BEDBUG | |
535 | #define CONFIG_CMD_NET | |
536 | #define CONFIG_CMD_SCSI | |
537 | #define CONFIG_CMD_EXT2 | |
538 | #endif | |
539 | ||
540 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
541 | ||
542 | /* | |
543 | * Miscellaneous configurable options | |
544 | */ | |
6d0f6bcf | 545 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
129ba616 | 546 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf JCPV |
547 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
548 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
129ba616 | 549 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 550 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
129ba616 | 551 | #else |
6d0f6bcf | 552 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
129ba616 | 553 | #endif |
6d0f6bcf JCPV |
554 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
555 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
556 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
557 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
129ba616 KG |
558 | |
559 | /* | |
560 | * For booting Linux, the board info and command line data | |
561 | * have to be in the first 8 MB of memory, since this is | |
562 | * the maximum mapped by the Linux kernel during initialization. | |
563 | */ | |
6d0f6bcf | 564 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
129ba616 KG |
565 | |
566 | /* | |
567 | * Internal Definitions | |
568 | * | |
569 | * Boot Flags | |
570 | */ | |
571 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
572 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
573 | ||
574 | #if defined(CONFIG_CMD_KGDB) | |
575 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
576 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
577 | #endif | |
578 | ||
579 | /* | |
580 | * Environment Configuration | |
581 | */ | |
582 | ||
583 | /* The mac addresses for all ethernet interface */ | |
584 | #if defined(CONFIG_TSEC_ENET) | |
585 | #define CONFIG_HAS_ETH0 | |
586 | #define CONFIG_ETHADDR 00:E0:0C:02:00:FD | |
587 | #define CONFIG_HAS_ETH1 | |
588 | #define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD | |
589 | #define CONFIG_HAS_ETH2 | |
590 | #define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD | |
591 | #define CONFIG_HAS_ETH3 | |
592 | #define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD | |
593 | #endif | |
594 | ||
595 | #define CONFIG_IPADDR 192.168.1.254 | |
596 | ||
597 | #define CONFIG_HOSTNAME unknown | |
598 | #define CONFIG_ROOTPATH /opt/nfsroot | |
599 | #define CONFIG_BOOTFILE uImage | |
600 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ | |
601 | ||
602 | #define CONFIG_SERVERIP 192.168.1.1 | |
603 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
604 | #define CONFIG_NETMASK 255.255.255.0 | |
605 | ||
606 | /* default location for tftp and bootm */ | |
607 | #define CONFIG_LOADADDR 1000000 | |
608 | ||
609 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
610 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
611 | ||
612 | #define CONFIG_BAUDRATE 115200 | |
613 | ||
614 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
4ca06607 | 615 | "memctl_intlv_ctl=2\0" \ |
129ba616 KG |
616 | "netdev=eth0\0" \ |
617 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
618 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
619 | "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ | |
620 | "erase " MK_STR(TEXT_BASE) " +$filesize; " \ | |
621 | "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ | |
622 | "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ | |
623 | "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ | |
624 | "consoledev=ttyS0\0" \ | |
625 | "ramdiskaddr=2000000\0" \ | |
626 | "ramdiskfile=8572ds/ramdisk.uboot\0" \ | |
627 | "fdtaddr=c00000\0" \ | |
628 | "fdtfile=8572ds/mpc8572ds.dtb\0" \ | |
629 | "bdev=sda3\0" | |
630 | ||
631 | #define CONFIG_HDBOOT \ | |
632 | "setenv bootargs root=/dev/$bdev rw " \ | |
633 | "console=$consoledev,$baudrate $othbootargs;" \ | |
634 | "tftp $loadaddr $bootfile;" \ | |
635 | "tftp $fdtaddr $fdtfile;" \ | |
636 | "bootm $loadaddr - $fdtaddr" | |
637 | ||
638 | #define CONFIG_NFSBOOTCOMMAND \ | |
639 | "setenv bootargs root=/dev/nfs rw " \ | |
640 | "nfsroot=$serverip:$rootpath " \ | |
641 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
642 | "console=$consoledev,$baudrate $othbootargs;" \ | |
643 | "tftp $loadaddr $bootfile;" \ | |
644 | "tftp $fdtaddr $fdtfile;" \ | |
645 | "bootm $loadaddr - $fdtaddr" | |
646 | ||
647 | #define CONFIG_RAMBOOTCOMMAND \ | |
648 | "setenv bootargs root=/dev/ram rw " \ | |
649 | "console=$consoledev,$baudrate $othbootargs;" \ | |
650 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
651 | "tftp $loadaddr $bootfile;" \ | |
652 | "tftp $fdtaddr $fdtfile;" \ | |
653 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
654 | ||
655 | #define CONFIG_BOOTCOMMAND CONFIG_HDBOOT | |
656 | ||
657 | #endif /* __CONFIG_H */ |