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9553df86 | 1 | /* |
ba8e76bd | 2 | * Copyright 2007-2011 Freescale Semiconductor, Inc. |
9553df86 | 3 | * |
5b8031cc | 4 | * SPDX-License-Identifier: GPL-2.0 |
9553df86 JL |
5 | */ |
6 | ||
7 | /* | |
8 | * MPC8610HPCD board configuration file | |
9553df86 JL |
9 | */ |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | /* High Level Configuration Options */ | |
9553df86 JL |
15 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
16 | ||
2ae18241 WD |
17 | #define CONFIG_SYS_TEXT_BASE 0xfff00000 |
18 | ||
070ba561 | 19 | /* video */ |
ba8e76bd TT |
20 | #define CONFIG_FSL_DIU_FB |
21 | ||
7d3053fb TT |
22 | #ifdef CONFIG_FSL_DIU_FB |
23 | #define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000) | |
e69e520f TT |
24 | #define CONFIG_VIDEO_LOGO |
25 | #define CONFIG_VIDEO_BMP_LOGO | |
070ba561 YS |
26 | #endif |
27 | ||
9553df86 | 28 | #ifdef RUN_DIAG |
6d0f6bcf | 29 | #define CONFIG_SYS_DIAG_ADDR 0xff800000 |
9553df86 JL |
30 | #endif |
31 | ||
1266df88 BB |
32 | /* |
33 | * virtual address to be used for temporary mappings. There | |
34 | * should be 128k free at this VA. | |
35 | */ | |
36 | #define CONFIG_SYS_SCRATCH_VA 0xc0000000 | |
37 | ||
b38eaec5 | 38 | #define CONFIG_PCI1 1 /* PCI controller 1 */ |
9553df86 JL |
39 | #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ |
40 | #define CONFIG_PCIE2 1 /* PCIe 2 connected to slot */ | |
41 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ | |
842033e6 | 42 | #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ |
8ba93f68 | 43 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
9553df86 JL |
44 | |
45 | #define CONFIG_ENV_OVERWRITE | |
9553df86 JL |
46 | #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ |
47 | ||
4bbfd3e2 | 48 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
31d82672 | 49 | #define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ |
9553df86 JL |
50 | #define CONFIG_ALTIVEC 1 |
51 | ||
52 | /* | |
53 | * L2CR setup -- make sure this is right for your board! | |
54 | */ | |
6d0f6bcf | 55 | #define CONFIG_SYS_L2 |
9553df86 | 56 | #define L2_INIT 0 |
a877880c | 57 | #define L2_ENABLE (L2CR_L2E |0x00100000 ) |
9553df86 JL |
58 | |
59 | #ifndef CONFIG_SYS_CLK_FREQ | |
60 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) | |
61 | #endif | |
62 | ||
a877880c | 63 | #define CONFIG_MISC_INIT_R 1 |
9553df86 | 64 | |
6d0f6bcf JCPV |
65 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
66 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
9553df86 JL |
67 | |
68 | /* | |
69 | * Base addresses -- Note these are effective addresses where the | |
70 | * actual resources get mapped (not physical addresses) | |
71 | */ | |
6d0f6bcf JCPV |
72 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
73 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
9553df86 | 74 | |
f698738e JL |
75 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR |
76 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
ad19e7a5 | 77 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
f698738e | 78 | |
39aa1a73 | 79 | /* DDR Setup */ |
39aa1a73 JL |
80 | #undef CONFIG_FSL_DDR_INTERACTIVE |
81 | #define CONFIG_SPD_EEPROM /* Use SPD for DDR */ | |
82 | #define CONFIG_DDR_SPD | |
83 | ||
84 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
85 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
86 | ||
6d0f6bcf JCPV |
87 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
88 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
1266df88 | 89 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
9553df86 JL |
90 | #define CONFIG_VERY_BIG_RAM |
91 | ||
39aa1a73 JL |
92 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 |
93 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
94 | ||
c39f44dc | 95 | #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ |
9553df86 | 96 | |
39aa1a73 | 97 | /* These are used when DDR doesn't use SPD. */ |
6d0f6bcf | 98 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
9553df86 JL |
99 | |
100 | #if 0 /* TODO */ | |
6d0f6bcf JCPV |
101 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F |
102 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202 /* Enable, no interleaving */ | |
103 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
104 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
105 | #define CONFIG_SYS_DDR_TIMING_1 0x3935d322 | |
106 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
107 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
108 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
109 | #define CONFIG_SYS_DDR_INTERVAL 0x06180100 | |
110 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
111 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
112 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
113 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
114 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
115 | #define CONFIG_SYS_DDR_CONTROL2 0x04400010 | |
116 | ||
117 | #define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000 | |
118 | #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 | |
119 | #define CONFIG_SYS_DDR_SBE 0x000f0000 | |
39aa1a73 | 120 | |
9553df86 | 121 | #endif |
39aa1a73 | 122 | |
ad8f8687 | 123 | #define CONFIG_ID_EEPROM |
6d0f6bcf | 124 | #define CONFIG_SYS_I2C_EEPROM_NXID |
32628c50 | 125 | #define CONFIG_ID_EEPROM |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
127 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
9553df86 | 128 | |
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_FLASH_BASE 0xf0000000 /* start of FLASH 128M */ |
130 | #define CONFIG_SYS_FLASH_BASE2 0xf8000000 | |
9553df86 | 131 | |
6d0f6bcf | 132 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2} |
9553df86 | 133 | |
6d0f6bcf JCPV |
134 | #define CONFIG_SYS_BR0_PRELIM 0xf8001001 /* port size 16bit */ |
135 | #define CONFIG_SYS_OR0_PRELIM 0xf8006e65 /* 128MB NOR Flash*/ | |
9553df86 | 136 | |
6d0f6bcf JCPV |
137 | #define CONFIG_SYS_BR1_PRELIM 0xf0001001 /* port size 16bit */ |
138 | #define CONFIG_SYS_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ | |
9553df86 | 139 | #if 0 /* TODO */ |
6d0f6bcf JCPV |
140 | #define CONFIG_SYS_BR2_PRELIM 0xf0000000 |
141 | #define CONFIG_SYS_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ | |
9553df86 | 142 | #endif |
6d0f6bcf JCPV |
143 | #define CONFIG_SYS_BR3_PRELIM 0xe8000801 /* port size 8bit */ |
144 | #define CONFIG_SYS_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ | |
9553df86 | 145 | |
761421cc | 146 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
9553df86 JL |
147 | #define PIXIS_BASE 0xe8000000 /* PIXIS registers */ |
148 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ | |
149 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
150 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
151 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
152 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch */ | |
153 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
a877880c | 154 | #define PIXIS_BRDCFG0 0x8 /* PIXIS Board Configuration Register0*/ |
9553df86 JL |
155 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ |
156 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
157 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
158 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
159 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ | |
160 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
161 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
162 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
2feb4af0 | 163 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0 /* Reset altbank mask */ |
9553df86 | 164 | |
6d0f6bcf JCPV |
165 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ |
166 | #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ | |
9553df86 | 167 | |
6d0f6bcf JCPV |
168 | #undef CONFIG_SYS_FLASH_CHECKSUM |
169 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
170 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
14d0a02a | 171 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
bf9a8c34 | 172 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
9553df86 | 173 | |
00b1883a | 174 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
175 | #define CONFIG_SYS_FLASH_CFI |
176 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
9553df86 | 177 | |
6d0f6bcf JCPV |
178 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
179 | #define CONFIG_SYS_RAMBOOT | |
9553df86 | 180 | #else |
6d0f6bcf | 181 | #undef CONFIG_SYS_RAMBOOT |
9553df86 JL |
182 | #endif |
183 | ||
6d0f6bcf | 184 | #if defined(CONFIG_SYS_RAMBOOT) |
9553df86 | 185 | #undef CONFIG_SPD_EEPROM |
6d0f6bcf | 186 | #define CONFIG_SYS_SDRAM_SIZE 256 |
9553df86 JL |
187 | #endif |
188 | ||
189 | #undef CONFIG_CLOCKS_IN_MHZ | |
190 | ||
6d0f6bcf JCPV |
191 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
192 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
193 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
9553df86 | 194 | #else |
6d0f6bcf | 195 | #define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000 /* Initial RAM address */ |
9553df86 | 196 | #endif |
553f0982 | 197 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
9553df86 | 198 | |
25ddd1fb | 199 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 200 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
9553df86 | 201 | |
6d0f6bcf JCPV |
202 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */ |
203 | #define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ | |
9553df86 JL |
204 | |
205 | /* Serial Port */ | |
206 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
207 | #define CONFIG_SYS_NS16550_SERIAL |
208 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
209 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
9553df86 | 210 | |
6d0f6bcf | 211 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
9553df86 JL |
212 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
213 | ||
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
215 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
9553df86 | 216 | |
9553df86 JL |
217 | /* maximum size of the flat tree (8K) */ |
218 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
219 | ||
9553df86 JL |
220 | /* |
221 | * I2C | |
222 | */ | |
00f792e0 HS |
223 | #define CONFIG_SYS_I2C |
224 | #define CONFIG_SYS_I2C_FSL | |
225 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
226 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
227 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
228 | #define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } | |
9553df86 JL |
229 | |
230 | /* | |
231 | * General PCI | |
232 | * Addresses are mapped 1-1. | |
233 | */ | |
3e3fffe3 BB |
234 | #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 |
235 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS | |
236 | #define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS | |
6d0f6bcf | 237 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */ |
3e3fffe3 | 238 | #define CONFIG_SYS_PCI1_IO_BUS 0x0000000 |
6d0f6bcf | 239 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000 |
3e3fffe3 | 240 | #define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000 |
6d0f6bcf | 241 | #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ |
9553df86 | 242 | |
9553df86 | 243 | /* controller 1, Base address 0xa000 */ |
b8526212 | 244 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
3e3fffe3 BB |
245 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 |
246 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS | |
6d0f6bcf | 247 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ |
3e3fffe3 | 248 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 |
6d0f6bcf JCPV |
249 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 |
250 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ | |
9553df86 JL |
251 | |
252 | /* controller 2, Base Address 0x9000 */ | |
b8526212 | 253 | #define CONFIG_SYS_PCIE2_NAME "Slot 1" |
3e3fffe3 BB |
254 | #define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 |
255 | #define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS | |
6d0f6bcf | 256 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ |
3e3fffe3 | 257 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 /* reuse mem LAW */ |
6d0f6bcf JCPV |
258 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000 |
259 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000 /* 1M */ | |
9553df86 | 260 | |
9553df86 JL |
261 | #if defined(CONFIG_PCI) |
262 | ||
263 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
264 | ||
7c2221eb RZ |
265 | #define CONFIG_ULI526X |
266 | #ifdef CONFIG_ULI526X | |
1d8a49ec | 267 | #endif |
9553df86 | 268 | |
9553df86 JL |
269 | /************************************************************ |
270 | * USB support | |
271 | ************************************************************/ | |
070ba561 YS |
272 | #define CONFIG_PCI_OHCI 1 |
273 | #define CONFIG_USB_OHCI_NEW 1 | |
6d0f6bcf JCPV |
274 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" |
275 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
276 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
9553df86 JL |
277 | |
278 | #if !defined(CONFIG_PCI_PNP) | |
279 | #define PCI_ENET0_IOADDR 0xe0000000 | |
280 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
281 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
282 | #endif | |
283 | ||
9553df86 JL |
284 | #ifdef CONFIG_SCSI_AHCI |
285 | #define CONFIG_SATA_ULI5288 | |
6d0f6bcf JCPV |
286 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
287 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
288 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
289 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
9553df86 JL |
290 | #endif |
291 | ||
292 | #endif /* CONFIG_PCI */ | |
293 | ||
294 | /* | |
295 | * BAT0 2G Cacheable, non-guarded | |
296 | * 0x0000_0000 2G DDR | |
297 | */ | |
9ff32d8c TT |
298 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW) |
299 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW) | |
9553df86 JL |
300 | |
301 | /* | |
302 | * BAT1 1G Cache-inhibited, guarded | |
303 | * 0x8000_0000 256M PCI-1 Memory | |
304 | * 0xa000_0000 256M PCI-Express 1 Memory | |
305 | * 0x9000_0000 256M PCI-Express 2 Memory | |
306 | */ | |
307 | ||
6d0f6bcf | 308 | #define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 309 | | BATL_GUARDEDSTORAGE) |
3e3fffe3 | 310 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP) |
6d0f6bcf JCPV |
311 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
312 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U | |
9553df86 JL |
313 | |
314 | /* | |
f3bceaab | 315 | * BAT2 16M Cache-inhibited, guarded |
9553df86 | 316 | * 0xe100_0000 1M PCI-1 I/O |
9553df86 JL |
317 | */ |
318 | ||
6d0f6bcf | 319 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 320 | | BATL_GUARDEDSTORAGE) |
3e3fffe3 | 321 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP) |
6d0f6bcf JCPV |
322 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) |
323 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
9553df86 JL |
324 | |
325 | /* | |
104992fc BB |
326 | * BAT3 4M Cache-inhibited, guarded |
327 | * 0xe000_0000 4M CCSR | |
9553df86 JL |
328 | */ |
329 | ||
104992fc | 330 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 331 | | BATL_GUARDEDSTORAGE) |
104992fc BB |
332 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP) |
333 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT) | |
6d0f6bcf | 334 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
9553df86 | 335 | |
f698738e JL |
336 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
337 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
338 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
339 | | BATL_GUARDEDSTORAGE) | |
340 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
341 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
342 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
343 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
344 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
345 | #endif | |
346 | ||
9553df86 | 347 | /* |
104992fc BB |
348 | * BAT4 32M Cache-inhibited, guarded |
349 | * 0xe200_0000 1M PCI-Express 2 I/O | |
350 | * 0xe300_0000 1M PCI-Express 1 I/O | |
9553df86 | 351 | */ |
104992fc BB |
352 | |
353 | #define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
9553df86 | 354 | | BATL_GUARDEDSTORAGE) |
104992fc BB |
355 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP) |
356 | #define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
6d0f6bcf | 357 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
9553df86 JL |
358 | |
359 | /* | |
360 | * BAT5 128K Cacheable, non-guarded | |
361 | * 0xe400_0000 128K Init RAM for stack in the CPU DCache (no backing memory) | |
362 | */ | |
6d0f6bcf JCPV |
363 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
364 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
365 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
366 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
9553df86 JL |
367 | |
368 | /* | |
369 | * BAT6 256M Cache-inhibited, guarded | |
370 | * 0xf000_0000 256M FLASH | |
371 | */ | |
6d0f6bcf | 372 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 373 | | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
374 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
375 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE) | |
376 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U | |
9553df86 | 377 | |
bf9a8c34 BB |
378 | /* Map the last 1M of flash where we're running from reset */ |
379 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
380 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
14d0a02a | 381 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
bf9a8c34 BB |
382 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
383 | | BATL_MEMCOHERENCE) | |
384 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
385 | ||
9553df86 JL |
386 | /* |
387 | * BAT7 4M Cache-inhibited, guarded | |
388 | * 0xe800_0000 4M PIXIS | |
389 | */ | |
6d0f6bcf | 390 | #define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ |
9553df86 | 391 | | BATL_GUARDEDSTORAGE) |
6d0f6bcf JCPV |
392 | #define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
393 | #define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) | |
394 | #define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U | |
9553df86 | 395 | |
9553df86 JL |
396 | /* |
397 | * Environment | |
398 | */ | |
6d0f6bcf | 399 | #ifndef CONFIG_SYS_RAMBOOT |
6d0f6bcf | 400 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
0e8d1586 JCPV |
401 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 126k (one sector) for env */ |
402 | #define CONFIG_ENV_SIZE 0x2000 | |
9553df86 | 403 | #else |
6d0f6bcf | 404 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
0e8d1586 | 405 | #define CONFIG_ENV_SIZE 0x2000 |
9553df86 JL |
406 | #endif |
407 | ||
408 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 409 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
9553df86 | 410 | |
9553df86 JL |
411 | /* |
412 | * BOOTP options | |
413 | */ | |
414 | #define CONFIG_BOOTP_BOOTFILESIZE | |
415 | #define CONFIG_BOOTP_BOOTPATH | |
416 | #define CONFIG_BOOTP_GATEWAY | |
417 | #define CONFIG_BOOTP_HOSTNAME | |
418 | ||
9553df86 JL |
419 | /* |
420 | * Command line configuration. | |
421 | */ | |
9553df86 | 422 | |
3473ab73 | 423 | #define CONFIG_WATCHDOG /* watchdog enabled */ |
6d0f6bcf | 424 | #define CONFIG_SYS_WATCHDOG_FREQ 5000 /* Feed interval, 5s */ |
9553df86 JL |
425 | |
426 | /* | |
427 | * Miscellaneous configurable options | |
428 | */ | |
6d0f6bcf | 429 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
6bee764b | 430 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
6d0f6bcf | 431 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
9553df86 | 432 | |
9553df86 JL |
433 | /* |
434 | * For booting Linux, the board info and command line data | |
435 | * have to be in the first 8 MB of memory, since this is | |
436 | * the maximum mapped by the Linux kernel during initialization. | |
437 | */ | |
e1efe43c SW |
438 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ |
439 | #define CONFIG_SYS_BOOTM_LEN (256 << 20) /* Increase max gunzip size */ | |
9553df86 | 440 | |
9553df86 JL |
441 | #if defined(CONFIG_CMD_KGDB) |
442 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
9553df86 JL |
443 | #endif |
444 | ||
445 | /* | |
446 | * Environment Configuration | |
447 | */ | |
448 | #define CONFIG_IPADDR 192.168.1.100 | |
449 | ||
450 | #define CONFIG_HOSTNAME unknown | |
8b3637c6 | 451 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 452 | #define CONFIG_BOOTFILE "uImage" |
9553df86 JL |
453 | #define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin |
454 | ||
455 | #define CONFIG_SERVERIP 192.168.1.1 | |
456 | #define CONFIG_GATEWAYIP 192.168.1.1 | |
457 | #define CONFIG_NETMASK 255.255.255.0 | |
458 | ||
459 | /* default location for tftp and bootm */ | |
e1efe43c | 460 | #define CONFIG_LOADADDR 0x10000000 |
9553df86 | 461 | |
9553df86 JL |
462 | #if defined(CONFIG_PCI1) |
463 | #define PCI_ENV \ | |
464 | "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \ | |
465 | "echo e;md ${a}e00 9\0" \ | |
466 | "pci1regs=setenv a e0008; run pcireg\0" \ | |
467 | "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \ | |
468 | "pci d.w $b.0 56 1\0" \ | |
469 | "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \ | |
470 | "pci w.w $b.0 56 ffff\0" \ | |
471 | "pci1err=setenv a e0008; run pcierr\0" \ | |
472 | "pci1errc=setenv a e0008; run pcierrc\0" | |
473 | #else | |
474 | #define PCI_ENV "" | |
475 | #endif | |
476 | ||
477 | #if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2) | |
478 | #define PCIE_ENV \ | |
479 | "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \ | |
480 | "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \ | |
481 | "pcie1regs=setenv a e000a; run pciereg\0" \ | |
482 | "pcie2regs=setenv a e0009; run pciereg\0" \ | |
483 | "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\ | |
484 | "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \ | |
485 | "pci d $b.0 130 1\0" \ | |
486 | "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\ | |
487 | "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \ | |
488 | "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \ | |
489 | "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \ | |
490 | "pcie1err=setenv a e000a; run pcieerr\0" \ | |
491 | "pcie2err=setenv a e0009; run pcieerr\0" \ | |
492 | "pcie1errc=setenv a e000a; run pcieerrc\0" \ | |
493 | "pcie2errc=setenv a e0009; run pcieerrc\0" | |
494 | #else | |
495 | #define PCIE_ENV "" | |
496 | #endif | |
497 | ||
498 | #define DMA_ENV \ | |
499 | "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\ | |
500 | "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \ | |
501 | "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\ | |
502 | "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \ | |
503 | "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\ | |
504 | "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \ | |
505 | "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\ | |
506 | "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0" | |
507 | ||
1815338f | 508 | #ifdef ENV_DEBUG |
9553df86 | 509 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
5368c55d MV |
510 | "netdev=eth0\0" \ |
511 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
512 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
513 | "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
514 | " +$filesize; " \ | |
515 | "erase " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
516 | " +$filesize; " \ | |
517 | "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
518 | " $filesize; " \ | |
519 | "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
520 | " +$filesize; " \ | |
521 | "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ | |
522 | " $filesize\0" \ | |
523 | "consoledev=ttyS0\0" \ | |
e1efe43c | 524 | "ramdiskaddr=0x18000000\0" \ |
5368c55d | 525 | "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ |
e1efe43c | 526 | "fdtaddr=0x17c00000\0" \ |
5368c55d MV |
527 | "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ |
528 | "bdev=sda3\0" \ | |
529 | "en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \ | |
530 | "dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \ | |
531 | "maxcpus=1" \ | |
532 | "eoi=mw e00400b0 0\0" \ | |
533 | "iack=md e00400a0 1\0" \ | |
534 | "ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \ | |
9553df86 JL |
535 | "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \ |
536 | "md ${a}f00 5\0" \ | |
5368c55d MV |
537 | "ddr1regs=setenv a e0002; run ddrreg\0" \ |
538 | "gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \ | |
9553df86 JL |
539 | "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \ |
540 | "md ${a}e60 1; md ${a}ef0 1d\0" \ | |
5368c55d MV |
541 | "guregs=setenv a e00e0; run gureg\0" \ |
542 | "mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \ | |
543 | "mcmregs=setenv a e0001; run mcmreg\0" \ | |
544 | "diuregs=md e002c000 1d\0" \ | |
545 | "dium=mw e002c01c\0" \ | |
546 | "diuerr=md e002c014 1\0" \ | |
547 | "pmregs=md e00e1000 2b\0" \ | |
548 | "lawregs=md e0000c08 4b\0" \ | |
549 | "lbcregs=md e0005000 36\0" \ | |
550 | "dma0regs=md e0021100 12\0" \ | |
551 | "dma1regs=md e0021180 12\0" \ | |
552 | "dma2regs=md e0021200 12\0" \ | |
553 | "dma3regs=md e0021280 12\0" \ | |
9553df86 JL |
554 | PCI_ENV \ |
555 | PCIE_ENV \ | |
556 | DMA_ENV | |
1815338f | 557 | #else |
5368c55d MV |
558 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
559 | "netdev=eth0\0" \ | |
560 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ | |
561 | "consoledev=ttyS0\0" \ | |
e1efe43c | 562 | "ramdiskaddr=0x18000000\0" \ |
5368c55d | 563 | "ramdiskfile=8610hpcd/ramdisk.uboot\0" \ |
e1efe43c | 564 | "fdtaddr=0x17c00000\0" \ |
5368c55d MV |
565 | "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \ |
566 | "bdev=sda3\0" | |
1815338f | 567 | #endif |
9553df86 JL |
568 | |
569 | #define CONFIG_NFSBOOTCOMMAND \ | |
570 | "setenv bootargs root=/dev/nfs rw " \ | |
571 | "nfsroot=$serverip:$rootpath " \ | |
572 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
573 | "console=$consoledev,$baudrate $othbootargs;" \ | |
574 | "tftp $loadaddr $bootfile;" \ | |
1df170f8 JL |
575 | "tftp $fdtaddr $fdtfile;" \ |
576 | "bootm $loadaddr - $fdtaddr" | |
9553df86 JL |
577 | |
578 | #define CONFIG_RAMBOOTCOMMAND \ | |
579 | "setenv bootargs root=/dev/ram rw " \ | |
580 | "console=$consoledev,$baudrate $othbootargs;" \ | |
581 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
582 | "tftp $loadaddr $bootfile;" \ | |
1df170f8 JL |
583 | "tftp $fdtaddr $fdtfile;" \ |
584 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
9553df86 JL |
585 | |
586 | #define CONFIG_BOOTCOMMAND \ | |
587 | "setenv bootargs root=/dev/$bdev rw " \ | |
588 | "console=$consoledev,$baudrate $othbootargs;" \ | |
589 | "tftp $loadaddr $bootfile;" \ | |
1df170f8 JL |
590 | "tftp $fdtaddr $fdtfile;" \ |
591 | "bootm $loadaddr - $fdtaddr" | |
9553df86 JL |
592 | |
593 | #endif /* __CONFIG_H */ |