projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 5c9efb36 | 1 | /* |
| 46f3e385 | 2 | * Copyright 2006, 2010 Freescale Semiconductor. |
| 5c9efb36 | 3 | * |
| debb7354 JL |
4 | * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) |
| 5 | * | |
| 6 | * See file CREDITS for list of people who contributed to this | |
| 7 | * project. | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or | |
| 10 | * modify it under the terms of the GNU General Public License as | |
| 11 | * published by the Free Software Foundation; either version 2 of | |
| 12 | * the License, or (at your option) any later version. | |
| 13 | * | |
| 14 | * This program is distributed in the hope that it will be useful, | |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 17 | * GNU General Public License for more details. | |
| 18 | * | |
| 19 | * You should have received a copy of the GNU General Public License | |
| 20 | * along with this program; if not, write to the Free Software | |
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 22 | * MA 02111-1307 USA | |
| 23 | */ | |
| 24 | ||
| 25 | /* | |
| 5c9efb36 | 26 | * MPC8641HPCN board configuration file |
| debb7354 JL |
27 | * |
| 28 | * Make sure you change the MAC address and other network params first, | |
| 29 | * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file. | |
| 30 | */ | |
| 31 | ||
| 32 | #ifndef __CONFIG_H | |
| 33 | #define __CONFIG_H | |
| 34 | ||
| 35 | /* High Level Configuration Options */ | |
| 36 | #define CONFIG_MPC86xx 1 /* MPC86xx */ | |
| 37 | #define CONFIG_MPC8641 1 /* MPC8641 specific */ | |
| 38 | #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ | |
| 7649a590 | 39 | #define CONFIG_MP 1 /* support multiple processors */ |
| 53677ef1 | 40 | #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ |
| 3111d32c | 41 | /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ |
| d591a80e | 42 | #define CONFIG_ADDR_MAP 1 /* Use addr map */ |
| debb7354 | 43 | |
| 2ae18241 WD |
44 | /* |
| 45 | * default CCSRBAR is at 0xff700000 | |
| 46 | * assume U-Boot is less than 0.5MB | |
| 47 | */ | |
| 48 | #define CONFIG_SYS_TEXT_BASE 0xeff00000 | |
| 49 | ||
| debb7354 | 50 | #ifdef RUN_DIAG |
| 6bf98b13 | 51 | #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE |
| debb7354 | 52 | #endif |
| 5c9efb36 | 53 | |
| 1266df88 BB |
54 | /* |
| 55 | * virtual address to be used for temporary mappings. There | |
| 56 | * should be 128k free at this VA. | |
| 57 | */ | |
| 58 | #define CONFIG_SYS_SCRATCH_VA 0xe0000000 | |
| 59 | ||
| af5d100e BB |
60 | /* |
| 61 | * set this to enable Rapid IO. PCI and RIO are mutually exclusive | |
| 62 | */ | |
| 63 | /*#define CONFIG_RIO 1*/ | |
| 64 | ||
| 65 | #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ | |
| 63cec581 | 66 | #define CONFIG_PCI 1 /* Enable PCI/PCIE */ |
| 46f3e385 KG |
67 | #define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ |
| 68 | #define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ | |
| 63cec581 | 69 | #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ |
| 8ba93f68 | 70 | #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ |
| af5d100e | 71 | #endif |
| 4933b91f | 72 | #define CONFIG_FSL_LAW 1 /* Use common FSL law init code */ |
| 5c9efb36 | 73 | |
| 53677ef1 | 74 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ |
| debb7354 | 75 | #define CONFIG_ENV_OVERWRITE |
| debb7354 | 76 | |
| 4bbfd3e2 | 77 | #define CONFIG_BAT_RW 1 /* Use common BAT rw code */ |
| 31d82672 | 78 | #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ |
| d591a80e | 79 | #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ |
| debb7354 | 80 | |
| 53677ef1 | 81 | #define CONFIG_ALTIVEC 1 |
| debb7354 | 82 | |
| 5c9efb36 | 83 | /* |
| debb7354 JL |
84 | * L2CR setup -- make sure this is right for your board! |
| 85 | */ | |
| 6d0f6bcf | 86 | #define CONFIG_SYS_L2 |
| debb7354 JL |
87 | #define L2_INIT 0 |
| 88 | #define L2_ENABLE (L2CR_L2E) | |
| 89 | ||
| 90 | #ifndef CONFIG_SYS_CLK_FREQ | |
| 63cec581 ES |
91 | #ifndef __ASSEMBLY__ |
| 92 | extern unsigned long get_board_sys_clk(unsigned long dummy); | |
| 93 | #endif | |
| 53677ef1 | 94 | #define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) |
| debb7354 JL |
95 | #endif |
| 96 | ||
| debb7354 JL |
97 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
| 98 | ||
| 6d0f6bcf JCPV |
99 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ |
| 100 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
| debb7354 | 101 | |
| 3111d32c BB |
102 | /* |
| 103 | * With the exception of PCI Memory and Rapid IO, most devices will simply | |
| 104 | * add CONFIG_SYS_PHYS_ADDR_HIGH to the front of the 32-bit VA to get the PA | |
| 105 | * when 36-bit is enabled. When 36-bit is not enabled, these bits are 0. | |
| 106 | */ | |
| 107 | #ifdef CONFIG_PHYS_64BIT | |
| 108 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0000000f00000000ULL | |
| 109 | #else | |
| 110 | #define CONFIG_SYS_PHYS_ADDR_HIGH 0x0 | |
| 111 | #endif | |
| 112 | ||
| debb7354 JL |
113 | /* |
| 114 | * Base addresses -- Note these are effective addresses where the | |
| 115 | * actual resources get mapped (not physical addresses) | |
| 116 | */ | |
| 6d0f6bcf | 117 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
| c759a01a | 118 | #define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ |
| 6d0f6bcf | 119 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ |
| debb7354 | 120 | |
| 3111d32c BB |
121 | /* Physical addresses */ |
| 122 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
| 123 | #ifdef CONFIG_PHYS_64BIT | |
| 124 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0xf | |
| d52082b1 BB |
125 | #define CONFIG_SYS_CCSRBAR_PHYS (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
| 126 | | ((u64)CONFIG_SYS_CCSRBAR_PHYS_HIGH << 32)) | |
| 3111d32c BB |
127 | #else |
| 128 | #define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0 | |
| d52082b1 | 129 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW |
| 3111d32c BB |
130 | #endif |
| 131 | ||
| 076bff8f YS |
132 | #define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ |
| 133 | ||
| debb7354 JL |
134 | /* |
| 135 | * DDR Setup | |
| 136 | */ | |
| 6a8e5692 KG |
137 | #define CONFIG_FSL_DDR2 |
| 138 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
| 139 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ | |
| 140 | #define CONFIG_DDR_SPD | |
| 141 | ||
| 142 | #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ | |
| 143 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
| 144 | ||
| 6d0f6bcf JCPV |
145 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
| 146 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
| 1266df88 | 147 | #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ |
| fcb28e76 | 148 | #define CONFIG_VERY_BIG_RAM |
| debb7354 | 149 | |
| 6a8e5692 KG |
150 | #define CONFIG_NUM_DDR_CONTROLLERS 2 |
| 151 | #define CONFIG_DIMM_SLOTS_PER_CTLR 2 | |
| 152 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
| 153 | ||
| 154 | /* | |
| 155 | * I2C addresses of SPD EEPROMs | |
| 156 | */ | |
| 157 | #define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ | |
| 158 | #define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 0 DIMM 1 */ | |
| 159 | #define SPD_EEPROM_ADDRESS3 0x53 /* CTLR 1 DIMM 0 */ | |
| 160 | #define SPD_EEPROM_ADDRESS4 0x54 /* CTLR 1 DIMM 1 */ | |
| 161 | ||
| 162 | ||
| 163 | /* | |
| 164 | * These are used when DDR doesn't use SPD. | |
| 165 | */ | |
| 6d0f6bcf JCPV |
166 | #define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */ |
| 167 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F | |
| 168 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */ | |
| 169 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
| 170 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 | |
| 171 | #define CONFIG_SYS_DDR_TIMING_1 0x39357322 | |
| 172 | #define CONFIG_SYS_DDR_TIMING_2 0x14904cc8 | |
| 173 | #define CONFIG_SYS_DDR_MODE_1 0x00480432 | |
| 174 | #define CONFIG_SYS_DDR_MODE_2 0x00000000 | |
| 175 | #define CONFIG_SYS_DDR_INTERVAL 0x06090100 | |
| 176 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
| 177 | #define CONFIG_SYS_DDR_CLK_CTRL 0x03800000 | |
| 178 | #define CONFIG_SYS_DDR_OCD_CTRL 0x00000000 | |
| 179 | #define CONFIG_SYS_DDR_OCD_STATUS 0x00000000 | |
| 180 | #define CONFIG_SYS_DDR_CONTROL 0xe3008000 /* Type = DDR2 */ | |
| 181 | #define CONFIG_SYS_DDR_CONTROL2 0x04400000 | |
| 6a8e5692 | 182 | |
| ad8f8687 | 183 | #define CONFIG_ID_EEPROM |
| 6d0f6bcf | 184 | #define CONFIG_SYS_I2C_EEPROM_NXID |
| 32628c50 | 185 | #define CONFIG_ID_EEPROM |
| 6d0f6bcf JCPV |
186 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 |
| 187 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
| debb7354 | 188 | |
| c759a01a | 189 | #define CONFIG_SYS_FLASH_BASE 0xef800000 /* start of FLASH 8M */ |
| 3111d32c BB |
190 | #define CONFIG_SYS_FLASH_BASE_PHYS (CONFIG_SYS_FLASH_BASE \ |
| 191 | | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| 192 | ||
| b81b773e | 193 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} |
| debb7354 | 194 | |
| 3111d32c BB |
195 | #define CONFIG_SYS_BR0_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 196 | | 0x00001001) /* port size 16bit */ | |
| 197 | #define CONFIG_SYS_OR0_PRELIM 0xff806ff7 /* 8MB Boot Flash area*/ | |
| debb7354 | 198 | |
| 3111d32c BB |
199 | #define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(CF_BASE_PHYS) \ |
| 200 | | 0x00001001) /* port size 16bit */ | |
| 201 | #define CONFIG_SYS_OR2_PRELIM 0xffffeff7 /* 32k Compact Flash */ | |
| debb7354 | 202 | |
| 3111d32c BB |
203 | #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \ |
| 204 | | 0x00000801) /* port size 8bit */ | |
| 205 | #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32k PIXIS area*/ | |
| debb7354 | 206 | |
| c759a01a BB |
207 | /* |
| 208 | * The LBC_BASE is the base of the region that contains the PIXIS and the CF. | |
| 209 | * The PIXIS and CF by themselves aren't large enough to take up the 128k | |
| 210 | * required for the smallest BAT mapping, so there's a 64k hole. | |
| 211 | */ | |
| 212 | #define CONFIG_SYS_LBC_BASE 0xffde0000 | |
| 3111d32c BB |
213 | #define CONFIG_SYS_LBC_BASE_PHYS (CONFIG_SYS_LBC_BASE \ |
| 214 | | CONFIG_SYS_PHYS_ADDR_HIGH) | |
| debb7354 | 215 | |
| 7608d75f | 216 | #define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ |
| c759a01a | 217 | #define PIXIS_BASE (CONFIG_SYS_LBC_BASE + 0x00010000) |
| 3111d32c | 218 | #define PIXIS_BASE_PHYS (CONFIG_SYS_LBC_BASE_PHYS + 0x00010000) |
| c759a01a | 219 | #define PIXIS_SIZE 0x00008000 /* 32k */ |
| 5c9efb36 JL |
220 | #define PIXIS_ID 0x0 /* Board ID at offset 0 */ |
| 221 | #define PIXIS_VER 0x1 /* Board version at offset 1 */ | |
| 222 | #define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ | |
| 223 | #define PIXIS_RST 0x4 /* PIXIS Reset Control register */ | |
| 224 | #define PIXIS_AUX 0x6 /* PIXIS Auxiliary register; Scratch register */ | |
| 225 | #define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ | |
| 226 | #define PIXIS_VCTL 0x10 /* VELA Control Register */ | |
| 227 | #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ | |
| 228 | #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ | |
| 229 | #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ | |
| 9af9c6bd KG |
230 | #define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ |
| 231 | #define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ | |
| 5c9efb36 JL |
232 | #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ |
| 233 | #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ | |
| 234 | #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ | |
| 235 | #define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ | |
| 6d0f6bcf | 236 | #define CONFIG_SYS_PIXIS_VBOOT_MASK 0x40 /* Reset altbank mask*/ |
| debb7354 | 237 | |
| b5431560 | 238 | /* Compact flash shares a BAT with PIXIS; make sure they're contiguous */ |
| c759a01a | 239 | #define CF_BASE (PIXIS_BASE + PIXIS_SIZE) |
| 3111d32c | 240 | #define CF_BASE_PHYS (PIXIS_BASE_PHYS + PIXIS_SIZE) |
| b5431560 | 241 | |
| 170deacb | 242 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ |
| 6d0f6bcf | 243 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ |
| debb7354 | 244 | |
| 6d0f6bcf JCPV |
245 | #undef CONFIG_SYS_FLASH_CHECKSUM |
| 246 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
| 247 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
| 14d0a02a | 248 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
| bf9a8c34 | 249 | #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ |
| debb7354 | 250 | |
| 00b1883a | 251 | #define CONFIG_FLASH_CFI_DRIVER |
| 6d0f6bcf JCPV |
252 | #define CONFIG_SYS_FLASH_CFI |
| 253 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
| debb7354 | 254 | |
| 6d0f6bcf JCPV |
255 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
| 256 | #define CONFIG_SYS_RAMBOOT | |
| debb7354 | 257 | #else |
| 6d0f6bcf | 258 | #undef CONFIG_SYS_RAMBOOT |
| debb7354 JL |
259 | #endif |
| 260 | ||
| 6d0f6bcf | 261 | #if defined(CONFIG_SYS_RAMBOOT) |
| fa7db9c3 | 262 | #undef CONFIG_SPD_EEPROM |
| 6d0f6bcf | 263 | #define CONFIG_SYS_SDRAM_SIZE 256 |
| debb7354 JL |
264 | #endif |
| 265 | ||
| 266 | #undef CONFIG_CLOCKS_IN_MHZ | |
| 267 | ||
| 6d0f6bcf JCPV |
268 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
| 269 | #ifndef CONFIG_SYS_INIT_RAM_LOCK | |
| 270 | #define CONFIG_SYS_INIT_RAM_ADDR 0x0fd00000 /* Initial RAM address */ | |
| debb7354 | 271 | #else |
| 6d0f6bcf | 272 | #define CONFIG_SYS_INIT_RAM_ADDR 0xf8400000 /* Initial RAM address */ |
| debb7354 | 273 | #endif |
| 553f0982 | 274 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
| debb7354 | 275 | |
| 25ddd1fb | 276 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
| 6d0f6bcf | 277 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
| debb7354 | 278 | |
| 6d0f6bcf JCPV |
279 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
| 280 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ | |
| debb7354 JL |
281 | |
| 282 | /* Serial Port */ | |
| 283 | #define CONFIG_CONS_INDEX 1 | |
| 6d0f6bcf JCPV |
284 | #define CONFIG_SYS_NS16550 |
| 285 | #define CONFIG_SYS_NS16550_SERIAL | |
| 286 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
| 287 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
| debb7354 | 288 | |
| 6d0f6bcf | 289 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
| debb7354 JL |
290 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} |
| 291 | ||
| 6d0f6bcf JCPV |
292 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
| 293 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
| debb7354 JL |
294 | |
| 295 | /* Use the HUSH parser */ | |
| 6d0f6bcf JCPV |
296 | #define CONFIG_SYS_HUSH_PARSER |
| 297 | #ifdef CONFIG_SYS_HUSH_PARSER | |
| 298 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
| debb7354 JL |
299 | #endif |
| 300 | ||
| 5c9efb36 JL |
301 | /* |
| 302 | * Pass open firmware flat tree to kernel | |
| 303 | */ | |
| ea9f7395 JL |
304 | #define CONFIG_OF_LIBFDT 1 |
| 305 | #define CONFIG_OF_BOARD_SETUP 1 | |
| 306 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
| debb7354 | 307 | |
| 586d1d5a JL |
308 | /* |
| 309 | * I2C | |
| 310 | */ | |
| 20476726 JL |
311 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
| 312 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
| debb7354 | 313 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
| 6d0f6bcf JCPV |
314 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 315 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
| 316 | #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */ | |
| 317 | #define CONFIG_SYS_I2C_OFFSET 0x3100 | |
| debb7354 | 318 | |
| 586d1d5a JL |
319 | /* |
| 320 | * RapidIO MMU | |
| 321 | */ | |
| c759a01a | 322 | #define CONFIG_SYS_RIO_MEM_BASE 0x80000000 /* base address */ |
| 3111d32c BB |
323 | #ifdef CONFIG_PHYS_64BIT |
| 324 | #define CONFIG_SYS_RIO_MEM_PHYS 0x0000000c00000000ULL | |
| 325 | #else | |
| 6d0f6bcf | 326 | #define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE |
| 3111d32c | 327 | #endif |
| 6d0f6bcf | 328 | #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */ |
| debb7354 JL |
329 | |
| 330 | /* | |
| 331 | * General PCI | |
| 332 | * Addresses are mapped 1-1. | |
| 333 | */ | |
| 49f46f3b | 334 | |
| 64e55d5e | 335 | #define CONFIG_SYS_PCIE1_NAME "ULI" |
| 46f3e385 | 336 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 |
| 3111d32c | 337 | #ifdef CONFIG_PHYS_64BIT |
| 46f3e385 KG |
338 | #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 |
| 339 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL | |
| 3111d32c | 340 | #else |
| 46f3e385 KG |
341 | #define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT |
| 342 | #define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT | |
| 3111d32c | 343 | #endif |
| 46f3e385 KG |
344 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ |
| 345 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
| 346 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
| 347 | #define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ | |
| 3111d32c | 348 | | CONFIG_SYS_PHYS_ADDR_HIGH) |
| 46f3e385 | 349 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ |
| debb7354 | 350 | |
| 4c78d4a6 BB |
351 | #ifdef CONFIG_PHYS_64BIT |
| 352 | /* | |
| 46f3e385 | 353 | * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. |
| 4c78d4a6 BB |
354 | * This will increase the amount of PCI address space available for |
| 355 | * for mapping RAM. | |
| 356 | */ | |
| 46f3e385 | 357 | #define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS |
| 4c78d4a6 | 358 | #else |
| 46f3e385 KG |
359 | #define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ |
| 360 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 4c78d4a6 | 361 | #endif |
| 46f3e385 KG |
362 | #define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ |
| 363 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 364 | #define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ | |
| 365 | + CONFIG_SYS_PCIE1_MEM_SIZE) | |
| 366 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
| 367 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
| 368 | #define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ | |
| 369 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
| 370 | #define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ | |
| 371 | + CONFIG_SYS_PCIE1_IO_SIZE) | |
| 372 | #define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE | |
| debb7354 | 373 | |
| debb7354 JL |
374 | #if defined(CONFIG_PCI) |
| 375 | ||
| 53677ef1 | 376 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| debb7354 | 377 | |
| 6d0f6bcf | 378 | #undef CONFIG_SYS_SCSI_SCAN_BUS_REVERSE |
| debb7354 JL |
379 | |
| 380 | #define CONFIG_NET_MULTI | |
| 53677ef1 | 381 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
| debb7354 JL |
382 | |
| 383 | #define CONFIG_RTL8139 | |
| 384 | ||
| debb7354 JL |
385 | #undef CONFIG_EEPRO100 |
| 386 | #undef CONFIG_TULIP | |
| 387 | ||
| a81d1c0b ZW |
388 | /************************************************************ |
| 389 | * USB support | |
| 390 | ************************************************************/ | |
| 53677ef1 | 391 | #define CONFIG_PCI_OHCI 1 |
| a81d1c0b | 392 | #define CONFIG_USB_OHCI_NEW 1 |
| 53677ef1 | 393 | #define CONFIG_USB_KEYBOARD 1 |
| 52cb4d4f | 394 | #define CONFIG_SYS_STDIO_DEREGISTER |
| 6d0f6bcf JCPV |
395 | #define CONFIG_SYS_USB_EVENT_POLL 1 |
| 396 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" | |
| 397 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 | |
| 398 | #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 | |
| a81d1c0b | 399 | |
| 0f460a1e | 400 | /*PCIE video card used*/ |
| 46f3e385 | 401 | #define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT |
| 0f460a1e JJ |
402 | |
| 403 | /*PCI video card used*/ | |
| 46f3e385 | 404 | /*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ |
| 0f460a1e JJ |
405 | |
| 406 | /* video */ | |
| 407 | #define CONFIG_VIDEO | |
| 408 | ||
| 409 | #if defined(CONFIG_VIDEO) | |
| 410 | #define CONFIG_BIOSEMU | |
| 411 | #define CONFIG_CFB_CONSOLE | |
| 412 | #define CONFIG_VIDEO_SW_CURSOR | |
| 413 | #define CONFIG_VGA_AS_SINGLE_DEVICE | |
| 414 | #define CONFIG_ATI_RADEON_FB | |
| 415 | #define CONFIG_VIDEO_LOGO | |
| 416 | /*#define CONFIG_CONSOLE_CURSOR*/ | |
| 46f3e385 | 417 | #define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT |
| 0f460a1e JJ |
418 | #endif |
| 419 | ||
| debb7354 | 420 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
| debb7354 | 421 | |
| dabf9ef8 JZ |
422 | #define CONFIG_DOS_PARTITION |
| 423 | #define CONFIG_SCSI_AHCI | |
| 424 | ||
| 425 | #ifdef CONFIG_SCSI_AHCI | |
| 426 | #define CONFIG_SATA_ULI5288 | |
| 6d0f6bcf JCPV |
427 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 |
| 428 | #define CONFIG_SYS_SCSI_MAX_LUN 1 | |
| 429 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) | |
| 430 | #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE | |
| dabf9ef8 JZ |
431 | #endif |
| 432 | ||
| debb7354 JL |
433 | #endif /* CONFIG_PCI */ |
| 434 | ||
| debb7354 JL |
435 | #if defined(CONFIG_TSEC_ENET) |
| 436 | ||
| 437 | #ifndef CONFIG_NET_MULTI | |
| 53677ef1 | 438 | #define CONFIG_NET_MULTI 1 |
| debb7354 JL |
439 | #endif |
| 440 | ||
| 441 | #define CONFIG_MII 1 /* MII PHY management */ | |
| 442 | ||
| 53677ef1 WD |
443 | #define CONFIG_TSEC1 1 |
| 444 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
| 445 | #define CONFIG_TSEC2 1 | |
| 446 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
| 447 | #define CONFIG_TSEC3 1 | |
| 448 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
| 449 | #define CONFIG_TSEC4 1 | |
| 450 | #define CONFIG_TSEC4_NAME "eTSEC4" | |
| debb7354 | 451 | |
| debb7354 JL |
452 | #define TSEC1_PHY_ADDR 0 |
| 453 | #define TSEC2_PHY_ADDR 1 | |
| 454 | #define TSEC3_PHY_ADDR 2 | |
| 455 | #define TSEC4_PHY_ADDR 3 | |
| 456 | #define TSEC1_PHYIDX 0 | |
| 457 | #define TSEC2_PHYIDX 0 | |
| 458 | #define TSEC3_PHYIDX 0 | |
| 459 | #define TSEC4_PHYIDX 0 | |
| 3a79013e AF |
460 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) |
| 461 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 462 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| 463 | #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
| debb7354 JL |
464 | |
| 465 | #define CONFIG_ETHPRIME "eTSEC1" | |
| 466 | ||
| 467 | #endif /* CONFIG_TSEC_ENET */ | |
| 468 | ||
| 3111d32c BB |
469 | /* Contort an addr into the format needed for BATs */ |
| 470 | #ifdef CONFIG_PHYS_64BIT | |
| 471 | #define BAT_PHYS_ADDR(x) ((unsigned long) \ | |
| 472 | ((x & 0x00000000ffffffffULL) | \ | |
| 473 | ((x & 0x0000000e00000000ULL) >> 24) | \ | |
| 474 | ((x & 0x0000000100000000ULL) >> 30))) | |
| 475 | #else | |
| 476 | #define BAT_PHYS_ADDR(x) (x) | |
| 477 | #endif | |
| 478 | ||
| 479 | ||
| 480 | /* Put high physical address bits into the BAT format */ | |
| 481 | #define PHYS_HIGH_TO_BXPN(x) ((x & 0x0000000e) << 8) | |
| 482 | #define PHYS_HIGH_TO_BX(x) ((x & 0x00000001) << 2) | |
| 483 | ||
| 586d1d5a | 484 | /* |
| c759a01a | 485 | * BAT0 DDR |
| debb7354 | 486 | */ |
| 6d0f6bcf | 487 | #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| 9ff32d8c | 488 | #define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) |
| debb7354 | 489 | |
| 586d1d5a | 490 | /* |
| c759a01a | 491 | * BAT1 LBC (PIXIS/CF) |
| af5d100e | 492 | */ |
| 3111d32c BB |
493 | #define CONFIG_SYS_DBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ |
| 494 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ | |
| 495 | BATL_GUARDEDSTORAGE) | |
| c759a01a BB |
496 | #define CONFIG_SYS_DBAT1U (CONFIG_SYS_LBC_BASE | BATU_BL_128K \ |
| 497 | | BATU_VS | BATU_VP) | |
| 3111d32c BB |
498 | #define CONFIG_SYS_IBAT1L (BAT_PHYS_ADDR(CONFIG_SYS_LBC_BASE_PHYS) \ |
| 499 | | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| c759a01a | 500 | #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U |
| af5d100e BB |
501 | |
| 502 | /* if CONFIG_PCI: | |
| 46f3e385 | 503 | * BAT2 PCIE1 and PCIE1 MEM |
| af5d100e | 504 | * if CONFIG_RIO |
| c759a01a | 505 | * BAT2 Rapidio Memory |
| debb7354 | 506 | */ |
| af5d100e | 507 | #ifdef CONFIG_PCI |
| 46f3e385 | 508 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ |
| 3111d32c BB |
509 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 510 | | BATL_GUARDEDSTORAGE) | |
| 46f3e385 | 511 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ |
| af5d100e | 512 | | BATU_VS | BATU_VP) |
| 46f3e385 | 513 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ |
| 3111d32c | 514 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| af5d100e BB |
515 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U |
| 516 | #else /* CONFIG_RIO */ | |
| 3111d32c BB |
517 | #define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ |
| 518 | | BATL_PP_RW | BATL_CACHEINHIBIT | \ | |
| 519 | BATL_GUARDEDSTORAGE) | |
| 520 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_BASE | BATU_BL_512M \ | |
| 521 | | BATU_VS | BATU_VP) | |
| 522 | #define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_RIO_MEM_PHYS) \ | |
| 523 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 524 | ||
| 6d0f6bcf | 525 | #define CONFIG_SYS_DBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW \ |
| 5c9efb36 | 526 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
| 6d0f6bcf JCPV |
527 | #define CONFIG_SYS_DBAT2U (CONFIG_SYS_RIO_MEM_PHYS | BATU_BL_512M | BATU_VS | BATU_VP) |
| 528 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_RIO_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 529 | #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U | |
| af5d100e | 530 | #endif |
| debb7354 | 531 | |
| 586d1d5a | 532 | /* |
| c759a01a | 533 | * BAT3 CCSR Space |
| 3111d32c BB |
534 | * This BAT is used early; don't use any macros with ULL - use HIGH/LOW pairs |
| 535 | * instead. The assembler chokes on ULL. | |
| debb7354 | 536 | */ |
| 3111d32c BB |
537 | #define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
| 538 | | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 539 | | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 540 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 541 | | BATL_GUARDEDSTORAGE) | |
| c759a01a BB |
542 | #define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS \ |
| 543 | | BATU_VP) | |
| 3111d32c BB |
544 | #define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR_PHYS_LOW \ |
| 545 | | PHYS_HIGH_TO_BXPN(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 546 | | PHYS_HIGH_TO_BX(CONFIG_SYS_CCSRBAR_PHYS_HIGH) \ | |
| 547 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 6d0f6bcf | 548 | #define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U |
| debb7354 | 549 | |
| 3111d32c BB |
550 | #if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR) |
| 551 | #define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 552 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 553 | | BATL_GUARDEDSTORAGE) | |
| 554 | #define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 555 | | BATU_BL_1M | BATU_VS | BATU_VP) | |
| 556 | #define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \ | |
| 557 | | BATL_PP_RW | BATL_CACHEINHIBIT) | |
| 558 | #define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU | |
| 559 | #endif | |
| 560 | ||
| 586d1d5a | 561 | /* |
| 46f3e385 | 562 | * BAT4 PCIE1_IO and PCIE2_IO |
| debb7354 | 563 | */ |
| 46f3e385 | 564 | #define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ |
| 3111d32c BB |
565 | | BATL_PP_RW | BATL_CACHEINHIBIT \ |
| 566 | | BATL_GUARDEDSTORAGE) | |
| 46f3e385 | 567 | #define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ |
| c759a01a | 568 | | BATU_VS | BATU_VP) |
| 46f3e385 | 569 | #define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ |
| 3111d32c | 570 | | BATL_PP_RW | BATL_CACHEINHIBIT) |
| 6d0f6bcf | 571 | #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U |
| debb7354 | 572 | |
| 586d1d5a | 573 | /* |
| c759a01a | 574 | * BAT5 Init RAM for stack in the CPU DCache (no backing memory) |
| debb7354 | 575 | */ |
| 6d0f6bcf JCPV |
576 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) |
| 577 | #define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) | |
| 578 | #define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L | |
| 579 | #define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U | |
| debb7354 | 580 | |
| 586d1d5a | 581 | /* |
| c759a01a | 582 | * BAT6 FLASH |
| debb7354 | 583 | */ |
| 3111d32c BB |
584 | #define CONFIG_SYS_DBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 585 | | BATL_PP_RW | BATL_CACHEINHIBIT \ | |
| 586 | | BATL_GUARDEDSTORAGE) | |
| 170deacb BB |
587 | #define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | BATU_VS \ |
| 588 | | BATU_VP) | |
| 3111d32c BB |
589 | #define CONFIG_SYS_IBAT6L (BAT_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \ |
| 590 | | BATL_PP_RW | BATL_MEMCOHERENCE) | |
| 6d0f6bcf | 591 | #define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U |
| debb7354 | 592 | |
| bf9a8c34 BB |
593 | /* Map the last 1M of flash where we're running from reset */ |
| 594 | #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | |
| 595 | | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | |
| 14d0a02a | 596 | #define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) |
| bf9a8c34 BB |
597 | #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ |
| 598 | | BATL_MEMCOHERENCE) | |
| 599 | #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY | |
| 600 | ||
| c759a01a BB |
601 | /* |
| 602 | * BAT7 FREE - used later for tmp mappings | |
| 603 | */ | |
| 6d0f6bcf JCPV |
604 | #define CONFIG_SYS_DBAT7L 0x00000000 |
| 605 | #define CONFIG_SYS_DBAT7U 0x00000000 | |
| 606 | #define CONFIG_SYS_IBAT7L 0x00000000 | |
| 607 | #define CONFIG_SYS_IBAT7U 0x00000000 | |
| debb7354 | 608 | |
| debb7354 JL |
609 | /* |
| 610 | * Environment | |
| 611 | */ | |
| 6d0f6bcf | 612 | #ifndef CONFIG_SYS_RAMBOOT |
| 5a1aceb0 | 613 | #define CONFIG_ENV_IS_IN_FLASH 1 |
| 6d0f6bcf | 614 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000) |
| 0e8d1586 | 615 | #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ |
| 5c9efb36 | 616 | #else |
| 93f6d725 | 617 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
| 6d0f6bcf | 618 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) |
| 5c9efb36 | 619 | #endif |
| 0f2d6602 | 620 | #define CONFIG_ENV_SIZE 0x2000 |
| debb7354 JL |
621 | |
| 622 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
| 6d0f6bcf | 623 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
| debb7354 | 624 | |
| 2f9c19e4 | 625 | |
| 659e2f67 JL |
626 | /* |
| 627 | * BOOTP options | |
| 628 | */ | |
| 629 | #define CONFIG_BOOTP_BOOTFILESIZE | |
| 630 | #define CONFIG_BOOTP_BOOTPATH | |
| 631 | #define CONFIG_BOOTP_GATEWAY | |
| 632 | #define CONFIG_BOOTP_HOSTNAME | |
| 633 | ||
| 634 | ||
| 2f9c19e4 JL |
635 | /* |
| 636 | * Command line configuration. | |
| 637 | */ | |
| 638 | #include <config_cmd_default.h> | |
| 639 | ||
| 640 | #define CONFIG_CMD_PING | |
| 641 | #define CONFIG_CMD_I2C | |
| 4f93f8b1 | 642 | #define CONFIG_CMD_REGINFO |
| 2f9c19e4 | 643 | |
| 6d0f6bcf | 644 | #if defined(CONFIG_SYS_RAMBOOT) |
| bdab39d3 | 645 | #undef CONFIG_CMD_SAVEENV |
| 2f9c19e4 JL |
646 | #endif |
| 647 | ||
| 648 | #if defined(CONFIG_PCI) | |
| 649 | #define CONFIG_CMD_PCI | |
| 650 | #define CONFIG_CMD_SCSI | |
| 651 | #define CONFIG_CMD_EXT2 | |
| bbf4796f | 652 | #define CONFIG_CMD_USB |
| debb7354 JL |
653 | #endif |
| 654 | ||
| debb7354 JL |
655 | |
| 656 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
| 657 | ||
| 658 | /* | |
| 659 | * Miscellaneous configurable options | |
| 660 | */ | |
| 6d0f6bcf | 661 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
| 53677ef1 | 662 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ |
| 6d0f6bcf JCPV |
663 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ |
| 664 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
| debb7354 | 665 | |
| 2f9c19e4 | 666 | #if defined(CONFIG_CMD_KGDB) |
| 6d0f6bcf | 667 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
| debb7354 | 668 | #else |
| 6d0f6bcf | 669 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
| debb7354 JL |
670 | #endif |
| 671 | ||
| 6d0f6bcf JCPV |
672 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
| 673 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
| 674 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
| 675 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ | |
| debb7354 JL |
676 | |
| 677 | /* | |
| 678 | * For booting Linux, the board info and command line data | |
| 679 | * have to be in the first 8 MB of memory, since this is | |
| 680 | * the maximum mapped by the Linux kernel during initialization. | |
| 681 | */ | |
| 6d0f6bcf | 682 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
| debb7354 | 683 | |
| 2f9c19e4 JL |
684 | #if defined(CONFIG_CMD_KGDB) |
| 685 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
| 686 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
| debb7354 JL |
687 | #endif |
| 688 | ||
| debb7354 JL |
689 | /* |
| 690 | * Environment Configuration | |
| 691 | */ | |
| 692 | ||
| 693 | /* The mac addresses for all ethernet interface */ | |
| 694 | #if defined(CONFIG_TSEC_ENET) | |
| 53677ef1 | 695 | #define CONFIG_ETHADDR 00:E0:0C:00:00:01 |
| debb7354 JL |
696 | #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD |
| 697 | #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD | |
| 698 | #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD | |
| 699 | #endif | |
| 700 | ||
| 10327dc5 | 701 | #define CONFIG_HAS_ETH0 1 |
| 5c9efb36 JL |
702 | #define CONFIG_HAS_ETH1 1 |
| 703 | #define CONFIG_HAS_ETH2 1 | |
| 704 | #define CONFIG_HAS_ETH3 1 | |
| debb7354 | 705 | |
| 18b6c8cd | 706 | #define CONFIG_IPADDR 192.168.1.100 |
| debb7354 JL |
707 | |
| 708 | #define CONFIG_HOSTNAME unknown | |
| 709 | #define CONFIG_ROOTPATH /opt/nfsroot | |
| 710 | #define CONFIG_BOOTFILE uImage | |
| 32922cdc | 711 | #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ |
| debb7354 | 712 | |
| 5c9efb36 | 713 | #define CONFIG_SERVERIP 192.168.1.1 |
| 18b6c8cd | 714 | #define CONFIG_GATEWAYIP 192.168.1.1 |
| 5c9efb36 | 715 | #define CONFIG_NETMASK 255.255.255.0 |
| debb7354 | 716 | |
| 5c9efb36 JL |
717 | /* default location for tftp and bootm */ |
| 718 | #define CONFIG_LOADADDR 1000000 | |
| debb7354 JL |
719 | |
| 720 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
| 53677ef1 | 721 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
| debb7354 JL |
722 | |
| 723 | #define CONFIG_BAUDRATE 115200 | |
| 724 | ||
| 53677ef1 WD |
725 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 726 | "netdev=eth0\0" \ | |
| 727 | "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ | |
| 728 | "tftpflash=tftpboot $loadaddr $uboot; " \ | |
| 14d0a02a WD |
729 | "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ |
| 730 | "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 731 | "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ | |
| 732 | "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ | |
| 733 | "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ | |
| 53677ef1 WD |
734 | "consoledev=ttyS0\0" \ |
| 735 | "ramdiskaddr=2000000\0" \ | |
| 736 | "ramdiskfile=your.ramdisk.u-boot\0" \ | |
| 737 | "fdtaddr=c00000\0" \ | |
| 738 | "fdtfile=mpc8641_hpcn.dtb\0" \ | |
| 3111d32c BB |
739 | "en-wd=mw.b ffdf0010 0x08; echo -expect:- 08; md.b ffdf0010 1\0" \ |
| 740 | "dis-wd=mw.b ffdf0010 0x00; echo -expect:- 00; md.b ffdf0010 1\0" \ | |
| 53677ef1 WD |
741 | "maxcpus=2" |
| 742 | ||
| 743 | ||
| 744 | #define CONFIG_NFSBOOTCOMMAND \ | |
| 745 | "setenv bootargs root=/dev/nfs rw " \ | |
| 746 | "nfsroot=$serverip:$rootpath " \ | |
| 747 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ | |
| 748 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 749 | "tftp $loadaddr $bootfile;" \ | |
| 750 | "tftp $fdtaddr $fdtfile;" \ | |
| 751 | "bootm $loadaddr - $fdtaddr" | |
| 752 | ||
| 753 | #define CONFIG_RAMBOOTCOMMAND \ | |
| 754 | "setenv bootargs root=/dev/ram rw " \ | |
| 755 | "console=$consoledev,$baudrate $othbootargs;" \ | |
| 756 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
| 757 | "tftp $loadaddr $bootfile;" \ | |
| 758 | "tftp $fdtaddr $fdtfile;" \ | |
| 759 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
| debb7354 JL |
760 | |
| 761 | #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND | |
| 762 | ||
| 763 | #endif /* __CONFIG_H */ |