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c005b939 AS |
1 | /* |
2 | * Copyright (C) Matrix Vision GmbH 2008 | |
3 | * | |
4 | * Matrix Vision mvBlueLYNX-M7 configuration file | |
5 | * based on Freescale's MPC8349ITX. | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
5ed546fd | 30 | #include <version.h> |
c005b939 AS |
31 | |
32 | /* | |
33 | * High Level Configuration Options | |
34 | */ | |
35 | #define CONFIG_E300 1 | |
0f898604 | 36 | #define CONFIG_MPC83xx 1 |
2c7920af | 37 | #define CONFIG_MPC834x 1 |
c005b939 AS |
38 | #define CONFIG_MPC8343 1 |
39 | ||
6d0f6bcf | 40 | #define CONFIG_SYS_IMMR 0xE0000000 |
c005b939 AS |
41 | |
42 | #define CONFIG_PCI | |
c005b939 AS |
43 | #define CONFIG_PCI_SKIP_HOST_BRIDGE |
44 | #define CONFIG_HARD_I2C | |
45 | #define CONFIG_TSEC_ENET | |
46 | #define CONFIG_MPC8XXX_SPI | |
47 | #define CONFIG_HARD_SPI | |
48 | #define MVBLM7_MMC_CS 0x04000000 | |
28887d83 | 49 | #define CONFIG_MISC_INIT_R |
c005b939 AS |
50 | |
51 | /* I2C */ | |
c005b939 AS |
52 | #define CONFIG_FSL_I2C |
53 | #define CONFIG_I2C_MULTI_BUS | |
6d0f6bcf JCPV |
54 | #define CONFIG_SYS_I2C_OFFSET 0x3000 |
55 | #define CONFIG_SYS_I2C2_OFFSET 0x3100 | |
c005b939 | 56 | |
6d0f6bcf JCPV |
57 | #define CONFIG_SYS_I2C_SPEED 100000 |
58 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
c005b939 AS |
59 | |
60 | /* | |
61 | * DDR Setup | |
62 | */ | |
28887d83 AS |
63 | #undef CONFIG_SPD_EEPROM |
64 | ||
6d0f6bcf JCPV |
65 | #define CONFIG_SYS_DDR_BASE 0x00000000 |
66 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
67 | #define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE | |
68 | #define CONFIG_SYS_83XX_DDR_USES_CS0 1 | |
69 | #define CONFIG_SYS_MEMTEST_START (60<<20) | |
70 | #define CONFIG_SYS_MEMTEST_END (70<<20) | |
28887d83 | 71 | #define CONFIG_VERY_BIG_RAM |
6d0f6bcf | 72 | |
28887d83 AS |
73 | #define CONFIG_SYS_DDRCDR 0x22000001 |
74 | #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 | |
c005b939 | 75 | |
28887d83 | 76 | #define CONFIG_SYS_DDR_SIZE 512 |
c005b939 | 77 | |
28887d83 | 78 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202 |
c005b939 | 79 | |
28887d83 | 80 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f |
c005b939 | 81 | |
28887d83 AS |
82 | #define CONFIG_SYS_DDR_TIMING_0 0x00260802 |
83 | #define CONFIG_SYS_DDR_TIMING_1 0x3837c322 | |
84 | #define CONFIG_SYS_DDR_TIMING_2 0x0f9848c6 | |
85 | #define CONFIG_SYS_DDR_TIMING_3 0x00000000 | |
c005b939 | 86 | |
28887d83 | 87 | #define CONFIG_SYS_DDR_SDRAM_CFG 0x43080008 |
6d0f6bcf | 88 | #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 |
28887d83 | 89 | #define CONFIG_SYS_DDR_INTERVAL 0x02000100 |
c005b939 | 90 | |
28887d83 AS |
91 | #define CONFIG_SYS_DDR_MODE 0x04040242 |
92 | #define CONFIG_SYS_DDR_MODE2 0x00800000 | |
c005b939 AS |
93 | |
94 | /* Flash */ | |
6d0f6bcf | 95 | #define CONFIG_SYS_FLASH_CFI |
00b1883a | 96 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
97 | #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT |
98 | ||
99 | #define CONFIG_SYS_FLASH_BASE 0xFF800000 | |
100 | #define CONFIG_SYS_FLASH_SIZE 8 | |
101 | #define CONFIG_SYS_FLASH_SIZE_SHIFT 3 | |
102 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
103 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 | |
104 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 | |
105 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
106 | #define CONFIG_SYS_MAX_FLASH_SECT 256 | |
107 | ||
108 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) | |
109 | #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) | OR_UPM_XAM | \ | |
2329fe11 | 110 | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS|\ |
c005b939 AS |
111 | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | \ |
112 | OR_GPCM_EAD) | |
6d0f6bcf JCPV |
113 | #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE |
114 | #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | (0x13 + CONFIG_SYS_FLASH_SIZE_SHIFT)) | |
c005b939 AS |
115 | |
116 | /* | |
117 | * U-Boot memory configuration | |
118 | */ | |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_MONITOR_BASE TEXT_BASE |
120 | #undef CONFIG_SYS_RAMBOOT | |
c005b939 | 121 | |
6d0f6bcf JCPV |
122 | #define CONFIG_SYS_INIT_RAM_LOCK |
123 | #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ | |
124 | #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ | |
c005b939 | 125 | |
6d0f6bcf JCPV |
126 | #define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ |
127 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) | |
128 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
c005b939 | 129 | |
6d0f6bcf JCPV |
130 | /* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */ |
131 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
132 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
c005b939 AS |
133 | |
134 | /* | |
135 | * Local Bus LCRR and LBCR regs | |
136 | * LCRR: DLL bypass, Clock divider is 4 | |
137 | * External Local Bus rate is | |
138 | * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV | |
139 | */ | |
c7190f02 KP |
140 | #define CONFIG_SYS_LCRR_DBYP LCRR_DBYP |
141 | #define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 | |
6d0f6bcf | 142 | #define CONFIG_SYS_LBC_LBCR 0x00000000 |
c005b939 AS |
143 | |
144 | /* LB sdram refresh timer, about 6us */ | |
6d0f6bcf | 145 | #define CONFIG_SYS_LBC_LSRT 0x32000000 |
c005b939 | 146 | /* LB refresh timer prescal, 266MHz/32*/ |
6d0f6bcf | 147 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 |
c005b939 AS |
148 | |
149 | /* | |
150 | * Serial Port | |
151 | */ | |
152 | #define CONFIG_CONS_INDEX 1 | |
6d0f6bcf JCPV |
153 | #define CONFIG_SYS_NS16550 |
154 | #define CONFIG_SYS_NS16550_SERIAL | |
155 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
156 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
c005b939 | 157 | |
6d0f6bcf | 158 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
c005b939 AS |
159 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
160 | ||
161 | #define CONFIG_CONSOLE ttyS0 | |
162 | #define CONFIG_BAUDRATE 115200 | |
163 | ||
6d0f6bcf JCPV |
164 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) |
165 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) | |
c005b939 AS |
166 | |
167 | /* pass open firmware flat tree */ | |
168 | #define CONFIG_OF_LIBFDT 1 | |
169 | #define CONFIG_OF_BOARD_SETUP 1 | |
170 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
171 | #define MV_DTB_NAME "mvblm7.dtb" | |
172 | ||
173 | /* | |
174 | * PCI | |
175 | */ | |
6d0f6bcf JCPV |
176 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
177 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
178 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 | |
179 | #define CONFIG_SYS_PCI1_MMIO_BASE (CONFIG_SYS_PCI1_MEM_BASE + CONFIG_SYS_PCI1_MEM_SIZE) | |
180 | #define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE | |
181 | #define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 | |
182 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
183 | #define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000 | |
184 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 | |
c005b939 | 185 | |
c005b939 AS |
186 | #define CONFIG_NET_MULTI 1 |
187 | #define CONFIG_NET_RETRY_COUNT 3 | |
188 | ||
189 | #define PCI_66M | |
190 | #define CONFIG_83XX_CLKIN 66666667 | |
191 | #define CONFIG_PCI_PNP | |
192 | #define CONFIG_PCI_SCAN_SHOW | |
193 | ||
194 | /* TSEC */ | |
195 | #define CONFIG_GMII | |
6d0f6bcf JCPV |
196 | #define CONFIG_SYS_VSC8601_SKEWFIX |
197 | #define CONFIG_SYS_VSC8601_SKEW_TX 3 | |
198 | #define CONFIG_SYS_VSC8601_SKEW_RX 3 | |
c005b939 AS |
199 | |
200 | #define CONFIG_TSEC1 | |
201 | #define CONFIG_TSEC2 | |
202 | ||
203 | #define CONFIG_HAS_ETH0 | |
204 | #define CONFIG_TSEC1_NAME "TSEC0" | |
205 | #define CONFIG_FEC1_PHY_NORXERR | |
6d0f6bcf JCPV |
206 | #define CONFIG_SYS_TSEC1_OFFSET 0x24000 |
207 | #define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) | |
c005b939 AS |
208 | #define TSEC1_PHY_ADDR 0x10 |
209 | #define TSEC1_PHYIDX 0 | |
210 | #define TSEC1_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) | |
211 | ||
212 | #define CONFIG_HAS_ETH1 | |
213 | #define CONFIG_TSEC2_NAME "TSEC1" | |
214 | #define CONFIG_FEC2_PHY_NORXERR | |
6d0f6bcf JCPV |
215 | #define CONFIG_SYS_TSEC2_OFFSET 0x25000 |
216 | #define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) | |
c005b939 AS |
217 | #define TSEC2_PHY_ADDR 0x11 |
218 | #define TSEC2_PHYIDX 0 | |
219 | #define TSEC2_FLAGS (TSEC_GIGABIT|TSEC_REDUCED) | |
220 | ||
221 | #define CONFIG_ETHPRIME "TSEC0" | |
222 | ||
223 | #define CONFIG_BOOTP_VENDOREX | |
224 | #define CONFIG_BOOTP_SUBNETMASK | |
225 | #define CONFIG_BOOTP_GATEWAY | |
226 | #define CONFIG_BOOTP_DNS | |
227 | #define CONFIG_BOOTP_DNS2 | |
228 | #define CONFIG_BOOTP_HOSTNAME | |
229 | #define CONFIG_BOOTP_BOOTFILESIZE | |
230 | #define CONFIG_BOOTP_BOOTPATH | |
231 | #define CONFIG_BOOTP_NTPSERVER | |
232 | #define CONFIG_BOOTP_RANDOM_DELAY | |
233 | #define CONFIG_BOOTP_SEND_HOSTNAME | |
234 | ||
235 | /* USB */ | |
fd194f82 AS |
236 | #define CONFIG_SYS_USB_HOST |
237 | #define CONFIG_USB_EHCI | |
238 | #define CONFIG_USB_EHCI_FSL | |
c005b939 | 239 | #define CONFIG_HAS_FSL_DR_USB |
fd194f82 | 240 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
c005b939 AS |
241 | |
242 | /* | |
243 | * Environment | |
244 | */ | |
6d0f6bcf | 245 | #undef CONFIG_SYS_FLASH_PROTECTION |
c005b939 AS |
246 | #define CONFIG_ENV_OVERWRITE |
247 | ||
5a1aceb0 | 248 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 JCPV |
249 | #define CONFIG_ENV_ADDR 0xFF800000 |
250 | #define CONFIG_ENV_SIZE 0x2000 | |
251 | #define CONFIG_ENV_SECT_SIZE 0x2000 | |
252 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) | |
253 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
c005b939 | 254 | |
e093a247 | 255 | #define CONFIG_LOADS_ECHO |
6d0f6bcf | 256 | #define CONFIG_SYS_LOADS_BAUD_CHANGE |
c005b939 AS |
257 | |
258 | /* | |
259 | * Command line configuration. | |
260 | */ | |
261 | #include <config_cmd_default.h> | |
262 | ||
263 | #define CONFIG_CMD_CACHE | |
264 | #define CONFIG_CMD_IRQ | |
265 | #define CONFIG_CMD_NET | |
266 | #define CONFIG_CMD_MII | |
267 | #define CONFIG_CMD_PING | |
268 | #define CONFIG_CMD_DHCP | |
269 | #define CONFIG_CMD_SDRAM | |
270 | #define CONFIG_CMD_PCI | |
271 | #define CONFIG_CMD_I2C | |
272 | #define CONFIG_CMD_FPGA | |
fd194f82 AS |
273 | #define CONFIG_CMD_USB |
274 | #define CONFIG_DOS_PARTITION | |
c005b939 AS |
275 | |
276 | #undef CONFIG_WATCHDOG | |
277 | ||
278 | /* | |
279 | * Miscellaneous configurable options | |
280 | */ | |
6d0f6bcf | 281 | #define CONFIG_SYS_LONGHELP |
c005b939 | 282 | #define CONFIG_CMDLINE_EDITING |
a059e90e | 283 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ |
6d0f6bcf JCPV |
284 | #define CONFIG_SYS_HUSH_PARSER |
285 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
c005b939 AS |
286 | |
287 | /* default load address */ | |
6d0f6bcf | 288 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 |
c005b939 AS |
289 | /* default location for tftp and bootm */ |
290 | #define CONFIG_LOADADDR 0x200000 | |
291 | ||
6d0f6bcf JCPV |
292 | #define CONFIG_SYS_PROMPT "mvBL-M7> " |
293 | #define CONFIG_SYS_CBSIZE 256 | |
c005b939 | 294 | |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) |
296 | #define CONFIG_SYS_MAXARGS 16 | |
297 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
298 | #define CONFIG_SYS_HZ 1000 | |
c005b939 AS |
299 | |
300 | /* | |
301 | * For booting Linux, the board info and command line data | |
302 | * have to be in the first 8 MB of memory, since this is | |
303 | * the maximum mapped by the Linux kernel during initialization. | |
304 | */ | |
6d0f6bcf | 305 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ |
c005b939 | 306 | |
6d0f6bcf JCPV |
307 | #define CONFIG_SYS_HRCW_LOW 0x0 |
308 | #define CONFIG_SYS_HRCW_HIGH 0x0 | |
c005b939 AS |
309 | |
310 | /* | |
311 | * System performance | |
312 | */ | |
6d0f6bcf JCPV |
313 | #define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ |
314 | #define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ | |
315 | #define CONFIG_SYS_SPCR_TSEC1EP 3 /* TSEC1 emergency priority (0-3) */ | |
316 | #define CONFIG_SYS_SPCR_TSEC2EP 3 /* TSEC2 emergency priority (0-3) */ | |
c005b939 AS |
317 | |
318 | /* clocking */ | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_SCCR_ENCCM 0 |
320 | #define CONFIG_SYS_SCCR_USBMPHCM 0 | |
321 | #define CONFIG_SYS_SCCR_USBDRCM 2 | |
322 | #define CONFIG_SYS_SCCR_TSEC1CM 1 | |
323 | #define CONFIG_SYS_SCCR_TSEC2CM 1 | |
c005b939 | 324 | |
6d0f6bcf JCPV |
325 | #define CONFIG_SYS_SICRH 0x1fff8003 |
326 | #define CONFIG_SYS_SICRL (SICRL_LDP_A | SICRL_USB1 | SICRL_USB0) | |
c005b939 | 327 | |
6d0f6bcf | 328 | #define CONFIG_SYS_HID0_INIT 0x000000000 |
1a2e203b KP |
329 | #define CONFIG_SYS_HID0_FINAL (CONFIG_SYS_HID0_INIT | \ |
330 | HID0_ENABLE_INSTRUCTION_CACHE) | |
c005b939 | 331 | |
6d0f6bcf | 332 | #define CONFIG_SYS_HID2 HID2_HBE |
5ed546fd | 333 | #define CONFIG_HIGH_BATS 1 |
c005b939 AS |
334 | |
335 | /* DDR */ | |
6d0f6bcf JCPV |
336 | #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
337 | #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
c005b939 AS |
338 | |
339 | /* PCI */ | |
6d0f6bcf JCPV |
340 | #define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) |
341 | #define CONFIG_SYS_IBAT1U (CONFIG_SYS_PCI1_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) | |
342 | #define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MMIO_BASE | BATL_PP_10 | BATL_CACHEINHIBIT |\ | |
c005b939 | 343 | BATL_GUARDEDSTORAGE) |
6d0f6bcf | 344 | #define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MMIO_BASE | BATU_BL_256M | BATU_VS | BATU_VP) |
c005b939 AS |
345 | |
346 | /* no PCI2 */ | |
6d0f6bcf JCPV |
347 | #define CONFIG_SYS_IBAT3L 0 |
348 | #define CONFIG_SYS_IBAT3U 0 | |
349 | #define CONFIG_SYS_IBAT4L 0 | |
350 | #define CONFIG_SYS_IBAT4U 0 | |
c005b939 AS |
351 | |
352 | /* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 & BCSR @ 0xE2400000 */ | |
6d0f6bcf | 353 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR | BATL_PP_10 | BATL_CACHEINHIBIT | \ |
c005b939 | 354 | BATL_GUARDEDSTORAGE) |
6d0f6bcf | 355 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) |
c005b939 AS |
356 | |
357 | /* stack in DCACHE 0xFDF00000 & FLASH @ 0xFF800000 */ | |
c1230980 SW |
358 | #define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ |
359 | BATL_GUARDEDSTORAGE) | |
6d0f6bcf JCPV |
360 | #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) |
361 | #define CONFIG_SYS_IBAT7L 0 | |
362 | #define CONFIG_SYS_IBAT7U 0 | |
363 | ||
364 | #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L | |
365 | #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U | |
366 | #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L | |
367 | #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U | |
368 | #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L | |
369 | #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U | |
370 | #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L | |
371 | #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U | |
372 | #define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L | |
373 | #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U | |
374 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
375 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
376 | #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L | |
377 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
378 | #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L | |
379 | #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U | |
c005b939 AS |
380 | |
381 | /* | |
382 | * Internal Definitions | |
383 | * | |
384 | * Boot Flags | |
385 | */ | |
386 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
387 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
388 | ||
389 | ||
390 | /* | |
391 | * Environment Configuration | |
392 | */ | |
393 | #define CONFIG_ENV_OVERWRITE | |
394 | ||
395 | #define CONFIG_NETDEV eth0 | |
396 | ||
397 | /* Default path and filenames */ | |
398 | #define CONFIG_BOOTDELAY 5 | |
399 | #define CONFIG_AUTOBOOT_KEYED | |
400 | #define CONFIG_AUTOBOOT_STOP_STR "s" | |
401 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
402 | #define CONFIG_RESET_TO_RETRY 1000 | |
403 | ||
1a9eeb78 AS |
404 | #define MV_CI mvBL-M7 |
405 | #define MV_VCI mvBL-M7 | |
28887d83 AS |
406 | #define MV_FPGA_DATA 0xfff40000 |
407 | #define MV_FPGA_SIZE 0 | |
1a9eeb78 AS |
408 | #define MV_KERNEL_ADDR 0xff810000 |
409 | #define MV_INITRD_ADDR 0xffb00000 | |
3202d331 PT |
410 | #define MV_SCRIPT_ADDR 0xff804000 |
411 | #define MV_SCRIPT_ADDR2 0xff806000 | |
1a9eeb78 AS |
412 | #define MV_DTB_ADDR 0xff808000 |
413 | #define MV_INITRD_LENGTH 0x00400000 | |
c005b939 AS |
414 | |
415 | #define CONFIG_SHOW_BOOT_PROGRESS 1 | |
416 | ||
1a9eeb78 AS |
417 | #define MV_KERNEL_ADDR_RAM 0x00100000 |
418 | #define MV_DTB_ADDR_RAM 0x00600000 | |
419 | #define MV_INITRD_ADDR_RAM 0x01000000 | |
c005b939 | 420 | |
3202d331 PT |
421 | #define CONFIG_BOOTCOMMAND "if imi ${script_addr}; \ |
422 | then source ${script_addr}; \ | |
423 | else source ${script_addr2}; \ | |
c005b939 AS |
424 | fi;" |
425 | #define CONFIG_BOOTARGS "root=/dev/ram ro rootfstype=squashfs" | |
426 | ||
427 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
428 | "console_nr=0\0" \ | |
1a9eeb78 | 429 | "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0" \ |
c005b939 AS |
430 | "stdin=serial\0" \ |
431 | "stdout=serial\0" \ | |
432 | "stderr=serial\0" \ | |
433 | "fpga=0\0" \ | |
1a9eeb78 AS |
434 | "fpgadata=" MK_STR(MV_FPGA_DATA) "\0" \ |
435 | "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0" \ | |
3202d331 PT |
436 | "script_addr=" MK_STR(MV_SCRIPT_ADDR) "\0" \ |
437 | "script_addr2=" MK_STR(MV_SCRIPT_ADDR2) "\0" \ | |
1a9eeb78 AS |
438 | "mv_kernel_addr=" MK_STR(MV_KERNEL_ADDR) "\0" \ |
439 | "mv_kernel_addr_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0" \ | |
440 | "mv_initrd_addr=" MK_STR(MV_INITRD_ADDR) "\0" \ | |
441 | "mv_initrd_addr_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0" \ | |
442 | "mv_initrd_length=" MK_STR(MV_INITRD_LENGTH) "\0" \ | |
443 | "mv_dtb_addr=" MK_STR(MV_DTB_ADDR) "\0" \ | |
444 | "mv_dtb_addr_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0" \ | |
445 | "dtb_name=" MK_STR(MV_DTB_NAME) "\0" \ | |
5ed546fd | 446 | "mv_version=" U_BOOT_VERSION "\0" \ |
1a9eeb78 AS |
447 | "dhcp_client_id=" MK_STR(MV_CI) "\0" \ |
448 | "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0" \ | |
c005b939 AS |
449 | "netretry=no\0" \ |
450 | "use_static_ipaddr=no\0" \ | |
451 | "static_ipaddr=192.168.90.10\0" \ | |
452 | "static_netmask=255.255.255.0\0" \ | |
453 | "static_gateway=0.0.0.0\0" \ | |
28887d83 | 454 | "initrd_name=uInitrd.mvBL-M7-rfs\0" \ |
c005b939 AS |
455 | "zcip=no\0" \ |
456 | "netboot=yes\0" \ | |
457 | "mvtest=Ff\0" \ | |
458 | "tried_bootfromflash=no\0" \ | |
459 | "tried_bootfromnet=no\0" \ | |
460 | "bootfile=mvblm72625.boot\0" \ | |
461 | "use_dhcp=yes\0" \ | |
462 | "gev_start=yes\0" \ | |
463 | "mvbcdma_debug=0\0" \ | |
464 | "mvbcia_debug=0\0" \ | |
465 | "propdev_debug=0\0" \ | |
466 | "gevss_debug=0\0" \ | |
467 | "watchdog=0\0" \ | |
468 | "usb_dr_mode=host\0" \ | |
1a9eeb78 | 469 | "sensor_cnt=2\0" \ |
c005b939 AS |
470 | "" |
471 | ||
472 | #define CONFIG_FPGA_COUNT 1 | |
6d0f6bcf | 473 | #define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2 |
c005b939 AS |
474 | #define CONFIG_FPGA_ALTERA |
475 | #define CONFIG_FPGA_CYCLON2 | |
476 | ||
477 | #endif |