[people/ms/u-boot.git] / include / configs / MVS1.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/*
 * board/config.h - configuration options, board specific
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC823		1	/* This is a MPC823 CPU		*/
#define CONFIG_MVS		1	/* ...on a MVsensor module	*/
#define CONFIG_MVS_16BIT_FLASH		/* ...with 16-bit flash access	*/
#define CONFIG_8xx_GCLK_FREQ	50000000/* ... and a 50 MHz CPU		*/

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#undef	CONFIG_8xx_CONS_SMC1		/* Console is *NOT* on SMC1	*/
#define	CONFIG_8xx_CONS_SMC2	1	/* Console is on SMC2		*/
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		115200	/* console baudrate		*/
#define CONFIG_BOOTDELAY	5	/* autoboot after this many seconds	*/

#define CONFIG_PREBOOT		"echo;" \
				"echo To mount root over NFS use \"run bootnet\";" \
				"echo To mount root from FLASH use  \"run bootflash\";" \
				"echo"
#define	CONFIG_BOOTARGS		"root=/dev/mtdblock2 rw"
#define CONFIG_BOOTCOMMAND							\
	"bootp; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#define	CONFIG_WATCHDOG			/* watchdog disabled/enabled	*/

#undef	CONFIG_STATUS_LED		/* Status LED disabled/enabled	*/

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_VENDOREX

#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


/*
 * Command line configuration.
 */
#define CONFIG_CMD_LOADS
#define CONFIG_CMD_LOADB
#define CONFIG_CMD_IMI
#define CONFIG_CMD_FLASH
#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_NET
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_SAVEENV
#define CONFIG_CMD_BOOTD
#define CONFIG_CMD_RUN


/*
 * Miscellaneous configurable options
 */
#undef	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT		"=> "	/* Monitor Command Prompt	*/

#undef	CONFIG_SYS_HUSH_PARSER			/* Hush parse for U-Boot ?? */

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFFF00000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000

#define	CONFIG_SYS_MONITOR_LEN		(128 << 10)	/* Reserve 192 kB for Monitor	*/

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	71	/* max number of sectors on one chip (for AMD320DB chip)	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1

/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
#define	CONFIG_ENV_OFFSET		0x8000	/* Offset of Environment Sector	(bottom boot sector) */
#define	CONFIG_ENV_SIZE		0x2000	/* Used Size of Environment Sector 8k	*/

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
	     SYPCR_SWE	| SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR   (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR  (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 */
#define CONFIG_SYS_PLPRCR	(PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CONFIG_SYS_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#define	CONFIG_IDE_PCCARD	0	/* **DON'T** Use IDE with PC Card Adapter	*/

#undef	CONFIG_IDE_PCMCIA		/* Direct IDE	 not supported	*/
#undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		0	/* max. no. of IDE buses			*/
#define CONFIG_SYS_IDE_MAXDEVICE	0	/* max. no. of drives per IDE bus	*/


#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000

#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR

/* Offset for data I/O			*/
#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for normal register accesses	*/
#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)

/* Offset for alternate registers	*/
#define CONFIG_SYS_ATA_ALT_OFFSET	0x0100

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#undef FLASH_BASE1_PRELIM

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */


/*
 * FLASH timing:
 */
/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
/*
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
				 OR_SCY_5_CLK | OR_EHTR)
*/

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#ifdef CONFIG_MVS_16BIT_FLASH
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
#else
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
#endif

#undef CONFIG_SYS_OR1_REMAP
#undef CONFIG_SYS_OR1_PRELIM
#undef CONFIG_SYS_BR1_PRELIM
/*
 * BR2/3 and OR2/3 (SDRAM)
 *
 */
#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
#undef SDRAM_BASE3_PRELIM
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	0x00000A00

#define CONFIG_SYS_OR2_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
#define CONFIG_SYS_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )

#undef CONFIG_SYS_OR3_PRELIM
#undef CONFIG_SYS_BR3_PRELIM


/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */
#define CONFIG_SYS_MAMR_PTA		 98

/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit	*/
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A7 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#endif	/* __CONFIG_H */
Commit	Line	Data
c609719b WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
c609719b WD	6	*/
	7
	8	/*
	9	* board/config.h - configuration options, board specific
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*
	16	* High Level Configuration Options
	17	* (easy to change)
	18	*/
	19
	20	#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
	21	#define CONFIG_MVS 1 /* ...on a MVsensor module */
	22	#define CONFIG_MVS_16BIT_FLASH /* ...with 16-bit flash access */
	23	#define CONFIG_8xx_GCLK_FREQ 50000000/* ... and a 50 MHz CPU */
	24
	25	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	26
	27	#undef CONFIG_8xx_CONS_SMC1 /* Console is NOT on SMC1 */
	28	#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
	29	#undef CONFIG_8xx_CONS_NONE
53677ef1	30	#define CONFIG_BAUDRATE 115200 /* console baudrate */
c609719b WD	31	#define CONFIG_BOOTDELAY 5 /* autoboot after this many seconds */
c609719b WD	32
53677ef1 WD	33	#define CONFIG_PREBOOT "echo;" \
	34	"echo To mount root over NFS use \"run bootnet\";" \
	35	"echo To mount root from FLASH use \"run bootflash\";" \
	36	"echo"
c609719b	37	#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rw"
53677ef1 WD	38	#define CONFIG_BOOTCOMMAND \
	39	"bootp; " \
	40	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	41	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
	42	"bootm"
c609719b WD	43
c609719b WD	44	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	45	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
c609719b WD	46
	47	#define CONFIG_WATCHDOG /* watchdog disabled/enabled */
	48
	49	#undef CONFIG_STATUS_LED /* Status LED disabled/enabled */
	50
53677ef1	51	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
c609719b	52
7be044e4 JL	53
	54	/*
	55	* BOOTP options
	56	*/
	57	#define CONFIG_BOOTP_SUBNETMASK
	58	#define CONFIG_BOOTP_GATEWAY
	59	#define CONFIG_BOOTP_HOSTNAME
	60	#define CONFIG_BOOTP_BOOTPATH
	61	#define CONFIG_BOOTP_VENDOREX
c609719b WD	62
	63	#undef CONFIG_MAC_PARTITION
	64	#undef CONFIG_DOS_PARTITION
	65
	66	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	67
8353e139 JL	68
	69	/*
	70	* Command line configuration.
	71	*/
	72	#define CONFIG_CMD_LOADS
	73	#define CONFIG_CMD_LOADB
	74	#define CONFIG_CMD_IMI
	75	#define CONFIG_CMD_FLASH
	76	#define CONFIG_CMD_MEMORY
	77	#define CONFIG_CMD_NET
	78	#define CONFIG_CMD_DHCP
bdab39d3	79	#define CONFIG_CMD_SAVEENV
8353e139 JL	80	#define CONFIG_CMD_BOOTD
	81	#define CONFIG_CMD_RUN
	82
c609719b WD	83
	84	/*
	85	* Miscellaneous configurable options
	86	*/
6d0f6bcf JCPV	87	#undef CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	88	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
c609719b	89
6d0f6bcf	90	#undef CONFIG_SYS_HUSH_PARSER /* Hush parse for U-Boot ?? */
c609719b	91
8353e139	92	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	93	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
c609719b	94	#else
6d0f6bcf	95	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
c609719b	96	#endif
6d0f6bcf JCPV	97	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	98	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	99	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
c609719b	100
6d0f6bcf JCPV	101	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	102	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
c609719b	103
6d0f6bcf	104	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
c609719b	105
6d0f6bcf	106	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
c609719b	107
c609719b WD	108	/*
	109	* Low Level Configuration Settings
	110	* (address mappings, register initial values, etc.)
	111	* You should know what you are doing if you make changes here.
	112	*/
	113	/*-----------------------------------------------------------------------
	114	* Internal Memory Mapped Register
	115	*/
6d0f6bcf	116	#define CONFIG_SYS_IMMR 0xFFF00000
c609719b WD	117
	118	/*-----------------------------------------------------------------------
	119	* Definitions for initial stack pointer and data area (in DPRAM)
	120	*/
6d0f6bcf	121	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	122	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	123	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	124	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
c609719b WD	125
	126	/*-----------------------------------------------------------------------
	127	* Start addresses for the final memory configuration
	128	* (Set up by the startup code)
6d0f6bcf	129	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
c609719b	130	*/
6d0f6bcf JCPV	131	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	132	#define CONFIG_SYS_FLASH_BASE 0x40000000
c609719b	133
6d0f6bcf	134	#define CONFIG_SYS_MONITOR_LEN (128 << 10) /* Reserve 192 kB for Monitor */
c609719b	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
6d0f6bcf JCPV	137	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
c609719b WD	138
	139	/*
	140	* For booting Linux, the board info and command line data
	141	* have to be in the first 8 MB of memory, since this is
	142	* the maximum mapped by the Linux kernel during initialization.
	143	*/
6d0f6bcf	144	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
c609719b WD	145
	146	/*-----------------------------------------------------------------------
	147	* FLASH organization
	148	*/
6d0f6bcf JCPV	149	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
6d0f6bcf JCPV	150	#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip (for AMD320DB chip) */
c609719b	151
6d0f6bcf JCPV	152	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	153	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
c609719b	154
5a1aceb0	155	#define CONFIG_ENV_IS_IN_FLASH 1
c609719b WD	156
c609719b WD	157	/* 4MB flash - use bottom sectors of a bottom boot sector flash (16 bit access) */
0e8d1586 JCPV	158	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector (bottom boot sector) */
0e8d1586 JCPV	159	#define CONFIG_ENV_SIZE 0x2000 /* Used Size of Environment Sector 8k */
c609719b WD	160
	161	/*-----------------------------------------------------------------------
	162	* Cache Configuration
	163	*/
6d0f6bcf	164	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
8353e139	165	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	166	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
c609719b WD	167	#endif
	168
	169	/*-----------------------------------------------------------------------
	170	* SYPCR - System Protection Control 11-9
	171	* SYPCR can only be written once after reset!
	172	*-----------------------------------------------------------------------
	173	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	174	*/
	175	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	176	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
53677ef1	177	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
c609719b	178	#else
6d0f6bcf	179	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
c609719b WD	180	#endif
	181
	182	/*-----------------------------------------------------------------------
	183	* SIUMCR - SIU Module Configuration 11-6
	184	*-----------------------------------------------------------------------
	185	* PCMCIA config., multi-function pin tri-state
	186	*/
6d0f6bcf	187	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
c609719b WD	188
	189	/*-----------------------------------------------------------------------
	190	* TBSCR - Time Base Status and Control 11-26
	191	*-----------------------------------------------------------------------
	192	* Clear Reference Interrupt Status, Timebase freezing enabled
	193	*/
6d0f6bcf	194	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
c609719b WD	195
	196	/*-----------------------------------------------------------------------
	197	* RTCSC - Real-Time Clock Status and Control Register 11-27
	198	*-----------------------------------------------------------------------
	199	*/
6d0f6bcf	200	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
c609719b WD	201
	202	/*-----------------------------------------------------------------------
	203	* PISCR - Periodic Interrupt Status and Control 11-31
	204	*-----------------------------------------------------------------------
	205	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	206	*/
6d0f6bcf	207	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
c609719b WD	208
	209	/*-----------------------------------------------------------------------
	210	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	211	*-----------------------------------------------------------------------
	212	* Reset PLL lock status sticky bit, timer expired status bit and timer
	213	* interrupt status bit
	214	*
	215	*/
6d0f6bcf	216	#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
c609719b WD	217
	218	/*-----------------------------------------------------------------------
	219	* SCCR - System Clock and reset Control Register 15-27
	220	*-----------------------------------------------------------------------
	221	* Set clock output, timebase and RTC source and divider,
	222	* power management and some other internal clocks
	223	*/
	224	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf	225	#define CONFIG_SYS_SCCR (SCCR_TBS \| \
c609719b WD	226	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	227	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	228	SCCR_DFALCD00)
	229
	230	/*-----------------------------------------------------------------------
	231	* PCMCIA stuff
	232	*-----------------------------------------------------------------------
	233	*
	234	*/
6d0f6bcf JCPV	235	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	236	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	237	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	238	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	239	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	240	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	241	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	242	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
c609719b WD	243
	244	/*-----------------------------------------------------------------------
	245	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	246	*-----------------------------------------------------------------------
	247	*/
	248
	249	#define CONFIG_IDE_PCCARD 0 /* DON'T Use IDE with PC Card Adapter */
	250
53677ef1 WD	251	#undef CONFIG_IDE_PCMCIA /* Direct IDE not supported */
53677ef1 WD	252	#undef CONFIG_IDE_LED /* LED for ide not supported */
c609719b WD	253	#undef CONFIG_IDE_RESET /* reset for ide not supported */
c609719b WD	254
6d0f6bcf JCPV	255	#define CONFIG_SYS_IDE_MAXBUS 0 /* max. no. of IDE buses */
6d0f6bcf JCPV	256	#define CONFIG_SYS_IDE_MAXDEVICE 0 /* max. no. of drives per IDE bus */
c609719b WD	257
c609719b WD	258
6d0f6bcf	259	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
c609719b	260
6d0f6bcf	261	#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
c609719b WD	262
c609719b WD	263	/* Offset for data I/O */
6d0f6bcf	264	#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
c609719b WD	265
c609719b WD	266	/* Offset for normal register accesses */
6d0f6bcf	267	#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
c609719b WD	268
c609719b WD	269	/* Offset for alternate registers */
6d0f6bcf	270	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
c609719b WD	271
	272	/*-----------------------------------------------------------------------
	273	*
	274	*-----------------------------------------------------------------------
	275	*
	276	*/
6d0f6bcf JCPV	277	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	278	#define CONFIG_SYS_DER 0
c609719b WD	279
	280	/*
	281	* Init Memory Controller:
	282	*
	283	* BR0/1 and OR0/1 (FLASH)
	284	*/
	285
	286	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	287	#undef FLASH_BASE1_PRELIM
	288
	289	/* used to re-map FLASH both when starting from SRAM or FLASH:
	290	* restrict access enough to keep SRAM working (if any)
	291	* but not too much to meddle with FLASH accesses
	292	*/
6d0f6bcf JCPV	293	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	294	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
c609719b WD	295
	296
	297	/*
	298	* FLASH timing:
	299	*/
	300	/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
6d0f6bcf	301	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
c609719b WD	302	OR_SCY_2_CLK \| OR_EHTR \| OR_BI)
	303	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
	304	/*
6d0f6bcf	305	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_ACS_DIV2 \| OR_BI \| \
c609719b WD	306	OR_SCY_5_CLK \| OR_EHTR)
	307	*/
	308
6d0f6bcf JCPV	309	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	310	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
c609719b	311	#ifdef CONFIG_MVS_16BIT_FLASH
6d0f6bcf	312	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
c609719b	313	#else
6d0f6bcf	314	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_32 \| BR_V )
c609719b WD	315	#endif
c609719b WD	316
6d0f6bcf JCPV	317	#undef CONFIG_SYS_OR1_REMAP
	318	#undef CONFIG_SYS_OR1_PRELIM
	319	#undef CONFIG_SYS_BR1_PRELIM
c609719b WD	320	/*
	321	* BR2/3 and OR2/3 (SDRAM)
	322	*
	323	*/
	324	#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
	325	#undef SDRAM_BASE3_PRELIM
	326	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	327
	328	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	329	#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
c609719b	330
6d0f6bcf JCPV	331	#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_SDRAM )
6d0f6bcf JCPV	332	#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_V )
c609719b	333
6d0f6bcf JCPV	334	#undef CONFIG_SYS_OR3_PRELIM
6d0f6bcf JCPV	335	#undef CONFIG_SYS_BR3_PRELIM
c609719b WD	336
	337
	338	/*
	339	* Memory Periodic Timer Prescaler
	340	*
	341	* The Divider for PTA (refresh timer) configuration is based on an
	342	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	343	* the number of chip selects (NCS) and the actually needed refresh
	344	* rate is done by setting MPTPR.
	345	*
	346	* PTA is calculated from
	347	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	348	*
	349	* gclk CPU clock (not bus clock!)
	350	* Trefresh Refresh cycle * 4 (four word bursts used)
	351	*
	352	* 4096 Rows from SDRAM example configuration
	353	* 1000 factor s -> ms
	354	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	355	* 4 Number of refresh cycles per period
	356	* 64 Refresh cycle in ms per number of rows
	357	* --------------------------------------------
	358	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	359	*
	360	* 50 MHz => 50.000.000 / Divider = 98
	361	* 66 Mhz => 66.000.000 / Divider = 129
	362	* 80 Mhz => 80.000.000 / Divider = 156
	363	*/
6d0f6bcf	364	#define CONFIG_SYS_MAMR_PTA 98
c609719b WD	365
c609719b WD	366	/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
6d0f6bcf JCPV	367	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	368	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
c609719b WD	369
c609719b WD	370	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	371	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	372	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
c609719b WD	373
	374	/*
	375	* MAMR settings for SDRAM
	376	*/
	377
	378	/* 8 column SDRAM */
6d0f6bcf	379	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
c609719b WD	380	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	381	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	382	/* 9 column SDRAM */
6d0f6bcf	383	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
c609719b WD	384	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A7 \| \
	385	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	386
c609719b	387	#endif /* __CONFIG_H */