]> git.ipfire.org Git - people/ms/u-boot.git/blame - include/configs/NETTA2.h
projects / people / ms / u-boot.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Add GPL-2.0+ SPDX-License-Identifier to source files
[people/ms/u-boot.git] / include / configs / NETTA2.h
CommitLineData
79fa88f3
WD		 1/*
2 * (C) Copyright 2000-2004
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
1a459660 5 * SPDX-License-Identifier: GPL-2.0+
79fa88f3
WD		 6 */
7
8/*
9 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
10 * U-Boot port on NetTA4 board
11 */
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16#if !defined(CONFIG_NETTA2_VERSION) || CONFIG_NETTA2_VERSION > 2
17#error Unsupported CONFIG_NETTA2 version
18#endif
19
20/*
21 * High Level Configuration Options
22 * (easy to change)
23 */
24
25#define CONFIG_MPC870 1 /* This is a MPC885 CPU */
26#define CONFIG_NETTA2 1 /* ...on a NetTA2 board */
27
2ae18241
WD		 28#define CONFIG_SYS_TEXT_BASE 0x40000000
29
79fa88f3
WD		 30#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
31#undef CONFIG_8xx_CONS_SMC2
32#undef CONFIG_8xx_CONS_NONE
33
34#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
35
36/* #define CONFIG_XIN 10000000 */
37#define CONFIG_XIN 50000000
38/* #define MPC8XX_HZ 120000000 */
39#define MPC8XX_HZ 66666666
40
41#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
42
43#if 0
44#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
45#else
46#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
47#endif
48
49#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
50
51#define CONFIG_PREBOOT "echo;"
52
53#undef CONFIG_BOOTARGS
54#define CONFIG_BOOTCOMMAND \
53677ef1
WD		 55 "tftpboot; " \
56 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
57 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
79fa88f3
WD		 58 "bootm"
59
74de7aef 60#define CONFIG_SOURCE
79fa88f3 61#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf 62#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
79fa88f3
WD		 63
64#undef CONFIG_WATCHDOG /* watchdog disabled */
65
66#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
67
68#define CONFIG_STATUS_LED 1 /* Status LED enabled */
69#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
70
7be044e4
JL		 71/*
72 * BOOTP options
73 */
74#define CONFIG_BOOTP_SUBNETMASK
75#define CONFIG_BOOTP_GATEWAY
76#define CONFIG_BOOTP_HOSTNAME
77#define CONFIG_BOOTP_BOOTPATH
78#define CONFIG_BOOTP_BOOTFILESIZE
79#define CONFIG_BOOTP_NISDOMAIN
80
79fa88f3
WD		 81
82#undef CONFIG_MAC_PARTITION
83#undef CONFIG_DOS_PARTITION
84
85#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
86
79fa88f3 87#define FEC_ENET 1 /* eth.c needs it that way... */
6d0f6bcf 88#undef CONFIG_SYS_DISCOVER_PHY
79fa88f3 89#define CONFIG_MII 1
0f3ba7e9 90#define CONFIG_MII_INIT 1
79fa88f3
WD		 91#define CONFIG_RMII 1 /* use RMII interface */
92
93#define CONFIG_ETHER_ON_FEC1 1
53677ef1 94#define CONFIG_FEC1_PHY 8 /* phy address of FEC */
79fa88f3
WD		 95#define CONFIG_FEC1_PHY_NORXERR 1
96
97#define CONFIG_ETHER_ON_FEC2 1
98#define CONFIG_FEC2_PHY 4
99#define CONFIG_FEC2_PHY_NORXERR 1
100
101#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
102
e18a1061
JL		 103
104/*
105 * Command line configuration.
106 */
107#include <config_cmd_default.h>
108
e18a1061
JL		 109#define CONFIG_CMD_DHCP
110#define CONFIG_CMD_PING
111#define CONFIG_CMD_MII
112#define CONFIG_CMD_CDP
113
79fa88f3
WD		 114
115#define CONFIG_BOARD_EARLY_INIT_F 1
116#define CONFIG_MISC_INIT_R
117
79fa88f3
WD		 118/*
119 * Miscellaneous configurable options
120 */
6d0f6bcf
JCPV		 121#define CONFIG_SYS_LONGHELP /* undef to save memory */
122#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
79fa88f3 123
6d0f6bcf 124#define CONFIG_SYS_HUSH_PARSER 1
79fa88f3 125
e18a1061 126#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 127#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
79fa88f3 128#else
6d0f6bcf 129#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
79fa88f3 130#endif
6d0f6bcf
JCPV		 131#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
132#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
133#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
79fa88f3 134
6d0f6bcf
JCPV		 135#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
136#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
79fa88f3 137
6d0f6bcf 138#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
79fa88f3 139
6d0f6bcf 140#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
79fa88f3 141
79fa88f3
WD		 142/*
143 * Low Level Configuration Settings
144 * (address mappings, register initial values, etc.)
145 * You should know what you are doing if you make changes here.
146 */
147/*-----------------------------------------------------------------------
148 * Internal Memory Mapped Register
149 */
6d0f6bcf 150#define CONFIG_SYS_IMMR 0xFF000000
79fa88f3
WD		 151
152/*-----------------------------------------------------------------------
153 * Definitions for initial stack pointer and data area (in DPRAM)
154 */
6d0f6bcf 155#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982 156#define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */
25ddd1fb 157#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf 158#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
79fa88f3
WD		 159
160/*-----------------------------------------------------------------------
161 * Start addresses for the final memory configuration
162 * (Set up by the startup code)
6d0f6bcf 163 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
79fa88f3 164 */
6d0f6bcf
JCPV		 165#define CONFIG_SYS_SDRAM_BASE 0x00000000
166#define CONFIG_SYS_FLASH_BASE 0x40000000
79fa88f3 167#if defined(DEBUG)
6d0f6bcf 168#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
79fa88f3 169#else
6d0f6bcf 170#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
79fa88f3 171#endif
6d0f6bcf
JCPV		 172#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
173#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
79fa88f3 174#if CONFIG_NETTA2_VERSION == 2
6d0f6bcf 175#define CONFIG_SYS_FLASH_BASE4 0x40080000
79fa88f3
WD		 176#endif
177
6d0f6bcf 178#define CONFIG_SYS_RESET_ADDRESS 0x80000000
79fa88f3
WD		 179
180/*
181 * For booting Linux, the board info and command line data
182 * have to be in the first 8 MB of memory, since this is
183 * the maximum mapped by the Linux kernel during initialization.
184 */
6d0f6bcf 185#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
79fa88f3
WD		 186
187/*-----------------------------------------------------------------------
188 * FLASH organization
189 */
190#if CONFIG_NETTA2_VERSION == 1
6d0f6bcf 191#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
79fa88f3 192#elif CONFIG_NETTA2_VERSION == 2
6d0f6bcf 193#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
79fa88f3 194#endif
6d0f6bcf 195#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
79fa88f3 196
6d0f6bcf
JCPV		 197#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
198#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
79fa88f3 199
5a1aceb0 200#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586 201#define CONFIG_ENV_SECT_SIZE 0x10000
79fa88f3 202
6d0f6bcf 203#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x60000)
0e8d1586
JCPV		 204#define CONFIG_ENV_OFFSET 0
205#define CONFIG_ENV_SIZE 0x4000
79fa88f3 206
6d0f6bcf 207#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x70000)
0e8d1586
JCPV		 208#define CONFIG_ENV_OFFSET_REDUND 0
209#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
79fa88f3
WD		 210
211/*-----------------------------------------------------------------------
212 * Cache Configuration
213 */
6d0f6bcf 214#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
e18a1061 215#if defined(CONFIG_CMD_KGDB)
6d0f6bcf 216#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
79fa88f3
WD		 217#endif
218
219/*-----------------------------------------------------------------------
220 * SYPCR - System Protection Control 11-9
221 * SYPCR can only be written once after reset!
222 *-----------------------------------------------------------------------
223 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
224 */
225#if defined(CONFIG_WATCHDOG)
6d0f6bcf 226#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
79fa88f3
WD		 227 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
228#else
6d0f6bcf 229#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
79fa88f3
WD		 230#endif
231
232/*-----------------------------------------------------------------------
233 * SIUMCR - SIU Module Configuration 11-6
234 *-----------------------------------------------------------------------
235 * PCMCIA config., multi-function pin tri-state
236 */
237#ifndef CONFIG_CAN_DRIVER
6d0f6bcf 238#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
79fa88f3 239#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf 240#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
79fa88f3
WD		 241#endif /* CONFIG_CAN_DRIVER */
242
243/*-----------------------------------------------------------------------
244 * TBSCR - Time Base Status and Control 11-26
245 *-----------------------------------------------------------------------
246 * Clear Reference Interrupt Status, Timebase freezing enabled
247 */
6d0f6bcf 248#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
79fa88f3
WD		 249
250/*-----------------------------------------------------------------------
251 * RTCSC - Real-Time Clock Status and Control Register 11-27
252 *-----------------------------------------------------------------------
253 */
6d0f6bcf 254#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
79fa88f3
WD		 255
256/*-----------------------------------------------------------------------
257 * PISCR - Periodic Interrupt Status and Control 11-31
258 *-----------------------------------------------------------------------
259 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
260 */
6d0f6bcf 261#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
79fa88f3
WD		 262
263/*-----------------------------------------------------------------------
264 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
265 *-----------------------------------------------------------------------
266 * Reset PLL lock status sticky bit, timer expired status bit and timer
267 * interrupt status bit
268 *
269 */
270
271#if CONFIG_XIN == 10000000
272
273#if MPC8XX_HZ == 120000000
6d0f6bcf 274#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 275 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
53677ef1 276 PLPRCR_TEXPS)
79fa88f3 277#elif MPC8XX_HZ == 100000000
6d0f6bcf 278#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 279 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
53677ef1 280 PLPRCR_TEXPS)
79fa88f3 281#elif MPC8XX_HZ == 50000000
6d0f6bcf 282#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 283 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
53677ef1 284 PLPRCR_TEXPS)
79fa88f3 285#elif MPC8XX_HZ == 25000000
6d0f6bcf 286#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 287 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
53677ef1 288 PLPRCR_TEXPS)
79fa88f3 289#elif MPC8XX_HZ == 40000000
6d0f6bcf 290#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 291 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
53677ef1 292 PLPRCR_TEXPS)
79fa88f3 293#elif MPC8XX_HZ == 75000000
6d0f6bcf 294#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 295 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
53677ef1 296 PLPRCR_TEXPS)
79fa88f3
WD		 297#else
298#error unsupported CPU freq for XIN = 10MHz
299#endif
300
301#elif CONFIG_XIN == 50000000
302
303#if MPC8XX_HZ == 120000000
6d0f6bcf 304#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 305 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
53677ef1 306 PLPRCR_TEXPS)
79fa88f3 307#elif MPC8XX_HZ == 100000000
6d0f6bcf 308#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 309 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
53677ef1 310 PLPRCR_TEXPS)
79fa88f3 311#elif MPC8XX_HZ == 66666666
6d0f6bcf 312#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
79fa88f3 313 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
53677ef1 314 PLPRCR_TEXPS)
79fa88f3
WD		 315#else
316#error unsupported CPU freq for XIN = 50MHz
317#endif
318
319#else
320
321#error unsupported XIN freq
322#endif
323
324
325/*
326 *-----------------------------------------------------------------------
327 * SCCR - System Clock and reset Control Register 15-27
328 *-----------------------------------------------------------------------
329 * Set clock output, timebase and RTC source and divider,
330 * power management and some other internal clocks
331 *
332 * Note: When TBS == 0 the timebase is independent of current cpu clock.
333 */
334
335#define SCCR_MASK SCCR_EBDF11
336#if MPC8XX_HZ > 66666666
6d0f6bcf 337#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
79fa88f3
WD		 338 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
339 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
340 SCCR_DFALCD00 | SCCR_EBDF01)
341#else
6d0f6bcf 342#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
79fa88f3
WD		 343 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
344 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
345 SCCR_DFALCD00)
346#endif
347
348/*-----------------------------------------------------------------------
349 *
350 *-----------------------------------------------------------------------
351 *
352 */
6d0f6bcf
JCPV		 353/*#define CONFIG_SYS_DER 0x2002000F*/
354#define CONFIG_SYS_DER 0
79fa88f3
WD		 355
356/*
357 * Init Memory Controller:
358 *
359 * BR0/1 and OR0/1 (FLASH)
360 */
361
362#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
363
364/* used to re-map FLASH both when starting from SRAM or FLASH:
365 * restrict access enough to keep SRAM working (if any)
366 * but not too much to meddle with FLASH accesses
367 */
6d0f6bcf
JCPV		 368#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
369#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
79fa88f3
WD		 370
371/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf 372#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX)
79fa88f3 373
6d0f6bcf
JCPV		 374#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
375#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
376#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
79fa88f3
WD		 377
378#if CONFIG_NETTA2_VERSION == 2
379
380#define FLASH_BASE4_PRELIM 0x40080000 /* FLASH bank #1 */
381
6d0f6bcf
JCPV		 382#define CONFIG_SYS_OR4_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
383#define CONFIG_SYS_OR4_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
384#define CONFIG_SYS_BR4_PRELIM ((FLASH_BASE4_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )
79fa88f3
WD		 385
386#endif
387
388/*
389 * BR3 and OR3 (SDRAM)
390 *
391 */
392#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
393#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
394
395/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf 396#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS)
79fa88f3 397
6d0f6bcf
JCPV		 398#define CONFIG_SYS_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
399#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_PS_32 | BR_V)
79fa88f3
WD		 400
401/*
402 * Memory Periodic Timer Prescaler
403 */
404
405/*
406 * Memory Periodic Timer Prescaler
407 *
408 * The Divider for PTA (refresh timer) configuration is based on an
409 * example SDRAM configuration (64 MBit, one bank). The adjustment to
410 * the number of chip selects (NCS) and the actually needed refresh
411 * rate is done by setting MPTPR.
412 *
413 * PTA is calculated from
414 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
415 *
416 * gclk CPU clock (not bus clock!)
417 * Trefresh Refresh cycle * 4 (four word bursts used)
418 *
419 * 4096 Rows from SDRAM example configuration
420 * 1000 factor s -> ms
421 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
422 * 4 Number of refresh cycles per period
423 * 64 Refresh cycle in ms per number of rows
424 * --------------------------------------------
425 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
426 *
427 * 50 MHz => 50.000.000 / Divider = 98
428 * 66 Mhz => 66.000.000 / Divider = 129
429 * 80 Mhz => 80.000.000 / Divider = 156
430 */
431
6d0f6bcf 432#define CONFIG_SYS_MAMR_PTA 234
79fa88f3
WD		 433
434/*
435 * For 16 MBit, refresh rates could be 31.3 us
436 * (= 64 ms / 2K = 125 / quad bursts).
437 * For a simpler initialization, 15.6 us is used instead.
438 *
6d0f6bcf
JCPV		 439 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
440 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
79fa88f3 441 */
6d0f6bcf
JCPV		 442#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
443#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
79fa88f3
WD		 444
445/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf
JCPV		 446#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
447#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
79fa88f3
WD		 448
449/*
450 * MAMR settings for SDRAM
451 */
452
453/* 8 column SDRAM */
6d0f6bcf 454#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
79fa88f3
WD		 455 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
456 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
457
458/* 9 column SDRAM */
6d0f6bcf 459#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
79fa88f3
WD		 460 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
461 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
462
79fa88f3
WD		 463#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
464
465/****************************************************************/
466
467#define DSP_SIZE 0x00010000 /* 64K */
468#define NAND_SIZE 0x00010000 /* 64K */
469
470#define DSP_BASE 0xF1000000
471#define NAND_BASE 0xF1010000
472
79fa88f3
WD		 473/*****************************************************************************/
474
6d0f6bcf 475#define CONFIG_SYS_DIRECT_FLASH_TFTP
79fa88f3
WD		 476
477/*****************************************************************************/
478
479#if CONFIG_NETTA2_VERSION == 1
480#define STATUS_LED_BIT 0x00000008 /* bit 28 */
481#elif CONFIG_NETTA2_VERSION == 2
482#define STATUS_LED_BIT 0x00000080 /* bit 24 */
483#endif
484
6d0f6bcf 485#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
79fa88f3
WD		 486#define STATUS_LED_STATE STATUS_LED_BLINKING
487
488#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
489#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
490
491#ifndef __ASSEMBLY__
492
493/* LEDs */
494
495/* led_id_t is unsigned int mask */
496typedef unsigned int led_id_t;
497
498#define __led_toggle(_msk) \
499 do { \
6d0f6bcf 500 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat ^= (_msk); \
79fa88f3
WD		 501 } while(0)
502
503#define __led_set(_msk, _st) \
504 do { \
505 if ((_st)) \
6d0f6bcf 506 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat |= (_msk); \
79fa88f3 507 else \
6d0f6bcf 508 ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat &= ~(_msk); \
79fa88f3
WD		 509 } while(0)
510
511#define __led_init(msk, st) __led_set(msk, st)
512
513#endif
514
515/***********************************************************************************************************
516
517 ----------------------------------------------------------------------------------------------
518
519 (V1) version 1 of the board
520 (V2) version 2 of the board
521
522 ----------------------------------------------------------------------------------------------
523
524 Pin definitions:
525
526 +------+----------------+--------+------------------------------------------------------------
527 | # | Name | Type | Comment
528 +------+----------------+--------+------------------------------------------------------------
529 | PA3 | SPIEN_MAX | Output | MAX serial to uart chip select
530 | PA7 | DSP_INT | Output | DSP interrupt
531 | PA10 | DSP_RESET | Output | DSP reset
532 | PA14 | USBOE | Output | USB (1)
533 | PA15 | USBRXD | Output | USB (1)
534 | PB19 | BT_RTS | Output | Bluetooth (0)
535 | PB23 | BT_CTS | Output | Bluetooth (0)
536 | PB26 | SPIEN_SEP | Output | Serial EEPROM chip select
537 | PB27 | SPICS_DISP | Output | Display chip select
538 | PB28 | SPI_RXD_3V | Input | SPI Data Rx
539 | PB29 | SPI_TXD | Output | SPI Data Tx
540 | PB30 | SPI_CLK | Output | SPI Clock
541 | PC10 | DISPA0 | Output | Display A0
542 | PC11 | BACKLIGHT | Output | Display backlit
543 | PC12 | SPI2RXD | Input | (V1) 2nd SPI RXD
544 | | IO_RESET | Output | (V2) General I/O reset
545 | PC13 | SPI2TXD | Output | (V1) 2nd SPI TXD (V1)
546 | | HOOK | Input | (V2) Hook input interrupt
547 | PC15 | SPI2CLK | Output | (V1) 2nd SPI CLK
548 | | F_RY_BY | Input | (V2) NAND F_RY_BY
549 | PE17 | F_ALE | Output | NAND F_ALE
550 | PE18 | F_CLE | Output | NAND F_CLE
551 | PE20 | F_CE | Output | NAND F_CE
552 | PE24 | SPICS_SCOUT | Output | (V1) Codec chip select
553 | | LED | Output | (V2) LED
554 | PE27 | SPICS_ER | Output | External serial register CS
555 | PE28 | LEDIO1 | Output | (V1) LED
556 | | BKBR1 | Input | (V2) Keyboard input scan
557 | PE29 | LEDIO2 | Output | (V1) LED hook for A (TA2)
558 | | BKBR2 | Input | (V2) Keyboard input scan
559 | PE30 | LEDIO3 | Output | (V1) LED hook for A (TA2)
560 | | BKBR3 | Input | (V2) Keyboard input scan
561 | PE31 | F_RY_BY | Input | (V1) NAND F_RY_BY
562 | | BKBR4 | Input | (V2) Keyboard input scan
563 +------+----------------+--------+---------------------------------------------------
564
565 ----------------------------------------------------------------------------------------------
566
567 Serial register input:
568
569 +------+----------------+------------------------------------------------------------
570 | # | Name | Comment
571 +------+----------------+------------------------------------------------------------
572 | 4 | HOOK | Hook switch
573 | 5 | BT_LINK | Bluetooth link status
574 | 6 | HOST_WAKE | Bluetooth host wake up
575 | 7 | OK_ETH | Cisco inline power OK status
576 +------+----------------+------------------------------------------------------------
577
578 ----------------------------------------------------------------------------------------------
579
580 Chip selects:
581
582 +------+----------------+------------------------------------------------------------
583 | # | Name | Comment
584 +------+----------------+------------------------------------------------------------
585 | CS0 | CS0 | Boot flash
586 | CS1 | CS_FLASH | NAND flash
587 | CS2 | CS_DSP | DSP
588 | CS3 | DCS_DRAM | DRAM
589 | CS4 | CS_FLASH2 | (V2) 2nd flash
590 +------+----------------+------------------------------------------------------------
591
592 ----------------------------------------------------------------------------------------------
593
594 Interrupts:
595
596 +------+----------------+------------------------------------------------------------
597 | # | Name | Comment
598 +------+----------------+------------------------------------------------------------
599 | IRQ1 | IRQ_DSP | DSP interrupt
600 | IRQ3 | S_INTER | DUSLIC ???
601 | IRQ4 | F_RY_BY | NAND
602 | IRQ7 | IRQ_MAX | MAX 3100 interrupt
603 +------+----------------+------------------------------------------------------------
604
605 ----------------------------------------------------------------------------------------------
606
607 Interrupts on PCMCIA pins:
608
609 +------+----------------+------------------------------------------------------------
610 | # | Name | Comment
611 +------+----------------+------------------------------------------------------------
612 | IP_A0| PHY1_LINK | Link status changed for #1 Ethernet interface
613 | IP_A1| PHY2_LINK | Link status changed for #2 Ethernet interface
614 | IP_A2| RMII1_MDINT | PHY interrupt for #1
615 | IP_A3| RMII2_MDINT | PHY interrupt for #2
616 | IP_A5| HOST_WAKE | (V2) Bluetooth host wake
617 | IP_A6| OK_ETH | (V2) Cisco inline power OK
618 +------+----------------+------------------------------------------------------------
619
620**************************************************************************************************/
621
6d0f6bcf
JCPV		 622#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
623#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
624#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
79fa88f3
WD		 625
626/*************************************************************************************************/
627
628/* use board specific hardware */
629#undef CONFIG_WATCHDOG /* watchdog disabled */
630#define CONFIG_HW_WATCHDOG
79fa88f3
WD		 631
632/*************************************************************************************************/
633
634#define CONFIG_CDP_DEVICE_ID 20
635#define CONFIG_CDP_DEVICE_ID_PREFIX "NT" /* netta2 */
636#define CONFIG_CDP_PORT_ID "eth%d"
637#define CONFIG_CDP_CAPABILITIES 0x00000010
561858ee 638#define CONFIG_CDP_VERSION "u-boot" " " U_BOOT_DATE " " U_BOOT_TIME
79fa88f3
WD		 639#define CONFIG_CDP_PLATFORM "Intracom NetTA2"
640#define CONFIG_CDP_TRIGGER 0x20020001
641#define CONFIG_CDP_POWER_CONSUMPTION 4300 /* 90 mA @ 48V */
642#define CONFIG_CDP_APPLIANCE_VLAN_TYPE 0x01 /* ipphone ? */
643
644/*************************************************************************************************/
645
646#define CONFIG_AUTO_COMPLETE 1
647
648/*************************************************************************************************/
649
650#define CONFIG_CRC32_VERIFY 1
651
652/*************************************************************************************************/
653
654#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
655
656/*************************************************************************************************/
657#endif /* __CONFIG_H */
"Das U-Boot" Source Tree