[people/ms/u-boot.git] / include / configs / NETVIA.h

/*
 * (C) Copyright 2000
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Pantelis Antoniou, Intracom S.A., panto@intracom.gr
 * U-Boot port on NetVia board
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC850		1	/* This is a MPC850 CPU		*/
#define CONFIG_NETVIA		1	/* ...on a NetVia board		*/
#undef  CONFIG_NETVIA_PLL_CLOCK		/* PLL or fixed crystal clock	*/

#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1
#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#else
#define CONFIG_8xx_CONS_NONE
#define CONFIG_MAX3100_SERIAL
#endif

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/

#ifdef CONFIG_NETVIA_PLL_CLOCK
/* XXX make sure that you calculate these two correctly */
#define CFG_GCLK_MF		1350
#define CONFIG_8xx_GCLK_FREQ	44236800
#else
#define CFG_GCLK_MF		1
#define CONFIG_8xx_GCLK_FREQ	50000000
#endif

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */

#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"tftpboot; " 								\
	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
	"bootm"

#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */
#endif

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

#define CONFIG_BOOTP_MASK		(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN)

#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

#define CONFIG_COMMANDS_BASE  ( CONFIG_CMD_DFL	| \
				CFG_CMD_DHCP	| \
				CFG_CMD_PING )

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
#define CONFIG_COMMANDS		(CONFIG_COMMANDS_BASE | CFG_CMD_NAND)
#else
#define CONFIG_COMMANDS		CONFIG_COMMANDS_BASE
#endif

#define CONFIG_BOARD_PRE_INIT
#define CONFIG_MISC_INIT_R

/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define	CFG_LONGHELP			/* undef to save memory		*/
#define	CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define	CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/

#define CFG_MEMTEST_START	0x0300000	/* memtest works on	*/
#define CFG_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/

#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/

#define	CFG_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CFG_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CFG_INIT_RAM_ADDR	CFG_IMMR
#define	CFG_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CFG_SDRAM_BASE _must_ start at 0
 */
#define	CFG_SDRAM_BASE		0x00000000
#define CFG_FLASH_BASE		0x40000000
#if defined(DEBUG)
#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif
#define CFG_MONITOR_BASE	CFG_FLASH_BASE
#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks		*/
#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/

#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SECT_SIZE	0x10000

#define	CFG_ENV_ADDR		(CFG_FLASH_BASE + 0x60000)
#define CFG_ENV_OFFSET		0
#define	CFG_ENV_SIZE		0x4000

#define CFG_ENV_ADDR_REDUND	(CFG_FLASH_BASE + 0x70000)
#define CFG_ENV_OFFSET_REDUND	0
#define CFG_ENV_SIZE_REDUND	CFG_ENV_SIZE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CFG_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 */

#define CFG_PLPRCR	( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) | PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#define CFG_SCCR	(SCCR_TBS     | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CFG_DER	0x2002000F*/
#define CFG_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)

#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V )

/*
 * BR3 and OR3 (SDRAM)
 *
 */
#define SDRAM_BASE3_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define	SDRAM_MAX_SIZE		0x04000000	/* max 64 MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CFG_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)

#define CFG_OR3_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM)
#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)

/*
 * Memory Periodic Timer Prescaler
 */

/* periodic timer for refresh */
#define CFG_MAMR_PTA	208

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 9 column SDRAM */
#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

/* Ethernet at SCC2 */
#define CONFIG_SCC2_ENET

#define CONFIG_ARTOS			/* include ARTOS support */

/****************************************************************/

#define DSP_SIZE	0x00010000	/* 64K */
#define FPGA_SIZE	0x00010000	/* 64K */

#define DSP0_BASE	0xF1000000
#define DSP1_BASE	(DSP0_BASE + DSP_SIZE)
#define FPGA_BASE	(DSP1_BASE + DSP_SIZE)

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

#define ER_SIZE		0x00010000	/* 64K */
#define ER_BASE		(FPGA_BASE + FPGA_SIZE)

#define NAND_SIZE	0x00010000	/* 64K */
#define NAND_BASE	(ER_BASE + ER_SIZE)

#endif

/****************************************************************/

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

#define STATUS_LED_BIT		0x00000001		/* bit 31 */
#define STATUS_LED_PERIOD	(CFG_HZ / 2)
#define STATUS_LED_STATE	STATUS_LED_BLINKING

#define STATUS_LED_BIT1		0x00000002		/* bit 30 */
#define STATUS_LED_PERIOD1	(CFG_HZ / 2)
#define STATUS_LED_STATE1	STATUS_LED_OFF

#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */

#endif

/*****************************************************************************/

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

/* NAND */
#define CFG_NAND_BASE			NAND_BASE
#define CONFIG_MTD_NAND_ECC_JFFS2

#define CFG_MAX_NAND_DEVICE		1

#define SECTORSIZE		512
#define ADDR_COLUMN		1
#define ADDR_PAGE		2
#define ADDR_COLUMN_PAGE	3
#define NAND_ChipID_UNKNOWN 	0x00
#define NAND_MAX_FLOORS		1
#define NAND_MAX_CHIPS		1

#define NAND_DISABLE_CE(nand) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0040; \
	} while(0)

#define NAND_ENABLE_CE(nand) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
	} while(0)

#define NAND_CTL_CLRALE(nandptr) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
	} while(0)

#define NAND_CTL_SETALE(nandptr) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0100; \
	} while(0)

#define NAND_CTL_CLRCLE(nandptr) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
	} while(0)

#define NAND_CTL_SETCLE(nandptr) \
	do { \
		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) |=  0x0080; \
	} while(0)

#define NAND_WAIT_READY(nand) \
	do { \
		while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
			; \
	} while (0)

#define WRITE_NAND_COMMAND(d, adr) \
	do { \
		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
	} while(0)

#define WRITE_NAND_ADDRESS(d, adr) \
	do { \
		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
	} while(0)

#define WRITE_NAND(d, adr) \
	do { \
		*(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \
	} while(0)

#define READ_NAND(adr) \
	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))

#endif

/*****************************************************************************/

#ifndef __ASSEMBLY__

#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2

/* LEDs */

/* last value written to the external register; we cannot read back */
extern unsigned int last_er_val;

/* led_id_t is unsigned long mask */
typedef unsigned int led_id_t;

static inline void __led_init(led_id_t mask, int state)
{
	unsigned int new_er_val;

	if (state)
		new_er_val = last_er_val & ~mask;
	else
		new_er_val = last_er_val |  mask;

	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

static inline void __led_toggle(led_id_t mask)
{
	unsigned int new_er_val;

	new_er_val = last_er_val ^ mask;
	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

static inline void __led_set(led_id_t mask, int state)
{
	unsigned int new_er_val;

	if (state)
		new_er_val = last_er_val & ~mask;
	else
		new_er_val = last_er_val |  mask;

	*(volatile unsigned int *)ER_BASE = new_er_val;
	last_er_val = new_er_val;
}

/* MAX3100 console */
#define MAX3100_SPI_RXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_RXD_BIT	0x00000008

#define MAX3100_SPI_TXD_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_TXD_BIT	0x00000004

#define MAX3100_SPI_CLK_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
#define MAX3100_SPI_CLK_BIT	0x00000002

#define MAX3100_CS_PORT		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
#define MAX3100_CS_BIT		0x0010

#endif

#endif

/****************************************************************/

#endif	/* __CONFIG_H */
Commit	Line	Data
5b1d7137 WD	1	/*
	2	* (C) Copyright 2000
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Pantelis Antoniou, Intracom S.A., panto@intracom.gr
	26	* U-Boot port on NetVia board
	27	*/
	28
	29	#ifndef __CONFIG_H
	30	#define __CONFIG_H
	31
	32	/*
	33	* High Level Configuration Options
	34	* (easy to change)
	35	*/
	36
	37	#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
	38	#define CONFIG_NETVIA 1 /* ...on a NetVia board */
	39	#undef CONFIG_NETVIA_PLL_CLOCK /* PLL or fixed crystal clock */
	40
993cad93	41	#if !defined(CONFIG_NETVIA_VERSION) \|\| CONFIG_NETVIA_VERSION == 1
5b1d7137 WD	42	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	43	#undef CONFIG_8xx_CONS_SMC2
	44	#undef CONFIG_8xx_CONS_NONE
993cad93 WD	45	#else
	46	#define CONFIG_8xx_CONS_NONE
	47	#define CONFIG_MAX3100_SERIAL
	48	#endif
	49
5b1d7137 WD	50	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
	51
	52	#ifdef CONFIG_NETVIA_PLL_CLOCK
	53	/* XXX make sure that you calculate these two correctly */
	54	#define CFG_GCLK_MF 1350
	55	#define CONFIG_8xx_GCLK_FREQ 44236800
	56	#else
	57	#define CFG_GCLK_MF 1
	58	#define CONFIG_8xx_GCLK_FREQ 50000000
	59	#endif
	60
	61	#if 0
	62	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	63	#else
	64	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	65	#endif
	66
	67	#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
	68
	69	#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
	70
	71	#undef CONFIG_BOOTARGS
	72	#define CONFIG_BOOTCOMMAND \
	73	"tftpboot; " \
	74	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \
	75	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \
	76	"bootm"
	77
	78	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
	79	#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
	80
	81	#undef CONFIG_WATCHDOG /* watchdog disabled */
	82
	83	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	84
993cad93 WD	85	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	86	#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
	87	#endif
	88
5b1d7137 WD	89	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
5b1d7137 WD	90
993cad93	91	#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT \| CONFIG_BOOTP_BOOTFILESIZE \| CONFIG_BOOTP_NISDOMAIN)
5b1d7137 WD	92
	93	#undef CONFIG_MAC_PARTITION
	94	#undef CONFIG_DOS_PARTITION
	95
	96	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	97
993cad93 WD	98	#define CONFIG_COMMANDS_BASE ( CONFIG_CMD_DFL \| \
	99	CFG_CMD_DHCP \| \
	100	CFG_CMD_PING )
	101
	102	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	103	#define CONFIG_COMMANDS (CONFIG_COMMANDS_BASE \| CFG_CMD_NAND)
	104	#else
	105	#define CONFIG_COMMANDS CONFIG_COMMANDS_BASE
	106	#endif
5b1d7137 WD	107
	108	#define CONFIG_BOARD_PRE_INIT
	109	#define CONFIG_MISC_INIT_R
	110
	111	/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	112	#include <cmd_confdefs.h>
	113
	114	/*
	115	* Miscellaneous configurable options
	116	*/
	117	#define CFG_LONGHELP /* undef to save memory */
	118	#define CFG_PROMPT "=> " /* Monitor Command Prompt */
	119	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	120	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	121	#else
	122	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	123	#endif
	124	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	125	#define CFG_MAXARGS 16 /* max number of command args */
	126	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	127
	128	#define CFG_MEMTEST_START 0x0300000 /* memtest works on */
	129	#define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
	130
	131	#define CFG_LOAD_ADDR 0x100000 /* default load address */
	132
	133	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	134
	135	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	136
	137	/*
	138	* Low Level Configuration Settings
	139	* (address mappings, register initial values, etc.)
	140	* You should know what you are doing if you make changes here.
	141	*/
	142	/*-----------------------------------------------------------------------
	143	* Internal Memory Mapped Register
	144	*/
	145	#define CFG_IMMR 0xFF000000
	146
	147	/*-----------------------------------------------------------------------
	148	* Definitions for initial stack pointer and data area (in DPRAM)
	149	*/
	150	#define CFG_INIT_RAM_ADDR CFG_IMMR
	151	#define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
	152	#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	153	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	154	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	155
	156	/*-----------------------------------------------------------------------
	157	* Start addresses for the final memory configuration
	158	* (Set up by the startup code)
	159	* Please note that CFG_SDRAM_BASE _must_ start at 0
	160	*/
	161	#define CFG_SDRAM_BASE 0x00000000
	162	#define CFG_FLASH_BASE 0x40000000
	163	#if defined(DEBUG)
	164	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
	165	#else
	166	#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	167	#endif
	168	#define CFG_MONITOR_BASE CFG_FLASH_BASE
	169	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
	170
171	/*
172	* For booting Linux, the board info and command line data
173	* have to be in the first 8 MB of memory, since this is
174	* the maximum mapped by the Linux kernel during initialization.
175	*/
176	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
177
178	/*-----------------------------------------------------------------------
179	* FLASH organization
180	*/
181	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
182	#define CFG_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
183
184	#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
185	#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
186
187	#define CFG_ENV_IS_IN_FLASH 1
5b1d7137 WD	188	#define CFG_ENV_SECT_SIZE 0x10000
5b1d7137 WD	189
993cad93 WD	190	#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x60000)
	191	#define CFG_ENV_OFFSET 0
	192	#define CFG_ENV_SIZE 0x4000
	193
	194	#define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x70000)
	195	#define CFG_ENV_OFFSET_REDUND 0
	196	#define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE
	197
5b1d7137 WD	198	/*-----------------------------------------------------------------------
	199	* Cache Configuration
	200	*/
	201	#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
	202	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
	203	#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
	204	#endif
	205
	206	/*-----------------------------------------------------------------------
	207	* SYPCR - System Protection Control 11-9
	208	* SYPCR can only be written once after reset!
	209	*-----------------------------------------------------------------------
	210	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	211	*/
	212	#if defined(CONFIG_WATCHDOG)
	213	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
	214	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
	215	#else
	216	#define CFG_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
	217	#endif
	218
	219	/*-----------------------------------------------------------------------
	220	* SIUMCR - SIU Module Configuration 11-6
	221	*-----------------------------------------------------------------------
	222	* PCMCIA config., multi-function pin tri-state
	223	*/
	224	#ifndef CONFIG_CAN_DRIVER
	225	#define CFG_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01 \| SIUMCR_FRC)
	226	#else /* we must activate GPL5 in the SIUMCR for CAN */
	227	#define CFG_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01 \| SIUMCR_FRC)
	228	#endif /* CONFIG_CAN_DRIVER */
	229
	230	/*-----------------------------------------------------------------------
	231	* TBSCR - Time Base Status and Control 11-26
	232	*-----------------------------------------------------------------------
	233	* Clear Reference Interrupt Status, Timebase freezing enabled
	234	*/
	235	#define CFG_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
	236
	237	/*-----------------------------------------------------------------------
	238	* RTCSC - Real-Time Clock Status and Control Register 11-27
	239	*-----------------------------------------------------------------------
	240	*/
	241	#define CFG_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
	242
	243	/*-----------------------------------------------------------------------
	244	* PISCR - Periodic Interrupt Status and Control 11-31
	245	*-----------------------------------------------------------------------
	246	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	247	*/
	248	#define CFG_PISCR (PISCR_PS \| PISCR_PITF)
	249
	250	/*-----------------------------------------------------------------------
	251	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	252	*-----------------------------------------------------------------------
	253	* Reset PLL lock status sticky bit, timer expired status bit and timer
	254	* interrupt status bit
	255	*
	256	*/
	257
	258	#define CFG_PLPRCR ( ((CFG_GCLK_MF-1) << PLPRCR_MF_SHIFT) \| PLPRCR_SPLSS \| PLPRCR_TEXPS \| PLPRCR_TMIST)
	259
	260	/*-----------------------------------------------------------------------
	261	* SCCR - System Clock and reset Control Register 15-27
262	*-----------------------------------------------------------------------
263	* Set clock output, timebase and RTC source and divider,
264	* power management and some other internal clocks
265	*/
266	#define SCCR_MASK SCCR_EBDF11
267	#define CFG_SCCR (SCCR_TBS \| \
268	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
269	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
270	SCCR_DFALCD00)
271
272	/*-----------------------------------------------------------------------
273	*
274	*-----------------------------------------------------------------------
275	*
276	*/
277	/#define CFG_DER 0x2002000F/
278	#define CFG_DER 0
279
280	/*
281	* Init Memory Controller:
282	*
283	* BR0/1 and OR0/1 (FLASH)
284	*/
285
286	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
287
288	/* used to re-map FLASH both when starting from SRAM or FLASH:
289	* restrict access enough to keep SRAM working (if any)
290	* but not too much to meddle with FLASH accesses
291	*/
292	#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
293	#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
294
295	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
296	#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_BI \| OR_SCY_5_CLK \| OR_TRLX)
297
298	#define CFG_OR0_REMAP (CFG_REMAP_OR_AM \| CFG_OR_TIMING_FLASH)
299	#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM \| CFG_OR_TIMING_FLASH)
300	#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_8 \| BR_V )
301
5b1d7137 WD	302	/*
	303	* BR3 and OR3 (SDRAM)
	304	*
	305	*/
	306	#define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank #0 */
	307	#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
	308
	309	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
	310	#define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM \| OR_G5LS)
	311
	312	#define CFG_OR3_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) \| CFG_OR_TIMING_SDRAM)
	313	#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_PS_32 \| BR_V)
	314
5b1d7137 WD	315	/*
	316	* Memory Periodic Timer Prescaler
	317	*/
	318
	319	/* periodic timer for refresh */
	320	#define CFG_MAMR_PTA 208
	321
	322	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
	323	#define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
	324
	325	/*
	326	* MAMR settings for SDRAM
	327	*/
	328
	329	/* 9 column SDRAM */
	330	#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
	331	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	332	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	333
	334	/*
	335	* Internal Definitions
	336	*
	337	* Boot Flags
	338	*/
	339	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	340	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	341
	342	/* Ethernet at SCC2 */
	343	#define CONFIG_SCC2_ENET
	344
7f70e853 WD	345	#define CONFIG_ARTOS /* include ARTOS support */
7f70e853 WD	346
993cad93 WD	347	/****************************************************************/
	348
	349	#define DSP_SIZE 0x00010000 /* 64K */
	350	#define FPGA_SIZE 0x00010000 /* 64K */
	351
	352	#define DSP0_BASE 0xF1000000
	353	#define DSP1_BASE (DSP0_BASE + DSP_SIZE)
	354	#define FPGA_BASE (DSP1_BASE + DSP_SIZE)
	355
	356	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	357
	358	#define ER_SIZE 0x00010000 /* 64K */
	359	#define ER_BASE (FPGA_BASE + FPGA_SIZE)
	360
	361	#define NAND_SIZE 0x00010000 /* 64K */
	362	#define NAND_BASE (ER_BASE + ER_SIZE)
	363
	364	#endif
	365
	366	/****************************************************************/
	367
	368	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	369
	370	#define STATUS_LED_BIT 0x00000001 /* bit 31 */
	371	#define STATUS_LED_PERIOD (CFG_HZ / 2)
	372	#define STATUS_LED_STATE STATUS_LED_BLINKING
	373
	374	#define STATUS_LED_BIT1 0x00000002 /* bit 30 */
	375	#define STATUS_LED_PERIOD1 (CFG_HZ / 2)
	376	#define STATUS_LED_STATE1 STATUS_LED_OFF
	377
	378	#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
	379	#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
	380
	381	#endif
	382
	383	/*****************************************************************************/
	384
	385	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
	386
	387	/* NAND */
	388	#define CFG_NAND_BASE NAND_BASE
1f4bb37d	389	#define CONFIG_MTD_NAND_ECC_JFFS2
993cad93 WD	390
	391	#define CFG_MAX_NAND_DEVICE 1
	392
	393	#define SECTORSIZE 512
	394	#define ADDR_COLUMN 1
	395	#define ADDR_PAGE 2
	396	#define ADDR_COLUMN_PAGE 3
	397	#define NAND_ChipID_UNKNOWN 0x00
	398	#define NAND_MAX_FLOORS 1
	399	#define NAND_MAX_CHIPS 1
	400
	401	#define NAND_DISABLE_CE(nand) \
	402	do { \
	403	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) \|= 0x0040; \
	404	} while(0)
	405
	406	#define NAND_ENABLE_CE(nand) \
	407	do { \
	408	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0040; \
	409	} while(0)
	410
	411	#define NAND_CTL_CLRALE(nandptr) \
	412	do { \
	413	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0100; \
	414	} while(0)
	415
	416	#define NAND_CTL_SETALE(nandptr) \
	417	do { \
	418	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) \|= 0x0100; \
	419	} while(0)
	420
	421	#define NAND_CTL_CLRCLE(nandptr) \
	422	do { \
	423	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) &= ~0x0080; \
	424	} while(0)
	425
	426	#define NAND_CTL_SETCLE(nandptr) \
	427	do { \
	428	(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat) \|= 0x0080; \
	429	} while(0)
	430
	431	#define NAND_WAIT_READY(nand) \
	432	do { \
	433	while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat & 0x100) == 0) \
	434	; \
	435	} while (0)
	436
	437	#define WRITE_NAND_COMMAND(d, adr) \
	438	do { \
	439	(volatile unsigned char )((unsigned long)(adr)) = (unsigned char)(d); \
	440	} while(0)
	441
	442	#define WRITE_NAND_ADDRESS(d, adr) \
	443	do { \
	444	(volatile unsigned char )((unsigned long)(adr)) = (unsigned char)(d); \
	445	} while(0)
	446
	447	#define WRITE_NAND(d, adr) \
	448	do { \
	449	(volatile unsigned char )((unsigned long)(adr)) = (unsigned char)(d); \
	450	} while(0)
	451
	452	#define READ_NAND(adr) \
	453	((unsigned char)((volatile unsigned char )(unsigned long)(adr)))
454
455	#endif
456
457	/*****************************************************************************/
458
459	#ifndef __ASSEMBLY__
460
461	#if defined(CONFIG_NETVIA_VERSION) && CONFIG_NETVIA_VERSION >= 2
462
463	/* LEDs */
464
465	/* last value written to the external register; we cannot read back */
466	extern unsigned int last_er_val;
467
468	/* led_id_t is unsigned long mask */
469	typedef unsigned int led_id_t;
470
471	static inline void __led_init(led_id_t mask, int state)
472	{
473	unsigned int new_er_val;
474
475	if (state)
476	new_er_val = last_er_val & ~mask;
477	else
478	new_er_val = last_er_val \| mask;
479
480	(volatile unsigned int )ER_BASE = new_er_val;
481	last_er_val = new_er_val;
482	}
483
484	static inline void __led_toggle(led_id_t mask)
485	{
486	unsigned int new_er_val;
487
488	new_er_val = last_er_val ^ mask;
489	(volatile unsigned int )ER_BASE = new_er_val;
490	last_er_val = new_er_val;
491	}
492
493	static inline void __led_set(led_id_t mask, int state)
494	{
495	unsigned int new_er_val;
496
497	if (state)
498	new_er_val = last_er_val & ~mask;
499	else
500	new_er_val = last_er_val \| mask;
501
502	(volatile unsigned int )ER_BASE = new_er_val;
503	last_er_val = new_er_val;
504	}
505
506	/* MAX3100 console */
507	#define MAX3100_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
508	#define MAX3100_SPI_RXD_BIT 0x00000008
509
510	#define MAX3100_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
511	#define MAX3100_SPI_TXD_BIT 0x00000004
512
513	#define MAX3100_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
514	#define MAX3100_SPI_CLK_BIT 0x00000002
515
516	#define MAX3100_CS_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
517	#define MAX3100_CS_BIT 0x0010
518
519	#endif
520
521	#endif
522
523	/****************************************************************/
524
5b1d7137	525	#endif /* __CONFIG_H */