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49249e13 PA |
1 | /* |
2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
49249e13 PA |
5 | */ |
6 | ||
7 | /* | |
8 | * P010 RDB board configuration file | |
9 | */ | |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
14 | #ifdef CONFIG_36BIT | |
15 | #define CONFIG_PHYS_64BIT | |
16 | #endif | |
17 | ||
49249e13 | 18 | #define CONFIG_P1010 |
74fa22ed PK |
19 | #define CONFIG_E500 /* BOOKE e500 family */ |
20 | #include <asm/config_mpc85xx.h> | |
d793e5a8 | 21 | #define CONFIG_NAND_FSL_IFC |
49249e13 PA |
22 | |
23 | #ifdef CONFIG_SDCARD | |
24 | #define CONFIG_RAMBOOT_SDCARD | |
25 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
26 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
27 | #endif | |
28 | ||
29 | #ifdef CONFIG_SPIFLASH | |
30 | #define CONFIG_RAMBOOT_SPIFLASH | |
31 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
32 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
33 | #endif | |
34 | ||
0fa934d2 PK |
35 | #ifdef CONFIG_NAND |
36 | #define CONFIG_SPL | |
37 | #define CONFIG_SPL_INIT_MINIMAL | |
38 | #define CONFIG_SPL_SERIAL_SUPPORT | |
39 | #define CONFIG_SPL_NAND_SUPPORT | |
40 | #define CONFIG_SPL_NAND_MINIMAL | |
41 | #define CONFIG_SPL_FLUSH_IMAGE | |
42 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
43 | ||
44 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
45 | #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 | |
46 | #define CONFIG_SPL_MAX_SIZE 8192 | |
47 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 | |
48 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
49 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((512 << 10) - 0x2000) | |
50 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) | |
51 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
52 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 | |
53 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
d793e5a8 DD |
54 | #endif |
55 | ||
2f439e80 RG |
56 | |
57 | #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ | |
58 | #define CONFIG_RAMBOOT_NAND | |
59 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
60 | #define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc | |
61 | #endif | |
62 | ||
49249e13 PA |
63 | #ifndef CONFIG_SYS_TEXT_BASE |
64 | #define CONFIG_SYS_TEXT_BASE 0xeff80000 | |
65 | #endif | |
66 | ||
67 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
68 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
69 | #endif | |
70 | ||
0fa934d2 PK |
71 | #ifdef CONFIG_SPL_BUILD |
72 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
73 | #else | |
74 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
49249e13 PA |
75 | #endif |
76 | ||
77 | /* High Level Configuration Options */ | |
78 | #define CONFIG_BOOKE /* BOOKE */ | |
79 | #define CONFIG_E500 /* BOOKE e500 family */ | |
80 | #define CONFIG_MPC85xx | |
81 | #define CONFIG_FSL_IFC /* Enable IFC Support */ | |
82 | #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ | |
83 | ||
84 | #define CONFIG_PCI /* Enable PCI/PCIE */ | |
85 | #if defined(CONFIG_PCI) | |
86 | #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ | |
87 | #define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ | |
88 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ | |
842033e6 | 89 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
49249e13 PA |
90 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
91 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
92 | ||
93 | #define CONFIG_CMD_NET | |
94 | #define CONFIG_CMD_PCI | |
95 | ||
96 | #define CONFIG_E1000 /* E1000 pci Ethernet card*/ | |
97 | ||
98 | /* | |
99 | * PCI Windows | |
100 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
101 | */ | |
102 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
103 | #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" | |
104 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
105 | #ifdef CONFIG_PHYS_64BIT | |
106 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
107 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
108 | #else | |
109 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
110 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
111 | #endif | |
112 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
113 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
114 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
115 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
116 | #ifdef CONFIG_PHYS_64BIT | |
117 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
118 | #else | |
119 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
120 | #endif | |
121 | ||
122 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
123 | #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" | |
124 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 | |
125 | #ifdef CONFIG_PHYS_64BIT | |
126 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
127 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
128 | #else | |
129 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
130 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
131 | #endif | |
132 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
133 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
134 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
135 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
136 | #ifdef CONFIG_PHYS_64BIT | |
137 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
138 | #else | |
139 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
140 | #endif | |
141 | ||
142 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ | |
143 | ||
144 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ | |
145 | #define CONFIG_DOS_PARTITION | |
146 | #endif | |
147 | ||
148 | #define CONFIG_FSL_LAW /* Use common FSL init code */ | |
149 | #define CONFIG_TSEC_ENET | |
150 | #define CONFIG_ENV_OVERWRITE | |
151 | ||
152 | #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ | |
153 | #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ | |
154 | ||
155 | #ifndef CONFIG_SDCARD | |
156 | #define CONFIG_MISC_INIT_R | |
157 | #endif | |
158 | ||
159 | #define CONFIG_HWCONFIG | |
160 | /* | |
161 | * These can be toggled for performance analysis, otherwise use default. | |
162 | */ | |
163 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
164 | #define CONFIG_BTB /* toggle branch predition */ | |
165 | ||
166 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
167 | ||
168 | #define CONFIG_ENABLE_36BIT_PHYS | |
169 | ||
170 | #ifdef CONFIG_PHYS_64BIT | |
171 | #define CONFIG_ADDR_MAP 1 | |
172 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
173 | #endif | |
174 | ||
175 | #define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ | |
176 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff | |
177 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
178 | ||
179 | /* DDR Setup */ | |
180 | #define CONFIG_FSL_DDR3 | |
1ba62f10 | 181 | #define CONFIG_SYS_DDR_RAW_TIMING |
49249e13 PA |
182 | #define CONFIG_DDR_SPD |
183 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
184 | #define SPD_EEPROM_ADDRESS 0x52 | |
185 | ||
186 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
187 | ||
188 | #ifndef __ASSEMBLY__ | |
189 | extern unsigned long get_sdram_size(void); | |
190 | #endif | |
191 | #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ | |
192 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
193 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
194 | ||
195 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
196 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
197 | ||
198 | /* DDR3 Controller Settings */ | |
199 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f | |
200 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
201 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
202 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
203 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
204 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
205 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
206 | ||
207 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 | |
208 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
209 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
210 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
211 | #define CONFIG_SYS_DDR_CONTROL 0x470C0000 /* Type = DDR3 */ | |
212 | #define CONFIG_SYS_DDR_CONTROL_2 0x04401010 | |
213 | #define CONFIG_SYS_DDR_TIMING_4 0x00000001 | |
214 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
215 | ||
216 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00020000 | |
217 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00330004 | |
218 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6B4644 | |
219 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF | |
220 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 | |
221 | #define CONFIG_SYS_DDR_MODE_1_800 0x40461520 | |
222 | #define CONFIG_SYS_DDR_MODE_2_800 0x8000c000 | |
223 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 | |
224 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8655A608 | |
225 | ||
226 | /* settings for DDR3 at 667MT/s */ | |
227 | #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 | |
228 | #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 | |
229 | #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 | |
230 | #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD | |
231 | #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 | |
232 | #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 | |
233 | #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 | |
234 | #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 | |
235 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 | |
236 | ||
237 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
238 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
239 | ||
d793e5a8 | 240 | /* Don't relocate CCSRBAR while in NAND_SPL */ |
0fa934d2 | 241 | #ifdef CONFIG_SPL_BUILD |
d793e5a8 DD |
242 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
243 | #endif | |
244 | ||
49249e13 PA |
245 | /* |
246 | * Memory map | |
247 | * | |
248 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheable | |
249 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable | |
250 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
251 | * | |
252 | * Localbus non-cacheable | |
253 | * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable | |
254 | * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable | |
255 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
256 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
257 | */ | |
258 | ||
259 | /* In case of SD card boot, IFC interface is not available because of muxing */ | |
260 | #ifdef CONFIG_SDCARD | |
261 | #define CONFIG_SYS_NO_FLASH | |
262 | #else | |
263 | /* | |
264 | * IFC Definitions | |
265 | */ | |
266 | /* NOR Flash on IFC */ | |
0fa934d2 PK |
267 | #ifdef CONFIG_SPL_BUILD |
268 | #define CONFIG_SYS_NO_FLASH | |
269 | #endif | |
270 | ||
49249e13 PA |
271 | #define CONFIG_SYS_FLASH_BASE 0xee000000 |
272 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ | |
273 | ||
274 | #ifdef CONFIG_PHYS_64BIT | |
275 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
276 | #else | |
277 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
278 | #endif | |
279 | ||
280 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
281 | CSPR_PORT_SIZE_16 | \ | |
282 | CSPR_MSEL_NOR | \ | |
283 | CSPR_V) | |
284 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) | |
285 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) | |
286 | /* NOR Flash Timing Params */ | |
287 | #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ | |
288 | FTIM0_NOR_TEADC(0x5) | \ | |
289 | FTIM0_NOR_TEAHC(0x5) | |
290 | #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ | |
291 | FTIM1_NOR_TRAD_NOR(0x0f) | |
292 | #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ | |
293 | FTIM2_NOR_TCH(0x4) | \ | |
294 | FTIM2_NOR_TWP(0x1c) | |
295 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
296 | ||
297 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
298 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
299 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
300 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
301 | ||
302 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
303 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
304 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
305 | ||
306 | /* CFI for NOR Flash */ | |
307 | #define CONFIG_FLASH_CFI_DRIVER | |
308 | #define CONFIG_SYS_FLASH_CFI | |
309 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
310 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
311 | ||
312 | /* NAND Flash on IFC */ | |
313 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
314 | #ifdef CONFIG_PHYS_64BIT | |
315 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
316 | #else | |
317 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
318 | #endif | |
319 | ||
320 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | |
321 | | CSPR_PORT_SIZE_8 \ | |
322 | | CSPR_MSEL_NAND \ | |
323 | | CSPR_V) | |
324 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
325 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
326 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
327 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
328 | | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ | |
329 | | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ | |
330 | | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ | |
331 | | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ | |
332 | ||
d793e5a8 DD |
333 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
334 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
335 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
336 | #define CONFIG_CMD_NAND | |
337 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) | |
338 | ||
49249e13 PA |
339 | /* NAND Flash Timing Params */ |
340 | #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ | |
341 | FTIM0_NAND_TWP(0x0C) | \ | |
342 | FTIM0_NAND_TWCHT(0x04) | \ | |
343 | FTIM0_NAND_TWH(0x05) | |
344 | #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ | |
345 | FTIM1_NAND_TWBE(0x1d) | \ | |
346 | FTIM1_NAND_TRR(0x07) | \ | |
347 | FTIM1_NAND_TRP(0x0c) | |
348 | #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ | |
349 | FTIM2_NAND_TREH(0x05) | \ | |
350 | FTIM2_NAND_TWHRE(0x0f) | |
351 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) | |
352 | ||
353 | #define CONFIG_SYS_NAND_DDR_LAW 11 | |
354 | ||
355 | /* Set up IFC registers for boot location NOR/NAND */ | |
0fa934d2 | 356 | #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) |
d793e5a8 DD |
357 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
358 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
359 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
360 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
361 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
362 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
363 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
364 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
365 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
366 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
367 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
368 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
369 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
370 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
371 | #else | |
49249e13 PA |
372 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
373 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
374 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
375 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
376 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
377 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
378 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
379 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
380 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
381 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
382 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
383 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
384 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
385 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
d793e5a8 DD |
386 | #endif |
387 | ||
49249e13 PA |
388 | /* CPLD on IFC */ |
389 | #define CONFIG_SYS_CPLD_BASE 0xffb00000 | |
390 | ||
391 | #ifdef CONFIG_PHYS_64BIT | |
392 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull | |
393 | #else | |
394 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
395 | #endif | |
396 | ||
397 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
398 | | CSPR_PORT_SIZE_8 \ | |
399 | | CSPR_MSEL_GPCM \ | |
400 | | CSPR_V) | |
401 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
402 | #define CONFIG_SYS_CSOR3 0x0 | |
403 | /* CPLD Timing parameters for IFC CS3 */ | |
404 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
405 | FTIM0_GPCM_TEADC(0x0e) | \ | |
406 | FTIM0_GPCM_TEAHC(0x0e)) | |
407 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
408 | FTIM1_GPCM_TRAD(0x1f)) | |
409 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
410 | FTIM2_GPCM_TCH(0x0) | \ | |
411 | FTIM2_GPCM_TWP(0x1f)) | |
412 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
413 | #endif /* CONFIG_SDCARD */ | |
414 | ||
0fa934d2 | 415 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) |
49249e13 PA |
416 | #define CONFIG_SYS_RAMBOOT |
417 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
418 | #else | |
419 | #undef CONFIG_SYS_RAMBOOT | |
420 | #endif | |
421 | ||
74fa22ed PK |
422 | #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
423 | #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT)\ | |
424 | && !defined(CONFIG_SECURE_BOOT) | |
425 | #define CONFIG_A003399_NOR_WORKAROUND | |
426 | #endif | |
427 | #endif | |
428 | ||
49249e13 PA |
429 | #define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ |
430 | #define CONFIG_BOARD_EARLY_INIT_R | |
431 | ||
432 | #define CONFIG_SYS_INIT_RAM_LOCK | |
433 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
434 | #define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ | |
435 | ||
436 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ | |
437 | - GENERATED_GBL_DATA_SIZE) | |
438 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
439 | ||
440 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon*/ | |
441 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ | |
442 | ||
443 | /* Serial Port */ | |
444 | #define CONFIG_CONS_INDEX 1 | |
445 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
446 | #define CONFIG_SYS_NS16550 | |
447 | #define CONFIG_SYS_NS16550_SERIAL | |
448 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
449 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
0fa934d2 | 450 | #ifdef CONFIG_SPL_BUILD |
d793e5a8 DD |
451 | #define CONFIG_NS16550_MIN_FUNCTIONS |
452 | #endif | |
49249e13 | 453 | |
49249e13 PA |
454 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ |
455 | ||
456 | #define CONFIG_SYS_BAUDRATE_TABLE \ | |
457 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
458 | ||
459 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
460 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
461 | ||
462 | /* Use the HUSH parser */ | |
463 | #define CONFIG_SYS_HUSH_PARSER | |
49249e13 PA |
464 | |
465 | /* | |
466 | * Pass open firmware flat tree | |
467 | */ | |
468 | #define CONFIG_OF_LIBFDT | |
469 | #define CONFIG_OF_BOARD_SETUP | |
470 | #define CONFIG_OF_STDOUT_VIA_ALIAS | |
471 | ||
472 | /* new uImage format support */ | |
473 | #define CONFIG_FIT | |
474 | #define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ | |
475 | ||
00f792e0 HS |
476 | /* I2C */ |
477 | #define CONFIG_SYS_I2C | |
478 | #define CONFIG_SYS_I2C_FSL | |
479 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
480 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
481 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
482 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
483 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
484 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
49249e13 PA |
485 | |
486 | /* I2C EEPROM */ | |
487 | #undef CONFIG_ID_EEPROM | |
488 | /* enable read and write access to EEPROM */ | |
489 | #define CONFIG_CMD_EEPROM | |
490 | #define CONFIG_SYS_I2C_MULTI_EEPROMS | |
491 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
492 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
493 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
494 | ||
495 | /* RTC */ | |
496 | #define CONFIG_RTC_PT7C4338 | |
497 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
498 | ||
499 | #define CONFIG_CMD_I2C | |
500 | ||
501 | /* | |
502 | * SPI interface will not be available in case of NAND boot SPI CS0 will be | |
503 | * used for SLIC | |
504 | */ | |
0fa934d2 | 505 | #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) |
49249e13 PA |
506 | /* eSPI - Enhanced SPI */ |
507 | #define CONFIG_FSL_ESPI | |
508 | #define CONFIG_SPI_FLASH | |
509 | #define CONFIG_SPI_FLASH_SPANSION | |
510 | #define CONFIG_CMD_SF | |
511 | #define CONFIG_SF_DEFAULT_SPEED 10000000 | |
512 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
d793e5a8 | 513 | #endif |
49249e13 PA |
514 | |
515 | #if defined(CONFIG_TSEC_ENET) | |
49249e13 PA |
516 | #define CONFIG_MII /* MII PHY management */ |
517 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
518 | #define CONFIG_TSEC1 1 | |
519 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
520 | #define CONFIG_TSEC2 1 | |
521 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
522 | #define CONFIG_TSEC3 1 | |
523 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
524 | ||
525 | #define TSEC1_PHY_ADDR 1 | |
526 | #define TSEC2_PHY_ADDR 0 | |
527 | #define TSEC3_PHY_ADDR 2 | |
528 | ||
529 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
530 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
531 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
532 | ||
533 | #define TSEC1_PHYIDX 0 | |
534 | #define TSEC2_PHYIDX 0 | |
535 | #define TSEC3_PHYIDX 0 | |
536 | ||
537 | #define CONFIG_ETHPRIME "eTSEC1" | |
538 | ||
539 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
540 | ||
541 | /* TBI PHY configuration for SGMII mode */ | |
542 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
543 | TBICR_PHY_RESET \ | |
544 | | TBICR_ANEG_ENABLE \ | |
545 | | TBICR_FULL_DUPLEX \ | |
546 | | TBICR_SPEED1_SET \ | |
547 | ) | |
548 | ||
549 | #endif /* CONFIG_TSEC_ENET */ | |
550 | ||
551 | ||
552 | /* SATA */ | |
553 | #define CONFIG_FSL_SATA | |
9760b274 | 554 | #define CONFIG_FSL_SATA_V2 |
49249e13 PA |
555 | #define CONFIG_LIBATA |
556 | ||
557 | #ifdef CONFIG_FSL_SATA | |
558 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
559 | #define CONFIG_SATA1 | |
560 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
561 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
562 | #define CONFIG_SATA2 | |
563 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
564 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
565 | ||
566 | #define CONFIG_CMD_SATA | |
567 | #define CONFIG_LBA48 | |
568 | #endif /* #ifdef CONFIG_FSL_SATA */ | |
569 | ||
570 | /* SD interface will only be available in case of SD boot */ | |
571 | #ifdef CONFIG_SDCARD | |
572 | #define CONFIG_MMC | |
573 | #define CONFIG_DEF_HWCONFIG esdhc | |
574 | #endif | |
575 | ||
576 | #ifdef CONFIG_MMC | |
577 | #define CONFIG_CMD_MMC | |
578 | #define CONFIG_DOS_PARTITION | |
579 | #define CONFIG_FSL_ESDHC | |
580 | #define CONFIG_GENERIC_MMC | |
581 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR | |
582 | #endif | |
583 | ||
584 | #define CONFIG_HAS_FSL_DR_USB | |
585 | ||
586 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
587 | #define CONFIG_USB_EHCI | |
588 | ||
589 | #ifdef CONFIG_USB_EHCI | |
590 | #define CONFIG_CMD_USB | |
591 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET | |
592 | #define CONFIG_USB_EHCI_FSL | |
593 | #define CONFIG_USB_STORAGE | |
594 | #endif | |
595 | #endif | |
596 | ||
597 | /* | |
598 | * Environment | |
599 | */ | |
49249e13 PA |
600 | #if defined(CONFIG_RAMBOOT_SDCARD) |
601 | #define CONFIG_ENV_IS_IN_MMC | |
4394d0c2 | 602 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
49249e13 PA |
603 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
604 | #define CONFIG_ENV_SIZE 0x2000 | |
605 | #elif defined(CONFIG_RAMBOOT_SPIFLASH) | |
606 | #define CONFIG_ENV_IS_IN_SPI_FLASH | |
607 | #define CONFIG_ENV_SPI_BUS 0 | |
608 | #define CONFIG_ENV_SPI_CS 0 | |
609 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
610 | #define CONFIG_ENV_SPI_MODE 0 | |
611 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
612 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
613 | #define CONFIG_ENV_SIZE 0x2000 | |
0fa934d2 | 614 | #elif defined(CONFIG_NAND) |
d793e5a8 DD |
615 | #define CONFIG_ENV_IS_IN_NAND |
616 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE | |
0fa934d2 | 617 | #define CONFIG_ENV_OFFSET ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE) |
d793e5a8 | 618 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) |
0fa934d2 | 619 | #elif defined(CONFIG_SYS_RAMBOOT) |
49249e13 PA |
620 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
621 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
622 | #define CONFIG_ENV_SIZE 0x2000 | |
49249e13 PA |
623 | #else |
624 | #define CONFIG_ENV_IS_IN_FLASH | |
625 | #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 | |
626 | #define CONFIG_ENV_ADDR 0xfff80000 | |
627 | #else | |
628 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) | |
629 | #endif | |
630 | #define CONFIG_ENV_SIZE 0x2000 | |
631 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
632 | #endif | |
633 | ||
634 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
635 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
636 | ||
637 | /* | |
638 | * Command line configuration. | |
639 | */ | |
640 | #include <config_cmd_default.h> | |
641 | ||
642 | #define CONFIG_CMD_DATE | |
643 | #define CONFIG_CMD_ERRATA | |
644 | #define CONFIG_CMD_ELF | |
645 | #define CONFIG_CMD_IRQ | |
646 | #define CONFIG_CMD_MII | |
647 | #define CONFIG_CMD_PING | |
648 | #define CONFIG_CMD_SETEXPR | |
649 | #define CONFIG_CMD_REGINFO | |
650 | ||
651 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
652 | ||
653 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ | |
654 | || defined(CONFIG_FSL_SATA) | |
655 | #define CONFIG_CMD_EXT2 | |
656 | #define CONFIG_CMD_FAT | |
657 | #define CONFIG_DOS_PARTITION | |
658 | #endif | |
659 | ||
660 | /* | |
661 | * Miscellaneous configurable options | |
662 | */ | |
663 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
664 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
665 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
666 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
667 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
668 | ||
669 | #if defined(CONFIG_CMD_KGDB) | |
670 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
671 | #else | |
672 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
673 | #endif | |
674 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
675 | /* Print Buffer Size */ | |
676 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
677 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
678 | #define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ | |
679 | ||
680 | /* | |
681 | * Internal Definitions | |
682 | * | |
683 | * Boot Flags | |
684 | */ | |
685 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
686 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
687 | ||
688 | /* | |
689 | * For booting Linux, the board info and command line data | |
690 | * have to be in the first 64 MB of memory, since this is | |
691 | * the maximum mapped by the Linux kernel during initialization. | |
692 | */ | |
693 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
694 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
695 | ||
696 | #if defined(CONFIG_CMD_KGDB) | |
697 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
698 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
699 | #endif | |
700 | ||
701 | /* | |
702 | * Environment Configuration | |
703 | */ | |
704 | ||
705 | #if defined(CONFIG_TSEC_ENET) | |
706 | #define CONFIG_HAS_ETH0 | |
707 | #define CONFIG_HAS_ETH1 | |
708 | #define CONFIG_HAS_ETH2 | |
709 | #endif | |
710 | ||
711 | #define CONFIG_HOSTNAME P1010RDB | |
8b3637c6 | 712 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 713 | #define CONFIG_BOOTFILE "uImage" |
49249e13 PA |
714 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
715 | ||
716 | /* default location for tftp and bootm */ | |
717 | #define CONFIG_LOADADDR 1000000 | |
718 | ||
719 | #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ | |
720 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
721 | ||
722 | #define CONFIG_BAUDRATE 115200 | |
723 | ||
724 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d | 725 | "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ |
49249e13 | 726 | "netdev=eth0\0" \ |
5368c55d | 727 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
49249e13 PA |
728 | "loadaddr=1000000\0" \ |
729 | "consoledev=ttyS0\0" \ | |
730 | "ramdiskaddr=2000000\0" \ | |
731 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
732 | "fdtaddr=c00000\0" \ | |
733 | "fdtfile=p1010rdb.dtb\0" \ | |
734 | "bdev=sda1\0" \ | |
735 | "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ | |
736 | "othbootargs=ramdisk_size=600000\0" \ | |
737 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
738 | "console=$consoledev,$baudrate $othbootargs; " \ | |
739 | "usb start;" \ | |
740 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
741 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
742 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
743 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
744 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
745 | "console=$consoledev,$baudrate $othbootargs; " \ | |
746 | "usb start;" \ | |
747 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
748 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
749 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
750 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
751 | ||
752 | #define CONFIG_RAMBOOTCOMMAND \ | |
753 | "setenv bootargs root=/dev/ram rw " \ | |
754 | "console=$consoledev,$baudrate $othbootargs; " \ | |
755 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
756 | "tftp $loadaddr $bootfile;" \ | |
757 | "tftp $fdtaddr $fdtfile;" \ | |
758 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
759 | ||
760 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
761 | ||
2f439e80 | 762 | #include <asm/fsl_secure_boot.h> |
2f439e80 | 763 | |
49249e13 | 764 | #endif /* __CONFIG_H */ |