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49249e13 PA |
1 | /* |
2 | * Copyright 2010-2011 Freescale Semiconductor, Inc. | |
3 | * | |
1a459660 | 4 | * SPDX-License-Identifier: GPL-2.0+ |
49249e13 PA |
5 | */ |
6 | ||
7 | /* | |
8 | * P010 RDB board configuration file | |
9 | */ | |
10 | ||
11 | #ifndef __CONFIG_H | |
12 | #define __CONFIG_H | |
13 | ||
74fa22ed | 14 | #include <asm/config_mpc85xx.h> |
d793e5a8 | 15 | #define CONFIG_NAND_FSL_IFC |
49249e13 PA |
16 | |
17 | #ifdef CONFIG_SDCARD | |
c9e1f588 YZ |
18 | #define CONFIG_SPL_MMC_MINIMAL |
19 | #define CONFIG_SPL_FLUSH_IMAGE | |
20 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
c9e1f588 YZ |
21 | #define CONFIG_SYS_TEXT_BASE 0x11001000 |
22 | #define CONFIG_SPL_TEXT_BASE 0xD0001000 | |
23 | #define CONFIG_SPL_PAD_TO 0x18000 | |
24 | #define CONFIG_SPL_MAX_SIZE (96 * 1024) | |
25 | #define CONFIG_SYS_MMC_U_BOOT_SIZE (512 << 10) | |
26 | #define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000) | |
27 | #define CONFIG_SYS_MMC_U_BOOT_START (0x11000000) | |
28 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (96 << 10) | |
29 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
30 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
31 | #define CONFIG_SPL_MMC_BOOT | |
32 | #ifdef CONFIG_SPL_BUILD | |
33 | #define CONFIG_SPL_COMMON_INIT_DDR | |
34 | #endif | |
49249e13 PA |
35 | #endif |
36 | ||
37 | #ifdef CONFIG_SPIFLASH | |
c9e1f588 | 38 | #ifdef CONFIG_SECURE_BOOT |
49249e13 PA |
39 | #define CONFIG_RAMBOOT_SPIFLASH |
40 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
84e0fb40 | 41 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
c9e1f588 | 42 | #else |
c9e1f588 YZ |
43 | #define CONFIG_SPL_SPI_FLASH_MINIMAL |
44 | #define CONFIG_SPL_FLUSH_IMAGE | |
45 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
c9e1f588 YZ |
46 | #define CONFIG_SYS_TEXT_BASE 0x11001000 |
47 | #define CONFIG_SPL_TEXT_BASE 0xD0001000 | |
48 | #define CONFIG_SPL_PAD_TO 0x18000 | |
49 | #define CONFIG_SPL_MAX_SIZE (96 * 1024) | |
50 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (512 << 10) | |
51 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000) | |
52 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000) | |
53 | #define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (96 << 10) | |
54 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
55 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds" | |
56 | #define CONFIG_SPL_SPI_BOOT | |
57 | #ifdef CONFIG_SPL_BUILD | |
58 | #define CONFIG_SPL_COMMON_INIT_DDR | |
59 | #endif | |
60 | #endif | |
49249e13 PA |
61 | #endif |
62 | ||
0fa934d2 | 63 | #ifdef CONFIG_NAND |
c9e1f588 | 64 | #ifdef CONFIG_SECURE_BOOT |
0fa934d2 | 65 | #define CONFIG_SPL_INIT_MINIMAL |
fbe76ae4 | 66 | #define CONFIG_SPL_NAND_BOOT |
0fa934d2 PK |
67 | #define CONFIG_SPL_FLUSH_IMAGE |
68 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
69 | ||
70 | #define CONFIG_SYS_TEXT_BASE 0x00201000 | |
71 | #define CONFIG_SPL_TEXT_BASE 0xFFFFE000 | |
72 | #define CONFIG_SPL_MAX_SIZE 8192 | |
73 | #define CONFIG_SPL_RELOC_TEXT_BASE 0x00100000 | |
74 | #define CONFIG_SPL_RELOC_STACK 0x00100000 | |
e222b1f3 | 75 | #define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000) |
0fa934d2 PK |
76 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x00200000 - CONFIG_SPL_MAX_SIZE) |
77 | #define CONFIG_SYS_NAND_U_BOOT_START 0x00200000 | |
78 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0 | |
79 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
c9e1f588 | 80 | #else |
c9e1f588 YZ |
81 | #ifdef CONFIG_TPL_BUILD |
82 | #define CONFIG_SPL_NAND_BOOT | |
83 | #define CONFIG_SPL_FLUSH_IMAGE | |
c9e1f588 | 84 | #define CONFIG_SPL_NAND_INIT |
c9e1f588 YZ |
85 | #define CONFIG_SPL_COMMON_INIT_DDR |
86 | #define CONFIG_SPL_MAX_SIZE (128 << 10) | |
87 | #define CONFIG_SPL_TEXT_BASE 0xD0001000 | |
88 | #define CONFIG_SYS_MPC85XX_NO_RESETVEC | |
89 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (576 << 10) | |
90 | #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) | |
91 | #define CONFIG_SYS_NAND_U_BOOT_START (0x11000000) | |
92 | #define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10) | |
93 | #elif defined(CONFIG_SPL_BUILD) | |
94 | #define CONFIG_SPL_INIT_MINIMAL | |
c9e1f588 YZ |
95 | #define CONFIG_SPL_NAND_MINIMAL |
96 | #define CONFIG_SPL_FLUSH_IMAGE | |
97 | #define CONFIG_SPL_TEXT_BASE 0xff800000 | |
98 | #define CONFIG_SPL_MAX_SIZE 8192 | |
99 | #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) | |
100 | #define CONFIG_SYS_NAND_U_BOOT_DST 0xD0000000 | |
101 | #define CONFIG_SYS_NAND_U_BOOT_START 0xD0000000 | |
102 | #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) | |
103 | #endif | |
104 | #define CONFIG_SPL_PAD_TO 0x20000 | |
105 | #define CONFIG_TPL_PAD_TO 0x20000 | |
106 | #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" | |
107 | #define CONFIG_SYS_TEXT_BASE 0x11001000 | |
108 | #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" | |
109 | #endif | |
d793e5a8 | 110 | #endif |
2f439e80 RG |
111 | |
112 | #ifdef CONFIG_NAND_SECBOOT /* NAND Boot */ | |
113 | #define CONFIG_RAMBOOT_NAND | |
114 | #define CONFIG_SYS_TEXT_BASE 0x11000000 | |
e222b1f3 | 115 | #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc |
2f439e80 RG |
116 | #endif |
117 | ||
49249e13 | 118 | #ifndef CONFIG_SYS_TEXT_BASE |
e222b1f3 | 119 | #define CONFIG_SYS_TEXT_BASE 0xeff40000 |
49249e13 PA |
120 | #endif |
121 | ||
122 | #ifndef CONFIG_RESET_VECTOR_ADDRESS | |
123 | #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc | |
124 | #endif | |
125 | ||
0fa934d2 PK |
126 | #ifdef CONFIG_SPL_BUILD |
127 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE | |
128 | #else | |
129 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ | |
49249e13 PA |
130 | #endif |
131 | ||
132 | /* High Level Configuration Options */ | |
737537ef | 133 | #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ |
49249e13 PA |
134 | #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ |
135 | ||
49249e13 | 136 | #if defined(CONFIG_PCI) |
b38eaec5 RD |
137 | #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ |
138 | #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ | |
49249e13 | 139 | #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ |
842033e6 | 140 | #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ |
49249e13 PA |
141 | #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ |
142 | #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ | |
143 | ||
49249e13 PA |
144 | #define CONFIG_CMD_PCI |
145 | ||
49249e13 PA |
146 | /* |
147 | * PCI Windows | |
148 | * Memory space is mapped 1-1, but I/O space must start from 0. | |
149 | */ | |
150 | /* controller 1, Slot 1, tgtid 1, Base address a000 */ | |
151 | #define CONFIG_SYS_PCIE1_NAME "mini PCIe Slot" | |
152 | #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 | |
153 | #ifdef CONFIG_PHYS_64BIT | |
154 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
155 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull | |
156 | #else | |
157 | #define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 | |
158 | #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 | |
159 | #endif | |
160 | #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ | |
161 | #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 | |
162 | #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 | |
163 | #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ | |
164 | #ifdef CONFIG_PHYS_64BIT | |
165 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull | |
166 | #else | |
167 | #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 | |
168 | #endif | |
169 | ||
170 | /* controller 2, Slot 2, tgtid 2, Base address 9000 */ | |
7601686c | 171 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
49249e13 | 172 | #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" |
7601686c | 173 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
174 | #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" |
175 | #endif | |
49249e13 PA |
176 | #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 |
177 | #ifdef CONFIG_PHYS_64BIT | |
178 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 | |
179 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull | |
180 | #else | |
181 | #define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 | |
182 | #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 | |
183 | #endif | |
184 | #define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ | |
185 | #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 | |
186 | #define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 | |
187 | #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ | |
188 | #ifdef CONFIG_PHYS_64BIT | |
189 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull | |
190 | #else | |
191 | #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 | |
192 | #endif | |
193 | ||
49249e13 | 194 | #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
49249e13 PA |
195 | #endif |
196 | ||
49249e13 PA |
197 | #define CONFIG_TSEC_ENET |
198 | #define CONFIG_ENV_OVERWRITE | |
199 | ||
200 | #define CONFIG_DDR_CLK_FREQ 66666666 /* DDRCLK on P1010 RDB */ | |
201 | #define CONFIG_SYS_CLK_FREQ 66666666 /* SYSCLK for P1010 RDB */ | |
202 | ||
49249e13 | 203 | #define CONFIG_MISC_INIT_R |
49249e13 PA |
204 | #define CONFIG_HWCONFIG |
205 | /* | |
206 | * These can be toggled for performance analysis, otherwise use default. | |
207 | */ | |
208 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
209 | #define CONFIG_BTB /* toggle branch predition */ | |
210 | ||
211 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
212 | ||
213 | #define CONFIG_ENABLE_36BIT_PHYS | |
214 | ||
215 | #ifdef CONFIG_PHYS_64BIT | |
216 | #define CONFIG_ADDR_MAP 1 | |
217 | #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ | |
218 | #endif | |
219 | ||
c3cc02af | 220 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ |
49249e13 PA |
221 | #define CONFIG_SYS_MEMTEST_END 0x1fffffff |
222 | #define CONFIG_PANIC_HANG /* do not reset board on panic */ | |
223 | ||
224 | /* DDR Setup */ | |
1ba62f10 | 225 | #define CONFIG_SYS_DDR_RAW_TIMING |
49249e13 PA |
226 | #define CONFIG_DDR_SPD |
227 | #define CONFIG_SYS_SPD_BUS_NUM 1 | |
228 | #define SPD_EEPROM_ADDRESS 0x52 | |
229 | ||
230 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef | |
231 | ||
232 | #ifndef __ASSEMBLY__ | |
233 | extern unsigned long get_sdram_size(void); | |
234 | #endif | |
235 | #define CONFIG_SYS_SDRAM_SIZE get_sdram_size() /* DDR size */ | |
236 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 | |
237 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
238 | ||
239 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
240 | #define CONFIG_CHIP_SELECTS_PER_CTRL 1 | |
241 | ||
242 | /* DDR3 Controller Settings */ | |
243 | #define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f | |
244 | #define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 | |
245 | #define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 | |
246 | #define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef | |
247 | #define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 | |
248 | #define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 | |
249 | #define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 | |
49249e13 PA |
250 | #define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 |
251 | #define CONFIG_SYS_DDR_SR_CNTR 0x00000000 | |
252 | #define CONFIG_SYS_DDR_RCW_1 0x00000000 | |
253 | #define CONFIG_SYS_DDR_RCW_2 0x00000000 | |
e512c50b SL |
254 | #define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ |
255 | #define CONFIG_SYS_DDR_CONTROL_2 0x24401000 | |
49249e13 PA |
256 | #define CONFIG_SYS_DDR_TIMING_4 0x00000001 |
257 | #define CONFIG_SYS_DDR_TIMING_5 0x03402400 | |
258 | ||
e512c50b SL |
259 | #define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 |
260 | #define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 | |
261 | #define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 | |
49249e13 PA |
262 | #define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF |
263 | #define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 | |
e512c50b SL |
264 | #define CONFIG_SYS_DDR_MODE_1_800 0x00441420 |
265 | #define CONFIG_SYS_DDR_MODE_2_800 0x00000000 | |
49249e13 | 266 | #define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 |
e512c50b | 267 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 |
49249e13 PA |
268 | |
269 | /* settings for DDR3 at 667MT/s */ | |
270 | #define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 | |
271 | #define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 | |
272 | #define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 | |
273 | #define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD | |
274 | #define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 | |
275 | #define CONFIG_SYS_DDR_MODE_1_667 0x00441210 | |
276 | #define CONFIG_SYS_DDR_MODE_2_667 0x00000000 | |
277 | #define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 | |
278 | #define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 | |
279 | ||
280 | #define CONFIG_SYS_CCSRBAR 0xffe00000 | |
281 | #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR | |
282 | ||
d793e5a8 | 283 | /* Don't relocate CCSRBAR while in NAND_SPL */ |
0fa934d2 | 284 | #ifdef CONFIG_SPL_BUILD |
d793e5a8 DD |
285 | #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE |
286 | #endif | |
287 | ||
49249e13 PA |
288 | /* |
289 | * Memory map | |
290 | * | |
291 | * 0x0000_0000 0x3fff_ffff DDR 1G cacheable | |
292 | * 0x8000_0000 0xbfff_ffff PCI Express Mem 1.5G non-cacheable | |
293 | * 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable | |
294 | * | |
295 | * Localbus non-cacheable | |
296 | * 0xff80_0000 0xff8f_ffff NAND Flash 1M non-cacheable | |
297 | * 0xffb0_0000 0xffbf_ffff Board CPLD 1M non-cacheable | |
298 | * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0 | |
299 | * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable | |
300 | */ | |
301 | ||
49249e13 PA |
302 | /* |
303 | * IFC Definitions | |
304 | */ | |
305 | /* NOR Flash on IFC */ | |
0fa934d2 | 306 | |
49249e13 PA |
307 | #define CONFIG_SYS_FLASH_BASE 0xee000000 |
308 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ | |
309 | ||
310 | #ifdef CONFIG_PHYS_64BIT | |
311 | #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) | |
312 | #else | |
313 | #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE | |
314 | #endif | |
315 | ||
316 | #define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ | |
317 | CSPR_PORT_SIZE_16 | \ | |
318 | CSPR_MSEL_NOR | \ | |
319 | CSPR_V) | |
320 | #define CONFIG_SYS_NOR_AMASK IFC_AMASK(32*1024*1024) | |
321 | #define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(7) | |
322 | /* NOR Flash Timing Params */ | |
323 | #define CONFIG_SYS_NOR_FTIM0 FTIM0_NOR_TACSE(0x4) | \ | |
324 | FTIM0_NOR_TEADC(0x5) | \ | |
325 | FTIM0_NOR_TEAHC(0x5) | |
326 | #define CONFIG_SYS_NOR_FTIM1 FTIM1_NOR_TACO(0x1e) | \ | |
327 | FTIM1_NOR_TRAD_NOR(0x0f) | |
328 | #define CONFIG_SYS_NOR_FTIM2 FTIM2_NOR_TCS(0x4) | \ | |
329 | FTIM2_NOR_TCH(0x4) | \ | |
330 | FTIM2_NOR_TWP(0x1c) | |
331 | #define CONFIG_SYS_NOR_FTIM3 0x0 | |
332 | ||
333 | #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} | |
334 | #define CONFIG_SYS_FLASH_QUIET_TEST | |
335 | #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ | |
336 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ | |
337 | ||
338 | #undef CONFIG_SYS_FLASH_CHECKSUM | |
339 | #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
340 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
341 | ||
342 | /* CFI for NOR Flash */ | |
343 | #define CONFIG_FLASH_CFI_DRIVER | |
344 | #define CONFIG_SYS_FLASH_CFI | |
345 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
346 | #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE | |
347 | ||
348 | /* NAND Flash on IFC */ | |
349 | #define CONFIG_SYS_NAND_BASE 0xff800000 | |
350 | #ifdef CONFIG_PHYS_64BIT | |
351 | #define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull | |
352 | #else | |
353 | #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE | |
354 | #endif | |
355 | ||
ac688078 ZQ |
356 | #define CONFIG_MTD_DEVICE |
357 | #define CONFIG_MTD_PARTITION | |
358 | #define CONFIG_CMD_MTDPARTS | |
359 | #define MTDIDS_DEFAULT "nand0=ff800000.flash" | |
360 | #define MTDPARTS_DEFAULT \ | |
361 | "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" | |
362 | ||
49249e13 PA |
363 | #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ |
364 | | CSPR_PORT_SIZE_8 \ | |
365 | | CSPR_MSEL_NAND \ | |
366 | | CSPR_V) | |
367 | #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) | |
e512c50b | 368 | |
7601686c | 369 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
49249e13 PA |
370 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ |
371 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
372 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
373 | | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ | |
374 | | CSOR_NAND_PGS_512 /* Page Size = 512b */ \ | |
375 | | CSOR_NAND_SPRZ_16 /* Spare size = 16 */ \ | |
376 | | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ | |
e512c50b SL |
377 | #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) |
378 | ||
7601686c | 379 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
380 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
381 | #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | |
382 | | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | |
383 | | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ | |
384 | | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \ | |
385 | | CSOR_NAND_PGS_4K /* Page Size = 4K */ \ | |
386 | | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \ | |
387 | | CSOR_NAND_PB(128)) /*Pages Per Block = 128 */ | |
388 | #define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024) | |
389 | #endif | |
49249e13 | 390 | |
d793e5a8 DD |
391 | #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } |
392 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
d793e5a8 | 393 | #define CONFIG_CMD_NAND |
d793e5a8 | 394 | |
7601686c | 395 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
49249e13 PA |
396 | /* NAND Flash Timing Params */ |
397 | #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ | |
398 | FTIM0_NAND_TWP(0x0C) | \ | |
399 | FTIM0_NAND_TWCHT(0x04) | \ | |
400 | FTIM0_NAND_TWH(0x05) | |
401 | #define CONFIG_SYS_NAND_FTIM1 FTIM1_NAND_TADLE(0x1d) | \ | |
402 | FTIM1_NAND_TWBE(0x1d) | \ | |
403 | FTIM1_NAND_TRR(0x07) | \ | |
404 | FTIM1_NAND_TRP(0x0c) | |
405 | #define CONFIG_SYS_NAND_FTIM2 FTIM2_NAND_TRAD(0x0c) | \ | |
406 | FTIM2_NAND_TREH(0x05) | \ | |
407 | FTIM2_NAND_TWHRE(0x0f) | |
408 | #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) | |
409 | ||
7601686c | 410 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
411 | /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ |
412 | /* ONFI NAND Flash mode0 Timing Params */ | |
413 | #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ | |
414 | FTIM0_NAND_TWP(0x18) | \ | |
415 | FTIM0_NAND_TWCHT(0x07) | \ | |
416 | FTIM0_NAND_TWH(0x0a)) | |
417 | #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32)| \ | |
418 | FTIM1_NAND_TWBE(0x39) | \ | |
419 | FTIM1_NAND_TRR(0x0e) | \ | |
420 | FTIM1_NAND_TRP(0x18)) | |
421 | #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \ | |
422 | FTIM2_NAND_TREH(0x0a) | \ | |
423 | FTIM2_NAND_TWHRE(0x1e)) | |
424 | #define CONFIG_SYS_NAND_FTIM3 0x0 | |
425 | #endif | |
426 | ||
49249e13 PA |
427 | #define CONFIG_SYS_NAND_DDR_LAW 11 |
428 | ||
429 | /* Set up IFC registers for boot location NOR/NAND */ | |
0fa934d2 | 430 | #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT) |
d793e5a8 DD |
431 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR |
432 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK | |
433 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR | |
434 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
435 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
436 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
437 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
438 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR_CSPR | |
439 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK | |
440 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR | |
441 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
442 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
443 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
444 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
445 | #else | |
49249e13 PA |
446 | #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR |
447 | #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK | |
448 | #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR | |
449 | #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 | |
450 | #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 | |
451 | #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 | |
452 | #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 | |
453 | #define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR | |
454 | #define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK | |
455 | #define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR | |
456 | #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 | |
457 | #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 | |
458 | #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 | |
459 | #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 | |
d793e5a8 DD |
460 | #endif |
461 | ||
49249e13 PA |
462 | /* CPLD on IFC */ |
463 | #define CONFIG_SYS_CPLD_BASE 0xffb00000 | |
464 | ||
465 | #ifdef CONFIG_PHYS_64BIT | |
466 | #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffb00000ull | |
467 | #else | |
468 | #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE | |
469 | #endif | |
470 | ||
471 | #define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ | |
472 | | CSPR_PORT_SIZE_8 \ | |
473 | | CSPR_MSEL_GPCM \ | |
474 | | CSPR_V) | |
475 | #define CONFIG_SYS_AMASK3 IFC_AMASK(64*1024) | |
476 | #define CONFIG_SYS_CSOR3 0x0 | |
477 | /* CPLD Timing parameters for IFC CS3 */ | |
478 | #define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ | |
479 | FTIM0_GPCM_TEADC(0x0e) | \ | |
480 | FTIM0_GPCM_TEAHC(0x0e)) | |
481 | #define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ | |
482 | FTIM1_GPCM_TRAD(0x1f)) | |
483 | #define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ | |
de519163 | 484 | FTIM2_GPCM_TCH(0x8) | \ |
49249e13 PA |
485 | FTIM2_GPCM_TWP(0x1f)) |
486 | #define CONFIG_SYS_CS3_FTIM3 0x0 | |
49249e13 | 487 | |
76c9aaf5 AB |
488 | #if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) || \ |
489 | defined(CONFIG_RAMBOOT_NAND) | |
49249e13 PA |
490 | #define CONFIG_SYS_RAMBOOT |
491 | #define CONFIG_SYS_EXTRA_ENV_RELOC | |
492 | #else | |
493 | #undef CONFIG_SYS_RAMBOOT | |
494 | #endif | |
495 | ||
74fa22ed | 496 | #ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399 |
50c76367 | 497 | #if !defined(CONFIG_SPL) && !defined(CONFIG_SYS_RAMBOOT) |
74fa22ed PK |
498 | #define CONFIG_A003399_NOR_WORKAROUND |
499 | #endif | |
500 | #endif | |
501 | ||
49249e13 PA |
502 | #define CONFIG_BOARD_EARLY_INIT_R |
503 | ||
504 | #define CONFIG_SYS_INIT_RAM_LOCK | |
505 | #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ | |
b39d1213 | 506 | #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ |
49249e13 | 507 | |
b39d1213 | 508 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE \ |
49249e13 PA |
509 | - GENERATED_GBL_DATA_SIZE) |
510 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET | |
511 | ||
9307cbab | 512 | #define CONFIG_SYS_MONITOR_LEN (768 * 1024) |
49249e13 PA |
513 | #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc*/ |
514 | ||
c9e1f588 YZ |
515 | /* |
516 | * Config the L2 Cache as L2 SRAM | |
517 | */ | |
518 | #if defined(CONFIG_SPL_BUILD) | |
519 | #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) | |
520 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
521 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
522 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
523 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
524 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 | |
525 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) | |
526 | #define CONFIG_SPL_RELOC_STACK_SIZE (16 << 10) | |
527 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) | |
528 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (128 << 10) | |
529 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 96 * 1024) | |
530 | #elif defined(CONFIG_NAND) | |
531 | #ifdef CONFIG_TPL_BUILD | |
532 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
533 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
534 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
535 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
536 | #define CONFIG_SPL_RELOC_TEXT_BASE 0xD0001000 | |
537 | #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024) | |
538 | #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024) | |
539 | #define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10) | |
540 | #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024) | |
541 | #else | |
542 | #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 | |
543 | #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR | |
544 | #define CONFIG_SYS_L2_SIZE (256 << 10) | |
545 | #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) | |
546 | #define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x3000) | |
547 | #define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF) | |
548 | #endif | |
549 | #endif | |
550 | #endif | |
551 | ||
49249e13 PA |
552 | /* Serial Port */ |
553 | #define CONFIG_CONS_INDEX 1 | |
554 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
49249e13 PA |
555 | #define CONFIG_SYS_NS16550_SERIAL |
556 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
557 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
c9e1f588 | 558 | #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL) |
d793e5a8 DD |
559 | #define CONFIG_NS16550_MIN_FUNCTIONS |
560 | #endif | |
49249e13 | 561 | |
49249e13 PA |
562 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
563 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} | |
564 | ||
565 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) | |
566 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
567 | ||
00f792e0 HS |
568 | /* I2C */ |
569 | #define CONFIG_SYS_I2C | |
570 | #define CONFIG_SYS_I2C_FSL | |
571 | #define CONFIG_SYS_FSL_I2C_SPEED 400000 | |
572 | #define CONFIG_SYS_FSL_I2C_SLAVE 0x7F | |
573 | #define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 | |
574 | #define CONFIG_SYS_FSL_I2C2_SPEED 400000 | |
575 | #define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F | |
576 | #define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 | |
ad89da0c | 577 | #define I2C_PCA9557_ADDR1 0x18 |
e512c50b | 578 | #define I2C_PCA9557_ADDR2 0x19 |
ad89da0c | 579 | #define I2C_PCA9557_BUS_NUM 0 |
49249e13 PA |
580 | |
581 | /* I2C EEPROM */ | |
7601686c | 582 | #if defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
583 | #define CONFIG_ID_EEPROM |
584 | #ifdef CONFIG_ID_EEPROM | |
585 | #define CONFIG_SYS_I2C_EEPROM_NXID | |
586 | #endif | |
587 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
588 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 | |
589 | #define CONFIG_SYS_EEPROM_BUS_NUM 0 | |
590 | #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ | |
591 | #endif | |
49249e13 PA |
592 | /* enable read and write access to EEPROM */ |
593 | #define CONFIG_CMD_EEPROM | |
49249e13 PA |
594 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 |
595 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 | |
596 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 | |
597 | ||
598 | /* RTC */ | |
599 | #define CONFIG_RTC_PT7C4338 | |
600 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 | |
601 | ||
49249e13 PA |
602 | /* |
603 | * SPI interface will not be available in case of NAND boot SPI CS0 will be | |
604 | * used for SLIC | |
605 | */ | |
0fa934d2 | 606 | #if !defined(CONFIG_NAND) || !defined(CONFIG_NAND_SECBOOT) |
49249e13 | 607 | /* eSPI - Enhanced SPI */ |
49249e13 PA |
608 | #define CONFIG_SF_DEFAULT_SPEED 10000000 |
609 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 | |
d793e5a8 | 610 | #endif |
49249e13 PA |
611 | |
612 | #if defined(CONFIG_TSEC_ENET) | |
49249e13 PA |
613 | #define CONFIG_MII /* MII PHY management */ |
614 | #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ | |
615 | #define CONFIG_TSEC1 1 | |
616 | #define CONFIG_TSEC1_NAME "eTSEC1" | |
617 | #define CONFIG_TSEC2 1 | |
618 | #define CONFIG_TSEC2_NAME "eTSEC2" | |
619 | #define CONFIG_TSEC3 1 | |
620 | #define CONFIG_TSEC3_NAME "eTSEC3" | |
621 | ||
622 | #define TSEC1_PHY_ADDR 1 | |
623 | #define TSEC2_PHY_ADDR 0 | |
624 | #define TSEC3_PHY_ADDR 2 | |
625 | ||
626 | #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
627 | #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
628 | #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) | |
629 | ||
630 | #define TSEC1_PHYIDX 0 | |
631 | #define TSEC2_PHYIDX 0 | |
632 | #define TSEC3_PHYIDX 0 | |
633 | ||
634 | #define CONFIG_ETHPRIME "eTSEC1" | |
635 | ||
636 | #define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ | |
637 | ||
638 | /* TBI PHY configuration for SGMII mode */ | |
639 | #define CONFIG_TSEC_TBICR_SETTINGS ( \ | |
640 | TBICR_PHY_RESET \ | |
641 | | TBICR_ANEG_ENABLE \ | |
642 | | TBICR_FULL_DUPLEX \ | |
643 | | TBICR_SPEED1_SET \ | |
644 | ) | |
645 | ||
646 | #endif /* CONFIG_TSEC_ENET */ | |
647 | ||
49249e13 PA |
648 | /* SATA */ |
649 | #define CONFIG_FSL_SATA | |
9760b274 | 650 | #define CONFIG_FSL_SATA_V2 |
49249e13 PA |
651 | #define CONFIG_LIBATA |
652 | ||
653 | #ifdef CONFIG_FSL_SATA | |
654 | #define CONFIG_SYS_SATA_MAX_DEVICE 2 | |
655 | #define CONFIG_SATA1 | |
656 | #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR | |
657 | #define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA | |
658 | #define CONFIG_SATA2 | |
659 | #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR | |
660 | #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA | |
661 | ||
662 | #define CONFIG_CMD_SATA | |
663 | #define CONFIG_LBA48 | |
664 | #endif /* #ifdef CONFIG_FSL_SATA */ | |
665 | ||
49249e13 | 666 | #ifdef CONFIG_MMC |
49249e13 | 667 | #define CONFIG_FSL_ESDHC |
49249e13 PA |
668 | #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR |
669 | #endif | |
670 | ||
671 | #define CONFIG_HAS_FSL_DR_USB | |
672 | ||
673 | #if defined(CONFIG_HAS_FSL_DR_USB) | |
674 | #define CONFIG_USB_EHCI | |
675 | ||
676 | #ifdef CONFIG_USB_EHCI | |
49249e13 PA |
677 | #define CONFIG_EHCI_HCD_INIT_AFTER_RESET |
678 | #define CONFIG_USB_EHCI_FSL | |
49249e13 PA |
679 | #endif |
680 | #endif | |
681 | ||
682 | /* | |
683 | * Environment | |
684 | */ | |
c9e1f588 | 685 | #if defined(CONFIG_SDCARD) |
49249e13 | 686 | #define CONFIG_ENV_IS_IN_MMC |
4394d0c2 | 687 | #define CONFIG_FSL_FIXED_MMC_LOCATION |
49249e13 PA |
688 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
689 | #define CONFIG_ENV_SIZE 0x2000 | |
c9e1f588 | 690 | #elif defined(CONFIG_SPIFLASH) |
49249e13 PA |
691 | #define CONFIG_ENV_IS_IN_SPI_FLASH |
692 | #define CONFIG_ENV_SPI_BUS 0 | |
693 | #define CONFIG_ENV_SPI_CS 0 | |
694 | #define CONFIG_ENV_SPI_MAX_HZ 10000000 | |
695 | #define CONFIG_ENV_SPI_MODE 0 | |
696 | #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ | |
697 | #define CONFIG_ENV_SECT_SIZE 0x10000 | |
698 | #define CONFIG_ENV_SIZE 0x2000 | |
0fa934d2 | 699 | #elif defined(CONFIG_NAND) |
d793e5a8 | 700 | #define CONFIG_ENV_IS_IN_NAND |
c9e1f588 YZ |
701 | #ifdef CONFIG_TPL_BUILD |
702 | #define CONFIG_ENV_SIZE 0x2000 | |
703 | #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) | |
704 | #else | |
7601686c | 705 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
d793e5a8 | 706 | #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE |
e512c50b | 707 | #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ |
7601686c | 708 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
709 | #define CONFIG_ENV_SIZE (16 * 1024) |
710 | #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ | |
711 | #endif | |
c9e1f588 YZ |
712 | #endif |
713 | #define CONFIG_ENV_OFFSET (1024 * 1024) | |
0fa934d2 | 714 | #elif defined(CONFIG_SYS_RAMBOOT) |
49249e13 PA |
715 | #define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */ |
716 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000) | |
717 | #define CONFIG_ENV_SIZE 0x2000 | |
49249e13 PA |
718 | #else |
719 | #define CONFIG_ENV_IS_IN_FLASH | |
49249e13 | 720 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
49249e13 PA |
721 | #define CONFIG_ENV_SIZE 0x2000 |
722 | #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ | |
723 | #endif | |
724 | ||
725 | #define CONFIG_LOADS_ECHO /* echo on for serial download */ | |
726 | #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ | |
727 | ||
728 | /* | |
729 | * Command line configuration. | |
730 | */ | |
49249e13 PA |
731 | #define CONFIG_CMD_DATE |
732 | #define CONFIG_CMD_ERRATA | |
49249e13 | 733 | #define CONFIG_CMD_IRQ |
49249e13 PA |
734 | #define CONFIG_CMD_REGINFO |
735 | ||
736 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
737 | ||
738 | #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ | |
739 | || defined(CONFIG_FSL_SATA) | |
49249e13 PA |
740 | #endif |
741 | ||
737537ef RG |
742 | /* Hash command with SHA acceleration supported in hardware */ |
743 | #ifdef CONFIG_FSL_CAAM | |
744 | #define CONFIG_CMD_HASH | |
745 | #define CONFIG_SHA_HW_ACCEL | |
746 | #endif | |
747 | ||
49249e13 PA |
748 | /* |
749 | * Miscellaneous configurable options | |
750 | */ | |
751 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
752 | #define CONFIG_CMDLINE_EDITING /* Command-line editing */ | |
753 | #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ | |
754 | #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ | |
49249e13 PA |
755 | |
756 | #if defined(CONFIG_CMD_KGDB) | |
757 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ | |
758 | #else | |
759 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
760 | #endif | |
761 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) | |
762 | /* Print Buffer Size */ | |
763 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
764 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ | |
49249e13 | 765 | |
49249e13 PA |
766 | /* |
767 | * For booting Linux, the board info and command line data | |
768 | * have to be in the first 64 MB of memory, since this is | |
769 | * the maximum mapped by the Linux kernel during initialization. | |
770 | */ | |
771 | #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ | |
772 | #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ | |
773 | ||
774 | #if defined(CONFIG_CMD_KGDB) | |
775 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ | |
49249e13 PA |
776 | #endif |
777 | ||
778 | /* | |
779 | * Environment Configuration | |
780 | */ | |
781 | ||
782 | #if defined(CONFIG_TSEC_ENET) | |
783 | #define CONFIG_HAS_ETH0 | |
784 | #define CONFIG_HAS_ETH1 | |
785 | #define CONFIG_HAS_ETH2 | |
786 | #endif | |
787 | ||
8b3637c6 | 788 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
b3f44c21 | 789 | #define CONFIG_BOOTFILE "uImage" |
49249e13 PA |
790 | #define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ |
791 | ||
792 | /* default location for tftp and bootm */ | |
793 | #define CONFIG_LOADADDR 1000000 | |
794 | ||
49249e13 PA |
795 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ |
796 | ||
797 | #define CONFIG_BAUDRATE 115200 | |
798 | ||
799 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
5368c55d | 800 | "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ |
49249e13 | 801 | "netdev=eth0\0" \ |
5368c55d | 802 | "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ |
49249e13 PA |
803 | "loadaddr=1000000\0" \ |
804 | "consoledev=ttyS0\0" \ | |
805 | "ramdiskaddr=2000000\0" \ | |
806 | "ramdiskfile=rootfs.ext2.gz.uboot\0" \ | |
b24a4f62 | 807 | "fdtaddr=1e00000\0" \ |
49249e13 PA |
808 | "fdtfile=p1010rdb.dtb\0" \ |
809 | "bdev=sda1\0" \ | |
810 | "hwconfig=usb1:dr_mode=host,phy_type=utmi\0" \ | |
811 | "othbootargs=ramdisk_size=600000\0" \ | |
812 | "usbfatboot=setenv bootargs root=/dev/ram rw " \ | |
813 | "console=$consoledev,$baudrate $othbootargs; " \ | |
814 | "usb start;" \ | |
815 | "fatload usb 0:2 $loadaddr $bootfile;" \ | |
816 | "fatload usb 0:2 $fdtaddr $fdtfile;" \ | |
817 | "fatload usb 0:2 $ramdiskaddr $ramdiskfile;" \ | |
818 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ | |
819 | "usbext2boot=setenv bootargs root=/dev/ram rw " \ | |
820 | "console=$consoledev,$baudrate $othbootargs; " \ | |
821 | "usb start;" \ | |
822 | "ext2load usb 0:4 $loadaddr $bootfile;" \ | |
823 | "ext2load usb 0:4 $fdtaddr $fdtfile;" \ | |
824 | "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \ | |
e512c50b SL |
825 | "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ |
826 | CONFIG_BOOTMODE | |
827 | ||
7601686c | 828 | #if defined(CONFIG_TARGET_P1010RDB_PA) |
e512c50b SL |
829 | #define CONFIG_BOOTMODE \ |
830 | "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ | |
831 | "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ | |
832 | "boot_bank1=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ | |
833 | "mw.b ffb00011 0; mw.b ffb00009 1; reset\0" \ | |
834 | "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ | |
835 | "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" | |
836 | ||
7601686c | 837 | #elif defined(CONFIG_TARGET_P1010RDB_PB) |
e512c50b SL |
838 | #define CONFIG_BOOTMODE \ |
839 | "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ | |
840 | "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \ | |
841 | "boot_bank1=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ | |
842 | "i2c mw 19 1 12; i2c mw 19 3 e1; reset\0" \ | |
843 | "boot_nand=i2c dev 0; i2c mw 18 1 fc; i2c mw 18 3 0;" \ | |
844 | "i2c mw 19 1 8; i2c mw 19 3 f7; reset\0" \ | |
845 | "boot_spi=i2c dev 0; i2c mw 18 1 fa; i2c mw 18 3 0;" \ | |
846 | "i2c mw 19 1 0; i2c mw 19 3 f7; reset\0" \ | |
847 | "boot_sd=i2c dev 0; i2c mw 18 1 f8; i2c mw 18 3 0;" \ | |
848 | "i2c mw 19 1 4; i2c mw 19 3 f3; reset\0" | |
849 | #endif | |
49249e13 PA |
850 | |
851 | #define CONFIG_RAMBOOTCOMMAND \ | |
852 | "setenv bootargs root=/dev/ram rw " \ | |
853 | "console=$consoledev,$baudrate $othbootargs; " \ | |
854 | "tftp $ramdiskaddr $ramdiskfile;" \ | |
855 | "tftp $loadaddr $bootfile;" \ | |
856 | "tftp $fdtaddr $fdtfile;" \ | |
857 | "bootm $loadaddr $ramdiskaddr $fdtaddr" | |
858 | ||
859 | #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND | |
860 | ||
2f439e80 | 861 | #include <asm/fsl_secure_boot.h> |
2f439e80 | 862 | |
49249e13 | 863 | #endif /* __CONFIG_H */ |