[people/ms/u-boot.git] / include / configs / P1022DS.h

/*
 * Copyright 2010-2011 Freescale Semiconductor, Inc.
 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
 *          Timur Tabi <timur@freescale.com>
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the Free
 * Software Foundation; either version 2 of the License, or (at your option)
 * any later version.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

#include "../board/freescale/common/ics307_clk.h"

#ifdef CONFIG_36BIT
#define CONFIG_PHYS_64BIT
#endif

/* High Level Configuration Options */
#define CONFIG_BOOKE			/* BOOKE */
#define CONFIG_E500			/* BOOKE e500 family */
#define CONFIG_MPC85xx			/* MPC8540/60/55/41/48 */
#define CONFIG_P1022
#define CONFIG_P1022DS
#define CONFIG_MP			/* support multiple processors */

#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE	0xeff80000
#endif

#ifndef CONFIG_RESET_VECTOR_ADDRESS
#define CONFIG_RESET_VECTOR_ADDRESS	0xeffffffc
#endif

#define CONFIG_FSL_ELBC			/* Has Enhanced localbus controller */
#define CONFIG_PCI			/* Enable PCI/PCIE */
#define CONFIG_PCIE1			/* PCIE controler 1 (slot 1) */
#define CONFIG_PCIE2			/* PCIE controler 2 (slot 2) */
#define CONFIG_PCIE3			/* PCIE controler 3 (ULI bridge) */
#define CONFIG_FSL_PCI_INIT		/* Use common FSL init code */
#define CONFIG_FSL_PCIE_RESET		/* need PCIe reset errata */
#define CONFIG_SYS_PCI_64BIT		/* enable 64-bit PCI resources */

#ifdef CONFIG_PHYS_64BIT
#define CONFIG_ENABLE_36BIT_PHYS
#define CONFIG_ADDR_MAP
#define CONFIG_SYS_NUM_ADDR_MAP		16	/* number of TLB1 entries */
#endif

#define CONFIG_FSL_LAW			/* Use common FSL init code */

#define CONFIG_SYS_CLK_FREQ	get_board_sys_clk()
#define CONFIG_DDR_CLK_FREQ	get_board_ddr_clk()
#define CONFIG_ICS307_REFCLK_HZ	33333000  /* ICS307 clock chip ref freq */

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE
#define CONFIG_BTB

#define CONFIG_SYS_MEMTEST_START	0x00000000
#define CONFIG_SYS_MEMTEST_END		0x7fffffff

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default */
#define CONFIG_SYS_CCSRBAR		0xffe00000	/* relocated CCSRBAR */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_CCSRBAR_PHYS		0xfffe00000ull
#else
#define CONFIG_SYS_CCSRBAR_PHYS		CONFIG_SYS_CCSRBAR
#endif
#define CONFIG_SYS_IMMR			CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_DDR_SPD
#define CONFIG_VERY_BIG_RAM
#define CONFIG_FSL_DDR3

#ifdef CONFIG_DDR_ECC
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
#define CONFIG_MEM_INIT_VALUE		0xdeadbeef
#endif

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define CONFIG_SYS_SPD_BUS_NUM		1
#define SPD_EEPROM_ADDRESS		0x51	/* CTLR 0 DIMM 0 */

/*
 * Memory map
 *
 * 0x0000_0000	0x7fff_ffff	DDR			2G Cacheable
 * 0x8000_0000	0xdfff_ffff	PCI Express Mem		1.5G non-cacheable
 * 0xffc0_0000	0xffc2_ffff	PCI IO range		192K non-cacheable
 *
 * Localbus cacheable (TBD)
 * 0xXXXX_XXXX	0xXXXX_XXXX	SRAM			YZ M Cacheable
 *
 * Localbus non-cacheable
 * 0xe000_0000	0xe80f_ffff	Promjet/free		128M non-cacheable
 * 0xe800_0000	0xefff_ffff	FLASH			128M non-cacheable
 * 0xffdf_0000	0xffdf_7fff	PIXIS			32K non-cacheable TLB0
 * 0xffd0_0000	0xffd0_3fff	L1 for stack		16K Cacheable TLB0
 * 0xffe0_0000	0xffef_ffff	CCSR			1M non-cacheable
 */

/*
 * Local Bus Definitions
 */
#define CONFIG_SYS_FLASH_BASE		0xe0000000 /* start of FLASH 128M */
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_FLASH_BASE_PHYS	0xfe0000000ull
#else
#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
#endif

#define CONFIG_FLASH_BR_PRELIM  \
	(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | BR_PS_16 | BR_V)
#define CONFIG_FLASH_OR_PRELIM	(OR_AM_128MB | 0xff7)

#define CONFIG_SYS_BR0_PRELIM	CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
#define CONFIG_SYS_OR0_PRELIM	CONFIG_FLASH_OR_PRELIM  /* NOR Options */

#define CONFIG_SYS_BR1_PRELIM	\
	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
#define CONFIG_SYS_OR1_PRELIM	CONFIG_FLASH_OR_PRELIM

#define CONFIG_SYS_FLASH_BANKS_LIST	\
	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_FLASH_SHOW_PROGRESS	45 /* count down from 45/5: 9..1 */

#define CONFIG_SYS_MAX_FLASH_BANKS	2
#define CONFIG_SYS_MAX_FLASH_SECT	1024

#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE	/* start of monitor */

#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_SYS_FLASH_EMPTY_INFO

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_BOARD_EARLY_INIT_R
#define CONFIG_MISC_INIT_R
#define CONFIG_HWCONFIG

#define CONFIG_FSL_NGPIXIS
#define PIXIS_BASE		0xffdf0000	/* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS		0xfffdf0000ull
#else
#define PIXIS_BASE_PHYS		PIXIS_BASE
#endif

#define CONFIG_SYS_BR2_PRELIM	(BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
#define CONFIG_SYS_OR2_PRELIM	(OR_AM_32KB | 0x6ff7)

#define PIXIS_LBMAP_SWITCH	7
#define PIXIS_LBMAP_MASK	0xF0
#define PIXIS_LBMAP_ALTBANK	0x20

#define CONFIG_SYS_INIT_RAM_LOCK
#define CONFIG_SYS_INIT_RAM_ADDR	0xffd00000 /* Initial L1 address */
#define CONFIG_SYS_INIT_RAM_SIZE		0x00004000 /* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	\
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(6 * 1024 * 1024)

/*
 * Serial Port
 */
#define CONFIG_CONS_INDEX		1
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE	\
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "

/* Video */
#undef CONFIG_FSL_DIU_FB

#ifdef CONFIG_FSL_DIU_FB
#define CONFIG_SYS_DIU_ADDR	(CONFIG_SYS_CCSRBAR + 0x10000)
#define CONFIG_VIDEO
#define CONFIG_CMD_BMP
#define CONFIG_CFB_CONSOLE
#define CONFIG_VGA_AS_SINGLE_DEVICE
#define CONFIG_VIDEO_LOGO
#define CONFIG_VIDEO_BMP_LOGO
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
/*
 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
 * disable empty flash sector detection, which is I/O-intensive.
 */
#undef CONFIG_SYS_FLASH_EMPTY_INFO
#endif

/*
 * Pass open firmware flat tree
 */
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP
#define CONFIG_OF_STDOUT_VIA_ALIAS

/* new uImage format support */
#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE

/* I2C */
#define CONFIG_FSL_I2C
#define CONFIG_HARD_I2C
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_I2C_SPEED		400000
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_SLAVE		0x7F
#define CONFIG_SYS_I2C_NOPROBES		{{0, 0x29}}
#define CONFIG_SYS_I2C_OFFSET		0x3000
#define CONFIG_SYS_I2C2_OFFSET		0x3100

/*
 * I2C2 EEPROM
 */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1
#define CONFIG_SYS_EEPROM_BUS_NUM	1

/*
 * General PCI
 * Memory space is mapped 1-1, but I/O space must start from 0.
 */

/* controller 1, Slot 2, tgtid 1, Base address a000 */
#define CONFIG_SYS_PCIE1_MEM_VIRT	0xc0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc40000000ull
#else
#define CONFIG_SYS_PCIE1_MEM_BUS	0xc0000000
#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc0000000
#endif
#define CONFIG_SYS_PCIE1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE1_IO_VIRT	0xffc20000
#define CONFIG_SYS_PCIE1_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE1_IO_PHYS	0xfffc20000ull
#else
#define CONFIG_SYS_PCIE1_IO_PHYS	0xffc20000
#endif
#define CONFIG_SYS_PCIE1_IO_SIZE	0x00010000	/* 64k */

/* controller 2, direct to uli, tgtid 2, Base address 9000 */
#define CONFIG_SYS_PCIE2_MEM_VIRT	0xa0000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xc20000000ull
#else
#define CONFIG_SYS_PCIE2_MEM_BUS	0xa0000000
#define CONFIG_SYS_PCIE2_MEM_PHYS	0xa0000000
#endif
#define CONFIG_SYS_PCIE2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE2_IO_VIRT	0xffc10000
#define CONFIG_SYS_PCIE2_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE2_IO_PHYS	0xfffc10000ull
#else
#define CONFIG_SYS_PCIE2_IO_PHYS	0xffc10000
#endif
#define CONFIG_SYS_PCIE2_IO_SIZE	0x00010000	/* 64k */

/* controller 3, Slot 1, tgtid 3, Base address b000 */
#define CONFIG_SYS_PCIE3_MEM_VIRT	0x80000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_MEM_BUS	0xe0000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0xc00000000ull
#else
#define CONFIG_SYS_PCIE3_MEM_BUS	0x80000000
#define CONFIG_SYS_PCIE3_MEM_PHYS	0x80000000
#endif
#define CONFIG_SYS_PCIE3_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCIE3_IO_VIRT	0xffc00000
#define CONFIG_SYS_PCIE3_IO_BUS		0x00000000
#ifdef CONFIG_PHYS_64BIT
#define CONFIG_SYS_PCIE3_IO_PHYS	0xfffc00000ull
#else
#define CONFIG_SYS_PCIE3_IO_PHYS	0xffc00000
#endif
#define CONFIG_SYS_PCIE3_IO_SIZE	0x00010000	/* 64k */

#ifdef CONFIG_PCI
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
#define CONFIG_E1000			/* Define e1000 pci Ethernet card */
#endif

/* SATA */
#define CONFIG_LIBATA
#define CONFIG_FSL_SATA
#define CONFIG_FSL_SATA_V2

#define CONFIG_SYS_SATA_MAX_DEVICE	2
#define CONFIG_SATA1
#define CONFIG_SYS_SATA1		CONFIG_SYS_MPC85xx_SATA1_ADDR
#define CONFIG_SYS_SATA1_FLAGS		FLAGS_DMA
#define CONFIG_SATA2
#define CONFIG_SYS_SATA2		CONFIG_SYS_MPC85xx_SATA2_ADDR
#define CONFIG_SYS_SATA2_FLAGS		FLAGS_DMA

#ifdef CONFIG_FSL_SATA
#define CONFIG_LBA48
#define CONFIG_CMD_SATA
#define CONFIG_DOS_PARTITION
#define CONFIG_CMD_EXT2
#endif

#define CONFIG_MMC
#ifdef CONFIG_MMC
#define CONFIG_CMD_MMC
#define CONFIG_FSL_ESDHC
#define CONFIG_GENERIC_MMC
#define CONFIG_SYS_FSL_ESDHC_ADDR	CONFIG_SYS_MPC85xx_ESDHC_ADDR
#endif

#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_FAT
#define CONFIG_DOS_PARTITION
#endif

#define CONFIG_TSEC_ENET
#ifdef CONFIG_TSEC_ENET

#define CONFIG_TSECV2
#define CONFIG_NET_MULTI

#define CONFIG_MII			/* MII PHY management */
#define CONFIG_TSEC1		1
#define CONFIG_TSEC1_NAME	"eTSEC1"
#define CONFIG_TSEC2		1
#define CONFIG_TSEC2_NAME	"eTSEC2"

#define TSEC1_PHY_ADDR		1
#define TSEC2_PHY_ADDR		2

#define TSEC1_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)
#define TSEC2_FLAGS		(TSEC_GIGABIT | TSEC_REDUCED)

#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0

#define CONFIG_ETHPRIME		"eTSEC1"

#define CONFIG_PHY_GIGE		/* Include GbE speed/duplex detection */
#endif

/*
 * Environment
 */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_OVERWRITE
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x2000
#define CONFIG_ENV_SECT_SIZE	0x20000

#define CONFIG_LOADS_ECHO
#define CONFIG_SYS_LOADS_BAUD_CHANGE

/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ELF
#define CONFIG_CMD_ERRATA
#define CONFIG_CMD_IRQ
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII
#define CONFIG_CMD_PING
#define CONFIG_CMD_SETEXPR
#define CONFIG_CMD_REGINFO

#ifdef CONFIG_PCI
#define CONFIG_CMD_PCI
#define CONFIG_CMD_NET
#endif

/*
 * USB
 */
#define CONFIG_USB_EHCI

#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
#define CONFIG_USB_EHCI_FSL
#define CONFIG_USB_STORAGE
#define CONFIG_CMD_FAT
#endif

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory	*/
#define CONFIG_CMDLINE_EDITING			/* Command-line editing */
#define CONFIG_AUTO_COMPLETE			/* add autocompletion support */
#define CONFIG_SYS_LOAD_ADDR	0x2000000	/* default load address */
#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt */
#ifdef CONFIG_CMD_KGDB
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size */
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size */
#endif
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS	16
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ		1000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 16 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ	(16 << 20)	/* Initial Memory map for Linux*/
#define CONFIG_SYS_BOOTM_LEN	(16 << 20)	/* Increase max gunzip size */

#ifdef CONFIG_CMD_KGDB
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*
 * Environment Configuration
 */

#define CONFIG_HOSTNAME		p1022ds
#define CONFIG_ROOTPATH		/opt/nfsroot
#define CONFIG_BOOTFILE		uImage
#define CONFIG_UBOOTPATH	u-boot.bin	/* U-Boot image on TFTP server */

#define CONFIG_LOADADDR		1000000

#define CONFIG_BOOTDELAY	10	/* -1 disables auto-boot */
#define CONFIG_BOOTARGS

#define CONFIG_BAUDRATE	115200

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"perf_mode=stable\0"						\
	"memctl_intlv_ctl=2\0"						\
	"netdev=eth0\0"							\
	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0"				\
	"tftpflash=tftpboot $loadaddr $uboot; "				\
		"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "	\
		"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
		"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; "	\
		"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; "		\
		"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0"	\
	"consoledev=ttyS0\0"						\
	"ramdiskaddr=2000000\0"						\
	"ramdiskfile=uramdisk\0"  		      	        	\
	"fdtaddr=c00000\0"	  			      		\
	"fdtfile=p1022ds.dtb\0"	  					\
	"bdev=sda3\0"		  			      		\
	"diuregs=md e002c000 1d\0"			 		\
	"dium=mw e002c01c\0" 						\
	"diuerr=md e002c014 1\0" 					\
	"othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
	"monitor=0-DVI\0"

#define CONFIG_HDBOOT					\
	"setenv bootargs root=/dev/$bdev rw "		\
	"console=$consoledev,$baudrate $othbootargs;"	\
	"tftp $loadaddr $bootfile;"			\
	"tftp $fdtaddr $fdtfile;"			\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_NFSBOOTCOMMAND						\
	"setenv bootargs root=/dev/nfs rw "				\
	"nfsroot=$serverip:$rootpath "					\
	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	"console=$consoledev,$baudrate $othbootargs;"			\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr - $fdtaddr"

#define CONFIG_RAMBOOTCOMMAND						\
	"setenv bootargs root=/dev/ram rw "				\
	"console=$consoledev,$baudrate $othbootargs;"			\
	"tftp $ramdiskaddr $ramdiskfile;"				\
	"tftp $loadaddr $bootfile;"					\
	"tftp $fdtaddr $fdtfile;"					\
	"bootm $loadaddr $ramdiskaddr $fdtaddr"

#define CONFIG_BOOTCOMMAND		CONFIG_RAMBOOTCOMMAND

#endif
Commit	Line	Data
c59e1b4d	1	/*
7c57f3e8	2	* Copyright 2010-2011 Freescale Semiconductor, Inc.
c59e1b4d TT	3	* Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
	4	* Timur Tabi <timur@freescale.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms of the GNU General Public License as published by the Free
	8	* Software Foundation; either version 2 of the License, or (at your option)
	9	* any later version.
	10	*/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	#include "../board/freescale/common/ics307_clk.h"
	16
9899ac19 JY	17	#ifdef CONFIG_36BIT
	18	#define CONFIG_PHYS_64BIT
	19	#endif
	20
c59e1b4d TT	21	/* High Level Configuration Options */
	22	#define CONFIG_BOOKE /* BOOKE */
	23	#define CONFIG_E500 /* BOOKE e500 family */
	24	#define CONFIG_MPC85xx /* MPC8540/60/55/41/48 */
	25	#define CONFIG_P1022
	26	#define CONFIG_P1022DS
	27	#define CONFIG_MP /* support multiple processors */
	28
2ae18241 WD	29	#ifndef CONFIG_SYS_TEXT_BASE
	30	#define CONFIG_SYS_TEXT_BASE 0xeff80000
	31	#endif
	32
7a577fda KG	33	#ifndef CONFIG_RESET_VECTOR_ADDRESS
	34	#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
	35	#endif
	36
c59e1b4d TT	37	#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
	38	#define CONFIG_PCI /* Enable PCI/PCIE */
	39	#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
	40	#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
	41	#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
	42	#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
	43	#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
	44	#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
	45
9899ac19	46	#ifdef CONFIG_PHYS_64BIT
c59e1b4d TT	47	#define CONFIG_ENABLE_36BIT_PHYS
	48	#define CONFIG_ADDR_MAP
	49	#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
9899ac19	50	#endif
c59e1b4d TT	51
	52	#define CONFIG_FSL_LAW /* Use common FSL init code */
	53
	54	#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
	55	#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
	56	#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
	57
	58	/*
	59	* These can be toggled for performance analysis, otherwise use default.
	60	*/
	61	#define CONFIG_L2_CACHE
	62	#define CONFIG_BTB
	63
	64	#define CONFIG_SYS_MEMTEST_START 0x00000000
	65	#define CONFIG_SYS_MEMTEST_END 0x7fffffff
	66
	67	/*
	68	* Base addresses -- Note these are effective addresses where the
	69	* actual resources get mapped (not physical addresses)
	70	*/
	71	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
	72	#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */
9899ac19	73	#ifdef CONFIG_PHYS_64BIT
c59e1b4d	74	#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull
9899ac19 JY	75	#else
	76	#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR
	77	#endif
c59e1b4d TT	78	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
c59e1b4d TT	79
c59e1b4d TT	80	/* DDR Setup */
	81	#define CONFIG_DDR_SPD
	82	#define CONFIG_VERY_BIG_RAM
	83	#define CONFIG_FSL_DDR3
	84
	85	#ifdef CONFIG_DDR_ECC
	86	#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
	87	#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
	88	#endif
	89
	90	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
	91	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
	92
	93	#define CONFIG_NUM_DDR_CONTROLLERS 1
	94	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	95	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	96
	97	/* I2C addresses of SPD EEPROMs */
	98	#define CONFIG_SYS_SPD_BUS_NUM 1
c39f44dc	99	#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
c59e1b4d TT	100
	101	/*
	102	* Memory map
	103	*
	104	* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
	105	* 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
	106	* 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
	107	*
	108	* Localbus cacheable (TBD)
	109	* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
	110	*
	111	* Localbus non-cacheable
	112	* 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
	113	* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
	114	* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
	115	* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
	116	* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
	117	*/
	118
	119	/*
	120	* Local Bus Definitions
	121	*/
	122	#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
9899ac19	123	#ifdef CONFIG_PHYS_64BIT
c59e1b4d	124	#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
9899ac19 JY	125	#else
	126	#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
	127	#endif
c59e1b4d TT	128
	129	#define CONFIG_FLASH_BR_PRELIM \
	130	(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) \| BR_PS_16 \| BR_V)
	131	#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB \| 0xff7)
	132
	133	#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
	134	#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
	135
	136	#define CONFIG_SYS_BR1_PRELIM \
	137	(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \| BR_PS_16 \| BR_V)
	138	#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM
	139
	140	#define CONFIG_SYS_FLASH_BANKS_LIST \
	141	{CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
	142	#define CONFIG_SYS_FLASH_QUIET_TEST
	143	#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
	144
	145	#define CONFIG_SYS_MAX_FLASH_BANKS 2
	146	#define CONFIG_SYS_MAX_FLASH_SECT 1024
	147
14d0a02a	148	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
c59e1b4d TT	149
	150	#define CONFIG_FLASH_CFI_DRIVER
	151	#define CONFIG_SYS_FLASH_CFI
	152	#define CONFIG_SYS_FLASH_EMPTY_INFO
	153
	154	#define CONFIG_BOARD_EARLY_INIT_F
	155	#define CONFIG_BOARD_EARLY_INIT_R
	156	#define CONFIG_MISC_INIT_R
a2d12f88	157	#define CONFIG_HWCONFIG
c59e1b4d TT	158
	159	#define CONFIG_FSL_NGPIXIS
	160	#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
9899ac19	161	#ifdef CONFIG_PHYS_64BIT
c59e1b4d	162	#define PIXIS_BASE_PHYS 0xfffdf0000ull
9899ac19 JY	163	#else
	164	#define PIXIS_BASE_PHYS PIXIS_BASE
	165	#endif
c59e1b4d TT	166
	167	#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) \| BR_PS_8 \| BR_V)
	168	#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB \| 0x6ff7)
	169
	170	#define PIXIS_LBMAP_SWITCH 7
2906845a	171	#define PIXIS_LBMAP_MASK 0xF0
c59e1b4d TT	172	#define PIXIS_LBMAP_ALTBANK 0x20
	173
	174	#define CONFIG_SYS_INIT_RAM_LOCK
	175	#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
553f0982	176	#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
c59e1b4d	177
c59e1b4d	178	#define CONFIG_SYS_GBL_DATA_OFFSET \
25ddd1fb	179	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
c59e1b4d TT	180	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
	181
	182	#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
	183	#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
	184
	185	/*
	186	* Serial Port
	187	*/
	188	#define CONFIG_CONS_INDEX 1
	189	#define CONFIG_SYS_NS16550
	190	#define CONFIG_SYS_NS16550_SERIAL
	191	#define CONFIG_SYS_NS16550_REG_SIZE 1
	192	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
	193
	194	#define CONFIG_SYS_BAUDRATE_TABLE \
	195	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
	196
	197	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
	198	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
	199
	200	/* Use the HUSH parser */
	201	#define CONFIG_SYS_HUSH_PARSER
	202	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
	203
c59e1b4d	204	/* Video */
d5e01e49 TT	205	#undef CONFIG_FSL_DIU_FB
	206
	207	#ifdef CONFIG_FSL_DIU_FB
	208	#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
	209	#define CONFIG_VIDEO
	210	#define CONFIG_CMD_BMP
c59e1b4d TT	211	#define CONFIG_CFB_CONSOLE
c59e1b4d TT	212	#define CONFIG_VGA_AS_SINGLE_DEVICE
d5e01e49 TT	213	#define CONFIG_VIDEO_LOGO
d5e01e49 TT	214	#define CONFIG_VIDEO_BMP_LOGO
55b05237 TT	215	#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
	216	/*
	217	* With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
	218	* disable empty flash sector detection, which is I/O-intensive.
	219	*/
	220	#undef CONFIG_SYS_FLASH_EMPTY_INFO
c59e1b4d TT	221	#endif
	222
	223	/*
	224	* Pass open firmware flat tree
	225	*/
	226	#define CONFIG_OF_LIBFDT
	227	#define CONFIG_OF_BOARD_SETUP
	228	#define CONFIG_OF_STDOUT_VIA_ALIAS
	229
	230	/* new uImage format support */
	231	#define CONFIG_FIT
	232	#define CONFIG_FIT_VERBOSE
	233
	234	/* I2C */
	235	#define CONFIG_FSL_I2C
	236	#define CONFIG_HARD_I2C
	237	#define CONFIG_I2C_MULTI_BUS
	238	#define CONFIG_SYS_I2C_SPEED 400000
	239	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	240	#define CONFIG_SYS_I2C_SLAVE 0x7F
	241	#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
	242	#define CONFIG_SYS_I2C_OFFSET 0x3000
	243	#define CONFIG_SYS_I2C2_OFFSET 0x3100
	244
	245	/*
	246	* I2C2 EEPROM
	247	*/
	248	#define CONFIG_ID_EEPROM
	249	#define CONFIG_SYS_I2C_EEPROM_NXID
	250	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
	251	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	252	#define CONFIG_SYS_EEPROM_BUS_NUM 1
	253
	254	/*
	255	* General PCI
	256	* Memory space is mapped 1-1, but I/O space must start from 0.
	257	*/
	258
	259	/* controller 1, Slot 2, tgtid 1, Base address a000 */
	260	#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
9899ac19	261	#ifdef CONFIG_PHYS_64BIT
c59e1b4d TT	262	#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
c59e1b4d TT	263	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
9899ac19 JY	264	#else
	265	#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
	266	#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
	267	#endif
c59e1b4d TT	268	#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
	269	#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
	270	#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
9899ac19	271	#ifdef CONFIG_PHYS_64BIT
c59e1b4d	272	#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
9899ac19 JY	273	#else
	274	#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
	275	#endif
c59e1b4d TT	276	#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
	277
	278	/* controller 2, direct to uli, tgtid 2, Base address 9000 */
	279	#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
9899ac19	280	#ifdef CONFIG_PHYS_64BIT
c59e1b4d TT	281	#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
c59e1b4d TT	282	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
9899ac19 JY	283	#else
	284	#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
	285	#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
	286	#endif
c59e1b4d TT	287	#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
	288	#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
	289	#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
9899ac19	290	#ifdef CONFIG_PHYS_64BIT
c59e1b4d	291	#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
9899ac19 JY	292	#else
	293	#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
	294	#endif
c59e1b4d TT	295	#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
	296
	297	/* controller 3, Slot 1, tgtid 3, Base address b000 */
	298	#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
9899ac19	299	#ifdef CONFIG_PHYS_64BIT
c59e1b4d TT	300	#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
c59e1b4d TT	301	#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
9899ac19 JY	302	#else
	303	#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
	304	#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
	305	#endif
c59e1b4d TT	306	#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
	307	#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
	308	#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
9899ac19	309	#ifdef CONFIG_PHYS_64BIT
c59e1b4d	310	#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
9899ac19 JY	311	#else
	312	#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
	313	#endif
c59e1b4d TT	314	#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
	315
	316	#ifdef CONFIG_PCI
	317	#define CONFIG_NET_MULTI
	318	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	319	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
16855ec1	320	#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
c59e1b4d TT	321	#endif
	322
	323	/* SATA */
	324	#define CONFIG_LIBATA
	325	#define CONFIG_FSL_SATA
2d7534a3	326	#define CONFIG_FSL_SATA_V2
c59e1b4d TT	327
	328	#define CONFIG_SYS_SATA_MAX_DEVICE 2
	329	#define CONFIG_SATA1
	330	#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
	331	#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
	332	#define CONFIG_SATA2
	333	#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
	334	#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
	335
	336	#ifdef CONFIG_FSL_SATA
	337	#define CONFIG_LBA48
	338	#define CONFIG_CMD_SATA
	339	#define CONFIG_DOS_PARTITION
	340	#define CONFIG_CMD_EXT2
	341	#endif
	342
	343	#define CONFIG_MMC
	344	#ifdef CONFIG_MMC
	345	#define CONFIG_CMD_MMC
	346	#define CONFIG_FSL_ESDHC
	347	#define CONFIG_GENERIC_MMC
	348	#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
	349	#endif
	350
	351	#if defined(CONFIG_MMC) \|\| defined(CONFIG_USB_EHCI)
	352	#define CONFIG_CMD_EXT2
	353	#define CONFIG_CMD_FAT
	354	#define CONFIG_DOS_PARTITION
	355	#endif
	356
	357	#define CONFIG_TSEC_ENET
	358	#ifdef CONFIG_TSEC_ENET
	359
	360	#define CONFIG_TSECV2
	361	#define CONFIG_NET_MULTI
	362
	363	#define CONFIG_MII /* MII PHY management */
	364	#define CONFIG_TSEC1 1
	365	#define CONFIG_TSEC1_NAME "eTSEC1"
	366	#define CONFIG_TSEC2 1
	367	#define CONFIG_TSEC2_NAME "eTSEC2"
	368
	369	#define TSEC1_PHY_ADDR 1
	370	#define TSEC2_PHY_ADDR 2
	371
	372	#define TSEC1_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	373	#define TSEC2_FLAGS (TSEC_GIGABIT \| TSEC_REDUCED)
	374
	375	#define TSEC1_PHYIDX 0
	376	#define TSEC2_PHYIDX 0
	377
	378	#define CONFIG_ETHPRIME "eTSEC1"
	379
	380	#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
	381	#endif
	382
	383	/*
	384	* Environment
	385	*/
	386	#define CONFIG_ENV_IS_IN_FLASH
	387	#define CONFIG_ENV_OVERWRITE
	388	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
	389	#define CONFIG_ENV_SIZE 0x2000
	390	#define CONFIG_ENV_SECT_SIZE 0x20000
391
392	#define CONFIG_LOADS_ECHO
393	#define CONFIG_SYS_LOADS_BAUD_CHANGE
394
395	/*
396	* Command line configuration.
397	*/
398	#include <config_cmd_default.h>
399
79ee3448 KG	400	#define CONFIG_CMD_ELF
79ee3448 KG	401	#define CONFIG_CMD_ERRATA
c59e1b4d	402	#define CONFIG_CMD_IRQ
c59e1b4d TT	403	#define CONFIG_CMD_I2C
c59e1b4d TT	404	#define CONFIG_CMD_MII
79ee3448	405	#define CONFIG_CMD_PING
c59e1b4d	406	#define CONFIG_CMD_SETEXPR
b8339e2b	407	#define CONFIG_CMD_REGINFO
c59e1b4d TT	408
	409	#ifdef CONFIG_PCI
	410	#define CONFIG_CMD_PCI
	411	#define CONFIG_CMD_NET
	412	#endif
	413
	414	/*
	415	* USB
	416	*/
	417	#define CONFIG_USB_EHCI
	418
	419	#ifdef CONFIG_USB_EHCI
	420	#define CONFIG_CMD_USB
	421	#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
	422	#define CONFIG_USB_EHCI_FSL
	423	#define CONFIG_USB_STORAGE
	424	#define CONFIG_CMD_FAT
	425	#endif
	426
	427	/*
	428	* Miscellaneous configurable options
	429	*/
	430	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	431	#define CONFIG_CMDLINE_EDITING /* Command-line editing */
5be58f5f	432	#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
c59e1b4d TT	433	#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
	434	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
	435	#ifdef CONFIG_CMD_KGDB
	436	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
	437	#else
	438	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	439	#endif
	440	/* Print Buffer Size */
	441	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
	442	#define CONFIG_SYS_MAXARGS 16
	443	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	444	#define CONFIG_SYS_HZ 1000
	445
	446	/*
	447	* For booting Linux, the board info and command line data
	448	* have to be in the first 16 MB of memory, since this is
	449	* the maximum mapped by the Linux kernel during initialization.
	450	*/
	451	#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
7c57f3e8	452	#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
c59e1b4d	453
c59e1b4d TT	454	#ifdef CONFIG_CMD_KGDB
	455	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	456	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	457	#endif
	458
	459	/*
	460	* Environment Configuration
	461	*/
	462
	463	#define CONFIG_HOSTNAME p1022ds
	464	#define CONFIG_ROOTPATH /opt/nfsroot
	465	#define CONFIG_BOOTFILE uImage
	466	#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
	467
	468	#define CONFIG_LOADADDR 1000000
	469
	470	#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
	471	#define CONFIG_BOOTARGS
	472
	473	#define CONFIG_BAUDRATE 115200
	474
	475	#define CONFIG_EXTRA_ENV_SETTINGS \
	476	"perf_mode=stable\0" \
	477	"memctl_intlv_ctl=2\0" \
	478	"netdev=eth0\0" \
	479	"uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
	480	"tftpflash=tftpboot $loadaddr $uboot; " \
14d0a02a WD	481	"protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	482	"erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	483	"cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
	484	"protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
	485	"cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
c59e1b4d TT	486	"consoledev=ttyS0\0" \
	487	"ramdiskaddr=2000000\0" \
	488	"ramdiskfile=uramdisk\0" \
	489	"fdtaddr=c00000\0" \
	490	"fdtfile=p1022ds.dtb\0" \
	491	"bdev=sda3\0" \
	492	"diuregs=md e002c000 1d\0" \
	493	"dium=mw e002c01c\0" \
	494	"diuerr=md e002c014 1\0" \
	495	"othbootargs=diufb=15M video=fslfb:1280x1024-32@60,monitor=0 tty0\0" \
	496	"monitor=0-DVI\0"
	497
	498	#define CONFIG_HDBOOT \
	499	"setenv bootargs root=/dev/$bdev rw " \
	500	"console=$consoledev,$baudrate $othbootargs;" \
	501	"tftp $loadaddr $bootfile;" \
	502	"tftp $fdtaddr $fdtfile;" \
	503	"bootm $loadaddr - $fdtaddr"
	504
	505	#define CONFIG_NFSBOOTCOMMAND \
	506	"setenv bootargs root=/dev/nfs rw " \
	507	"nfsroot=$serverip:$rootpath " \
	508	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
	509	"console=$consoledev,$baudrate $othbootargs;" \
	510	"tftp $loadaddr $bootfile;" \
	511	"tftp $fdtaddr $fdtfile;" \
	512	"bootm $loadaddr - $fdtaddr"
	513
	514	#define CONFIG_RAMBOOTCOMMAND \
	515	"setenv bootargs root=/dev/ram rw " \
	516	"console=$consoledev,$baudrate $othbootargs;" \
	517	"tftp $ramdiskaddr $ramdiskfile;" \
	518	"tftp $loadaddr $bootfile;" \
	519	"tftp $fdtaddr $fdtfile;" \
	520	"bootm $loadaddr $ramdiskaddr $fdtaddr"
	521
	522	#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
	523
	524	#endif